JPH06112204A - Semiconductor device and its production - Google Patents

Semiconductor device and its production

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Publication number
JPH06112204A
JPH06112204A JP26183892A JP26183892A JPH06112204A JP H06112204 A JPH06112204 A JP H06112204A JP 26183892 A JP26183892 A JP 26183892A JP 26183892 A JP26183892 A JP 26183892A JP H06112204 A JPH06112204 A JP H06112204A
Authority
JP
Japan
Prior art keywords
wiring
insulating film
semiconductor device
insulation film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26183892A
Other languages
Japanese (ja)
Other versions
JP3049964B2 (en
Inventor
Ryuichi Okamura
龍一 岡村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4261838A priority Critical patent/JP3049964B2/en
Publication of JPH06112204A publication Critical patent/JPH06112204A/en
Application granted granted Critical
Publication of JP3049964B2 publication Critical patent/JP3049964B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To prevent peeling-off between an Au wiring and an insulation film by forming and irregular surface on the Au wiring of a semiconductor substrate. CONSTITUTION:After an Au wiring 200 is formed on a substrate 100 through plating method, etc., and it is applied with a heat treatment at 300-400 deg.C in an N2 atmosphere for 30-60min, the irregularity of the Au surface is eliminated to form a smooth surface, and a resist or an insulation film is patterned and the Au is etched by using it as a mask. Then, openings are made in the wiring 200 to form holes 201 of at least 0.2mum in depth, and it is applied with surface treatment by a diluted aqua regia of a composition ratio of HNO3:HCl:H2O =1:3:10 for about 1-2min, so that the fine irregularity on the Au surface is emphasized and the projecting and recessed parts are formed on the surface of the wiring 200. Therefore, if an organic or inorganic coating film is formed as an insulation film 300, the contact area and contact strength between an Au and the insulation film will be increased, resulting in providing a semiconductor device where the insulation film 300 on the wiring 200 can be prevented from being peeled off.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
Ａｕ配線の表面の形状に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the surface shape of Au wiring.

【０００２】[0002]

【従来の技術】従来例を図５（ａ）〜（ｃ）を参照して
説明する。まず半導体装置が形成された基板１００上に
Ａｕ配線２００を形成する。この時、Ａｕ配線２００を
メッキ法にて形成すると、Ａｕ配線表面には図５（ａ）
のように凹凸が生じる。2. Description of the Related Art A conventional example will be described with reference to FIGS. First, the Au wiring 200 is formed on the substrate 100 on which the semiconductor device is formed. At this time, when the Au wiring 200 is formed by the plating method, the Au wiring 200 is formed on the surface of the Au wiring as shown in FIG.
Unevenness occurs.

【０００３】次にＡｕ配線２００にＮ2 雰囲気中で３０
０〜４００℃で３０〜６０分程度の熱処理を施す。メッ
キ法にて形成されたＡｕは熱処理を行うと、体積収縮を
起こし、さらに表面の凹凸が緩和され、図５（ｂ）のよ
うに滑らかな表面形状となる。熱処理前にＡｕ配線上に
絶縁膜を形成すると、後工程の熱処理によりＡｕ配線が
収縮して、Ａｕ配線上の絶縁膜が剥がれてしまうので、
通常は熱処理を施しＡｕ配線を収縮させてから絶縁膜を
形成する。Next, the Au wiring 200 is subjected to 30 in an N 2 atmosphere.
Heat treatment is performed at 0 to 400 ° C. for about 30 to 60 minutes. When the heat treatment is performed on Au formed by the plating method, volume contraction occurs, and the surface irregularities are alleviated, so that the surface has a smooth surface shape as shown in FIG. 5B. If the insulating film is formed on the Au wiring before the heat treatment, the Au wiring contracts due to the heat treatment in the subsequent step, and the insulating film on the Au wiring is peeled off.
Generally, heat treatment is performed to shrink the Au wiring, and then the insulating film is formed.

【０００４】次にＣＶＤ法等でＳｉＯあるいはＳｉＮ等
の無機膜を形成するか、有機あるいは無機の塗布膜を形
成して絶縁膜３００とする。このとき図５（ｃ）のよう
にＡｕ配線上の絶縁膜の剥がれ４００が発生する。Next, an inorganic film such as SiO or SiN is formed by the CVD method or an organic or inorganic coating film is formed to form the insulating film 300. At this time, peeling 400 of the insulating film on the Au wiring occurs as shown in FIG.

【０００５】[0005]

【発明が解決しようとする課題】前述した従来例におい
て、Ａｕ表面形状が滑らかになりＡｕ配線と絶縁膜の密
着面積及び密着強度が低下することにより、Ａｕ配線上
の絶縁膜の剥がれが発生し、歩留低下を招くという問題
点を有する。In the above-mentioned conventional example, the Au surface shape becomes smooth and the adhesion area and adhesion strength between the Au wiring and the insulating film are reduced, so that the insulating film on the Au wiring is peeled off. However, there is a problem in that the yield is reduced.

【０００６】本発明の目的は、Ａｕ配線と絶縁膜の剥が
れを防止した半導体装置及びその製造方法を提供するこ
とにある。An object of the present invention is to provide a semiconductor device in which the Au wiring and the insulating film are prevented from peeling off, and a manufacturing method thereof.

【０００７】[0007]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、Ａｕ配線を有する半導
体装置であって、Ａｕ配線は、絶縁膜で被覆された表面
に絶縁膜との密着面積及び密着強度を増加させるための
凹凸を有するものである。In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having an Au wiring, wherein the Au wiring has a surface covered with an insulating film and an insulating film. It has irregularities for increasing the adhesion area and the adhesion strength.

【０００８】また、前記Ａｕ配線上に、０．２μｍ以上
の深さのホールを有するものである。Further, the Au wiring has a hole having a depth of 0.2 μm or more.

【０００９】また、本発明に係る半導体装置の製造方法
は、Ａｕ配線工程と、熱処理工程と、凹凸処理工程と、
絶縁膜形成工程とを有し、半導体装置にＡｕ配線を形成
する半導体装置の製造方法であって、Ａｕ配線工程は、
少なくとも半導体基板上にＡｕ配線を形成するものであ
り、熱処理工程は、前記Ａｕ配線に熱処理を施すもので
あり、凹凸処理工程は、熱処理された前記Ａｕ配線の表
面に凹凸を形成するものであり、絶縁膜形成工程は、凹
凸が形成されたＡｕ配線上に絶縁膜を形成するものであ
る。The method of manufacturing a semiconductor device according to the present invention includes an Au wiring step, a heat treatment step, an unevenness treatment step,
A method of manufacturing a semiconductor device, the method comprising: forming an Au film on a semiconductor device, the method comprising:
At least an Au wiring is formed on a semiconductor substrate, a heat treatment step is a heat treatment for the Au wiring, and a concavo-convex treatment step is for forming irregularities on a surface of the heat-treated Au wiring. In the insulating film forming step, an insulating film is formed on the Au wiring having the unevenness.

【００１０】また、前記半導体装置の製造方法であっ
て、前記Ａｕ配線上に、０．２μｍ以上の深さのホール
を形成する工程を付加したものである。The method of manufacturing the semiconductor device further includes a step of forming a hole having a depth of 0.2 μm or more on the Au wiring.

【００１１】[0011]

【作用】半導体基板１００上のＡｕ配線２００の表面に
凹凸を形成することにより、密着面積及び密着強度を増
加させＡｕ配線１００と絶縁膜３００の剥がれを防ぐ。By forming irregularities on the surface of the Au wiring 200 on the semiconductor substrate 100, the adhesion area and the adhesion strength are increased to prevent the Au wiring 100 and the insulating film 300 from peeling off.

【００１２】[0012]

【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.

【００１３】（実施例１）図１，図２は、本発明の実施
例１を工程順に示す断面図である。まず図１（ａ）のよ
うに、半導体装置が形成された基板１００上にＡｕ配線
２００をメッキ法等で形成する。次にＡｕ配線２００に
Ｎ2 雰囲気中で３００〜４００℃、３０〜６０分程度の
熱処理を施すと、図１（ｂ）のようにＡｕ表面の凹凸が
緩和され、滑らかな表面形状となる。(Embodiment 1) FIGS. 1 and 2 are sectional views showing Embodiment 1 of the present invention in the order of steps. First, as shown in FIG. 1A, an Au wiring 200 is formed by a plating method or the like on a substrate 100 on which a semiconductor device is formed. Next, when the Au wiring 200 is subjected to a heat treatment at 300 to 400 ° C. for about 30 to 60 minutes in an N 2 atmosphere, the unevenness of the Au surface is relaxed as shown in FIG.

【００１４】次にＨＮＯ3 ：ＨＣｌ：Ｈ2 Ｏ＝１：３：
１０程度の希釈王水にて１〜２分程度の表面処理を行う
と、Ａｕ表面の微細な凹凸が強調され図２（ｃ）のよう
にＡｕ配線２００の表面に凹凸が形成される。その上に
ＣＶＤ法等でＳｉＯあるいはＳｉＮ等の無機膜を形成す
るか、有機あるいは無機の塗布膜を形成して絶縁膜３０
０とする。図２（ｄ）は、ＣＶＤ−ＳｉＯを形成した場
合である。Next, HNO 3 : HCl: H 2 O = 1: 3:
When the surface treatment is performed with diluted aqua regia of about 10 for about 1 to 2 minutes, fine irregularities on the Au surface are emphasized and irregularities are formed on the surface of the Au wiring 200 as shown in FIG. An inorganic film such as SiO or SiN is formed thereon by a CVD method or the like, or an organic or inorganic coating film is formed to form an insulating film 30.
Set to 0. FIG. 2D shows a case where CVD-SiO is formed.

【００１５】このとき、Ａｕ配線１００の表面の凹凸に
より、Ａｕと絶縁膜の密着面積および密着強度が増加し
て、Ａｕ配線上の絶縁膜の剥がれが抑えられる。At this time, due to the unevenness of the surface of the Au wiring 100, the adhesion area and the adhesion strength between Au and the insulating film are increased, and the peeling of the insulating film on the Au wiring is suppressed.

【００１６】従来の剥がれの発生率は、５０μｍ以上の
幅を持ったＡｕ配線上の絶縁膜では８０％以上、５０μ
ｍ以下〜１μｍ程度の幅のＡｕ配線上でも３０％程度あ
ったが、本実施例では剥がれの発生率を、Ａｕ配線の幅
に関係なく、１０％以下に抑えることができる。The conventional peeling rate is 80% or more and 50 μm or more for the insulating film on the Au wiring having a width of 50 μm or more.
Although it was about 30% even on the Au wiring having a width of m or less to about 1 μm, the occurrence rate of peeling can be suppressed to 10% or less regardless of the width of the Au wiring in this embodiment.

【００１７】（実施例２）図３，図４は、本発明の実施
例２を工程順に示す断面図である。まず図３（ａ）のよ
うに、半導体装置が形成された基板１００上にＡｕ配線
２００をメッキ法等で形成する。次にＡｕ配線２００に
Ｎ2 雰囲気中で３００〜４００℃、３０〜６０分程度の
熱処理を施すと、図３（ｂ）のようにＡｕ表面の凹凸が
緩和され、滑らかな表面形状となる。(Embodiment 2) FIGS. 3 and 4 are sectional views showing Embodiment 2 of the present invention in the order of steps. First, as shown in FIG. 3A, the Au wiring 200 is formed by a plating method or the like on the substrate 100 on which the semiconductor device is formed. Next, when the Au wiring 200 is subjected to a heat treatment at 300 to 400 ° C. for about 30 to 60 minutes in an N 2 atmosphere, the unevenness of the Au surface is relaxed and a smooth surface shape is obtained as shown in FIG. 3B.

【００１８】次に、Ａｕ配線１００上にレジストあるい
は絶縁膜をパターニングして、それをマスクとしてＡｕ
のエッチングを行い、図３（ｃ）のようにＡｕ配線を開
口し、０．２μｍ以上の深さのホール２０１を形成す
る。Next, a resist or an insulating film is patterned on the Au wiring 100, and Au is used as a mask.
Etching is performed to open the Au wiring as shown in FIG. 3C, and a hole 201 having a depth of 0.2 μm or more is formed.

【００１９】次にＨＮＯ3 ：ＨＣｌ：Ｈ2 Ｏ＝１：３：
１０程度の希釈王水にて１〜２分程度の表面処理を行う
と、Ａｕ表面の微細な凹凸が強調され図４（ｄ）のよう
にＡｕ配線表面に凹凸が形成される。その上にＣＶＤ法
等でＳｉＯあるいはＳｉＮ等の無機膜を形成するか、有
機あるいは無機の塗布膜を形成して絶縁膜３００とす
る。図４（ｅ）は、有機塗布膜を形成した場合である。Next, HNO 3 : HCl: H 2 O = 1: 3:
When the surface treatment is performed with diluted aqua regia of about 10 for about 1 to 2 minutes, fine irregularities on the Au surface are emphasized and irregularities are formed on the Au wiring surface as shown in FIG. An inorganic film such as SiO or SiN is formed thereon by a CVD method or the like, or an organic or inorganic coating film is formed to form the insulating film 300. FIG. 4E shows a case where an organic coating film is formed.

【００２０】このとき、Ａｕ配線表面のホール及び凹凸
により、実施例１よりもさらにＡｕと絶縁膜の密着面積
および密着強度が増加して、Ａｕ配線上の絶縁膜の剥が
れが抑えられる。特に２０μｍ以上の幅のＡｕ配線上で
は、剥がれの発生率を１％以下に抑えることができる。At this time, due to the holes and the irregularities on the surface of the Au wiring, the adhesion area and adhesion strength between Au and the insulating film are further increased as compared with the first embodiment, and the peeling of the insulating film on the Au wiring is suppressed. Particularly on the Au wiring having a width of 20 μm or more, the occurrence rate of peeling can be suppressed to 1% or less.

【００２１】[0021]

【発明の効果】以上説明したように本発明は、Ａｕ配線
の表面に凹凸が形成されているため、Ａｕと絶縁膜の密
着面積及び密着強度が増加して、Ａｕ配線上の絶縁膜の
剥がれを防止でき、歩留が向上するという効果がある。As described above, according to the present invention, since the unevenness is formed on the surface of the Au wiring, the adhesion area and the adhesion strength between Au and the insulating film are increased, and the insulating film on the Au wiring is peeled off. This has the effect of preventing this and improving the yield.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例１を工程順に示す断面図であ
る。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

【図２】本発明の実施例１を工程順に示す断面図であ
る。FIG. 2 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図３】本発明の実施例２を工程順に示す断面図であ
る。FIG. 3 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図４】本発明の実施例２を工程順に示す断面図であ
る。FIG. 4 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図５】従来例を工程順に示す断面図である。FIG. 5 is a cross-sectional view showing a conventional example in the order of steps.

【符号の説明】[Explanation of symbols]

１００ 基板 ２００ Ａｕ配線 ２０１ ホール ３００ 絶縁膜 ４００ 絶縁膜の剥がれ 100 substrate 200 Au wiring 201 hole 300 insulating film 400 peeling of insulating film

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 Ａｕ配線を有する半導体装置であって、 Ａｕ配線は、絶縁膜で被覆された表面に絶縁膜との密着
面積及び密着強度を増加させるための凹凸を有するもの
であることを特徴とする半導体装置。1. A semiconductor device having an Au wiring, wherein the Au wiring has irregularities on a surface covered with the insulating film for increasing a contact area and a contact strength with the insulating film. Semiconductor device. 【請求項２】 前記Ａｕ配線上に、０．２μｍ以上の深
さのホールを有することを特徴とする請求項１に記載の
半導体装置。2. The semiconductor device according to claim 1, wherein a hole having a depth of 0.2 μm or more is provided on the Au wiring. 【請求項３】 Ａｕ配線工程と、熱処理工程と、凹凸処
理工程と、絶縁膜形成工程とを有し、半導体装置にＡｕ
配線を形成する半導体装置の製造方法であって、 Ａｕ配線工程は、少なくとも半導体基板上にＡｕ配線を
形成するものであり、 熱処理工程は、前記Ａｕ配線に熱処理を施すものであ
り、 凹凸処理工程は、熱処理された前記Ａｕ配線の表面に凹
凸を形成するものであり、 絶縁膜形成工程は、凹凸が形成されたＡｕ配線上に絶縁
膜を形成するものであることを特徴とする半導体装置の
製造方法。3. A semiconductor device comprising an Au wiring step, a heat treatment step, an unevenness treatment step, and an insulating film forming step.
A method of manufacturing a semiconductor device for forming a wiring, wherein the Au wiring step is a step of forming an Au wiring on at least a semiconductor substrate, and the heat treatment step is a step of subjecting the Au wiring to a heat treatment. Is for forming irregularities on the surface of the heat-treated Au wiring, and the insulating film forming step is for forming an insulating film on the Au wiring on which irregularities are formed. Production method. 【請求項４】 請求項３に記載の半導体装置の製造方法
であって、前記Ａｕ配線上に、０．２μｍ以上の深さの
ホールを形成する工程を付加したことを特徴とする半導
体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of forming a hole having a depth of 0.2 μm or more on the Au wiring. Production method.
JP4261838A 1992-09-30 1992-09-30 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3049964B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4261838A JP3049964B2 (en) 1992-09-30 1992-09-30 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4261838A JP3049964B2 (en) 1992-09-30 1992-09-30 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH06112204A true JPH06112204A (en) 1994-04-22
JP3049964B2 JP3049964B2 (en) 2000-06-05

Family

ID=17367450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4261838A Expired - Fee Related JP3049964B2 (en) 1992-09-30 1992-09-30 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3049964B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858936B2 (en) 2002-07-01 2005-02-22 Kabushiki Kaisha Toshiba Semiconductor device having an improved construction in the interlayer insulating film
KR100892338B1 (en) * 2007-10-31 2009-04-08 주식회사 하이닉스반도체 Semiconductor device
CN108028234A (en) * 2015-12-04 2018-05-11 瑞萨电子株式会社 Semiconductor chip, semiconductor devices and electronic device
CN108300999A (en) * 2017-01-11 2018-07-20 佛山市同心珠宝首饰有限公司 A kind of gold ornament surface treatment liquid and its processing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858936B2 (en) 2002-07-01 2005-02-22 Kabushiki Kaisha Toshiba Semiconductor device having an improved construction in the interlayer insulating film
US7144804B2 (en) 2002-07-01 2006-12-05 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
KR100892338B1 (en) * 2007-10-31 2009-04-08 주식회사 하이닉스반도체 Semiconductor device
CN108028234A (en) * 2015-12-04 2018-05-11 瑞萨电子株式会社 Semiconductor chip, semiconductor devices and electronic device
CN108028234B (en) * 2015-12-04 2021-12-31 瑞萨电子株式会社 Semiconductor chip, semiconductor device, and electronic device
CN108300999A (en) * 2017-01-11 2018-07-20 佛山市同心珠宝首饰有限公司 A kind of gold ornament surface treatment liquid and its processing method

Also Published As

Publication number Publication date
JP3049964B2 (en) 2000-06-05

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