JP3049964B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3049964B2 JP3049964B2 JP4261838A JP26183892A JP3049964B2 JP 3049964 B2 JP3049964 B2 JP 3049964B2 JP 4261838 A JP4261838 A JP 4261838A JP 26183892 A JP26183892 A JP 26183892A JP 3049964 B2 JP3049964 B2 JP 3049964B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- semiconductor device
- heat treatment
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
Ａｕ配線の表面の形状に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a surface shape of an Au wiring.
【０００２】[0002]
【従来の技術】従来例を図５（ａ）〜（ｃ）を参照して
説明する。まず半導体装置が形成された基板１００上に
Ａｕ配線２００を形成する。この時、Ａｕ配線２００を
メッキ法にて形成すると、Ａｕ配線表面には図５（ａ）
のように凹凸が生じる。2. Description of the Related Art A conventional example will be described with reference to FIGS. First, the Au wiring 200 is formed on the substrate 100 on which the semiconductor device is formed. At this time, when the Au wiring 200 is formed by the plating method, the surface of the Au wiring 200 is formed as shown in FIG.
As shown in FIG.
【０００３】次にＡｕ配線２００にＮ2 雰囲気中で３０
０〜４００℃で３０〜６０分程度の熱処理を施す。メッ
キ法にて形成されたＡｕは熱処理を行うと、体積収縮を
起こし、さらに表面の凹凸が緩和され、図５（ｂ）のよ
うに滑らかな表面形状となる。熱処理前にＡｕ配線上に
絶縁膜を形成すると、後工程の熱処理によりＡｕ配線が
収縮して、Ａｕ配線上の絶縁膜が剥がれてしまうので、
通常は熱処理を施しＡｕ配線を収縮させてから絶縁膜を
形成する。Next, the Au wiring 200 is placed in an N 2 atmosphere for 30 minutes.
Heat treatment is performed at 0 to 400 ° C. for about 30 to 60 minutes. When heat treatment is performed, Au formed by the plating method causes volume shrinkage, and the surface irregularities are further alleviated, resulting in a smooth surface shape as shown in FIG. 5B. If an insulating film is formed on the Au wiring before the heat treatment, the Au wiring contracts due to the heat treatment in a later step, and the insulating film on the Au wiring is peeled off.
Usually, an insulating film is formed after heat treatment is performed to shrink the Au wiring.
【０００４】次にＣＶＤ法等でＳｉＯあるいはＳｉＮ等
の無機膜を形成するか、有機あるいは無機の塗布膜を形
成して絶縁膜３００とする。このとき図５（ｃ）のよう
にＡｕ配線上の絶縁膜の剥がれ４００が発生する。Next, an inorganic film such as SiO or SiN is formed by a CVD method or the like, or an organic or inorganic coating film is formed to form an insulating film 300. At this time, peeling 400 of the insulating film on the Au wiring occurs as shown in FIG.
【０００５】[0005]
【発明が解決しようとする課題】前述した従来例におい
て、Ａｕ表面形状が滑らかになりＡｕ配線と絶縁膜の密
着面積及び密着強度が低下することにより、Ａｕ配線上
の絶縁膜の剥がれが発生し、歩留低下を招くという問題
点を有する。In the prior art described above, the Au surface shape becomes smooth and the adhesion area and the adhesion strength between the Au wiring and the insulating film are reduced, so that peeling of the insulating film on the Au wiring occurs. In addition, there is a problem that the yield is reduced.
【０００６】本発明の目的は、Ａｕ配線と絶縁膜の剥が
れを防止した半導体装置及びその製造方法を提供するこ
とにある。An object of the present invention is to provide a semiconductor device in which peeling of an Au wiring and an insulating film is prevented and a method of manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、Ａｕ配線を有する半導
体装置であって、Ａｕ配線は、Ａｕ配線上に０．２μｍ
以上の深さのホールを有し、ホール内を含めて絶縁膜で
被覆されたＡｕ配線の表面に、絶縁膜との密着面積及び
密着強度を増加させるための凹凸を有するものである。In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having an Au wiring, wherein the Au wiring has a thickness of 0.2 μm on the Au wiring.
The surface of the Au wiring which has the hole having the above depth and is covered with the insulating film including the inside of the hole has irregularities for increasing the adhesion area and the adhesion strength with the insulating film.
【０００８】[0008]
【０００９】また本発明に係る半導体装置の製造方法
は、Ａｕ配線工程と、熱処理工程と、凹凸処理工程と、
絶縁膜形成工程とを有し、半導体装置にＡｕ配線を形成
する半導体装置の製造方法であって、前記Ａｕ配線工程
は少なくとも半導体基板上にＡｕ配線を形成するもので
あり、前記熱処理工程は前記Ａｕ配線に熱処理を施すも
のであり、前記凹凸処理工程は前記熱処理された前記Ａ
ｕ配線の表面に凹凸を形成するものであり、前記絶縁膜
形成工程は、凹凸が形成されたＡｕ配線上に絶縁膜を形
成するものである。Further, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: an Au wiring step; a heat treatment step;
And an insulating film forming step, a method of manufacturing a semiconductor device for forming a Au wire to a semiconductor device, the Au wiring step is to form a Au wire to at least the semiconductor substrate, the thermal treatment process is the are those subjected to a heat treatment to Au wiring, the a the roughening process step that is the heat treatment
is intended to form the uneven surface of the u wiring, the insulating film forming step is to on the Au wiring irregularities are formed to form an insulating film.
【００１０】また前記Ａｕ配線上に０．２μｍ以上の深
さのホールを形成後に、前記凹凸処理工程を有するもの
である。The method may further comprise the step of forming a hole having a depth of 0.2 μm or more on the Au wiring.
【００１１】[0011]
【作用】半導体基板１００上のＡｕ配線２００の表面に
凹凸を形成することにより、密着面積及び密着強度を増
加させＡｕ配線２００と絶縁膜３００の剥がれを防ぐ。[Action] By forming the irregularities on the surface of the Au wire 200 on the semiconductor substrate 100 to increase the contact area and adhesion strength to prevent peeling of the Au wire 2 00 and the insulating film 300.
【００１２】[0012]
【実施例】次に本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１３】（実施例１）図１，図２は、本発明の実施
例１を工程順に示す断面図である。まず図１（ａ）のよ
うに、半導体装置が形成された基板１００上にＡｕ配線
２００をメッキ法等で形成する。次にＡｕ配線２００に
Ｎ2 雰囲気中で３００〜４００℃、３０〜６０分程度の
熱処理を施すと、図１（ｂ）のようにＡｕ表面の凹凸が
緩和され、滑らかな表面形状となる。(Embodiment 1) FIGS. 1 and 2 are sectional views showing a first embodiment of the present invention in the order of steps. First, as shown in FIG. 1A, an Au wiring 200 is formed on a substrate 100 on which a semiconductor device is formed by a plating method or the like. Next, when the Au wiring 200 is subjected to a heat treatment in an N 2 atmosphere at 300 to 400 ° C. for about 30 to 60 minutes, the irregularities on the Au surface are alleviated as shown in FIG.
【００１４】次にＨＮＯ3 ：ＨＣｌ：Ｈ2 Ｏ＝１：３：
１０程度の希釈王水にて１〜２分程度の表面処理を行う
と、Ａｕ表面の微細な凹凸が強調され図２（ｃ）のよう
にＡｕ配線２００の表面に凹凸が形成される。その上に
ＣＶＤ法等でＳｉＯあるいはＳｉＮ等の無機膜を形成す
るか、有機あるいは無機の塗布膜を形成して絶縁膜３０
０とする。図２（ｄ）は、ＣＶＤ−ＳｉＯを形成した場
合である。Next, HNO 3 : HCl: H 2 O = 1: 3:
When surface treatment is performed for about 1 to 2 minutes with about 10 dilution aqua regia, fine irregularities on the Au surface are emphasized, and irregularities are formed on the surface of the Au wiring 200 as shown in FIG. An inorganic film such as SiO or SiN is formed thereon by CVD or the like, or an organic or inorganic coating film is formed to form an insulating film 30.
Set to 0. FIG. 2D shows a case where CVD-SiO is formed.
【００１５】このとき、Ａｕ配線２００の表面の凹凸に
より、Ａｕと絶縁膜の密着面積および密着強度が増加し
て、Ａｕ配線上の絶縁膜の剥がれが抑えられる。At this time, due to the irregularities on the surface of the Au wiring 200 , the adhesion area and the adhesion strength between Au and the insulating film are increased, and the peeling of the insulating film on the Au wiring is suppressed.
【００１６】従来の剥がれの発生率は、５０μｍ以上の
幅を持ったＡｕ配線上の絶縁膜では８０％以上、５０μ
ｍ以下〜１μｍ程度の幅のＡｕ配線上でも３０％程度あ
ったが、本実施例では剥がれの発生率を、Ａｕ配線の幅
に関係なく、１０％以下に抑えることができる。The conventional rate of peeling is 80% or more for an insulating film on an Au wiring having a width of 50 μm or more and 50 μm or more.
Although it is about 30% even on an Au wiring having a width of about 1 m to 1 m, the occurrence rate of peeling can be suppressed to 10% or less regardless of the width of the Au wiring in this embodiment.
【００１７】（実施例２）図３，図４は、本発明の実施
例２を工程順に示す断面図である。まず図３（ａ）のよ
うに、半導体装置が形成された基板１００上にＡｕ配線
２００をメッキ法等で形成する。次にＡｕ配線２００に
Ｎ2 雰囲気中で３００〜４００℃、３０〜６０分程度の
熱処理を施すと、図３（ｂ）のようにＡｕ表面の凹凸が
緩和され、滑らかな表面形状となる。(Embodiment 2) FIGS. 3 and 4 are sectional views showing a second embodiment of the present invention in the order of steps. First, as shown in FIG. 3A, an Au wiring 200 is formed on a substrate 100 on which a semiconductor device is formed by a plating method or the like. Next, when the Au wiring 200 is subjected to a heat treatment in an N 2 atmosphere at 300 to 400 ° C. for about 30 to 60 minutes, the irregularities on the Au surface are alleviated as shown in FIG.
【００１８】次に、Ａｕ配線１００上にレジストあるい
は絶縁膜をパターニングして、それをマスクとしてＡｕ
のエッチングを行い、図３（ｃ）のようにＡｕ配線を開
口し、０．２μｍ以上の深さのホール２０１を形成す
る。Next, a resist or an insulating film is patterned on the Au wiring 100, and the Au or
Then, an Au wiring is opened as shown in FIG. 3C, and a hole 201 having a depth of 0.2 μm or more is formed.
【００１９】次にＨＮＯ3 ：ＨＣｌ：Ｈ2 Ｏ＝１：３：
１０程度の希釈王水にて１〜２分程度の表面処理を行う
と、Ａｕ表面の微細な凹凸が強調され図４（ｄ）のよう
にＡｕ配線表面に凹凸が形成される。その上にＣＶＤ法
等でＳｉＯあるいはＳｉＮ等の無機膜を形成するか、有
機あるいは無機の塗布膜を形成して絶縁膜３００とす
る。図４（ｅ）は、有機塗布膜を形成した場合である。Next, HNO 3 : HCl: H 2 O = 1: 3:
When surface treatment is performed for about 1 to 2 minutes with about 10 dilution aqua regia, fine irregularities on the Au surface are emphasized, and irregularities are formed on the Au wiring surface as shown in FIG. An inorganic film such as SiO or SiN is formed thereon by a CVD method or the like, or an organic or inorganic coating film is formed as the insulating film 300. FIG. 4E shows a case where an organic coating film is formed.
【００２０】このとき、Ａｕ配線表面のホール及び凹凸
により、実施例１よりもさらにＡｕと絶縁膜の密着面積
および密着強度が増加して、Ａｕ配線上の絶縁膜の剥が
れが抑えられる。特に２０μｍ以上の幅のＡｕ配線上で
は、剥がれの発生率を１％以下に抑えることができる。At this time, due to holes and irregularities on the surface of the Au wiring, the adhesion area and adhesion strength between Au and the insulating film are further increased as compared with the first embodiment, and peeling of the insulating film on the Au wiring is suppressed. In particular, on Au wires having a width of 20 μm or more, the rate of occurrence of peeling can be suppressed to 1% or less.
【００２１】[0021]
【発明の効果】以上説明したように本発明は、Ａｕ配線
の表面に凹凸が形成されているため、Ａｕと絶縁膜の密
着面積及び密着強度が増加して、Ａｕ配線上の絶縁膜の
剥がれを防止でき、歩留が向上するという効果がある。As described above, according to the present invention, since the unevenness is formed on the surface of the Au wiring, the adhesion area and the adhesion strength between Au and the insulating film are increased, and the insulating film on the Au wiring is peeled off. Can be prevented, and the yield is improved.
【図１】本発明の実施例１を工程順に示す断面図であ
る。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in the order of steps.
【図２】本発明の実施例１を工程順に示す断面図であ
る。FIG. 2 is a sectional view showing Example 1 of the present invention in the order of steps.
【図３】本発明の実施例２を工程順に示す断面図であ
る。FIG. 3 is a cross-sectional view showing a second embodiment of the present invention in the order of steps.
【図４】本発明の実施例２を工程順に示す断面図であ
る。FIG. 4 is a sectional view showing Example 2 of the present invention in the order of steps.
【図５】従来例を工程順に示す断面図である。FIG. 5 is a sectional view showing a conventional example in the order of steps.
１００ 基板 ２００ Ａｕ配線 ２０１ ホール ３００ 絶縁膜 ４００ 絶縁膜の剥がれ REFERENCE SIGNS LIST 100 substrate 200 Au wiring 201 hole 300 insulating film 400 peeling of insulating film
Claims (3)
記Ａｕ配線は、前記Ａｕ配線上に０．２μｍ以上の深さ
のホールを有し、前記ホール内を含めて絶縁膜で被覆さ
れた前記Ａｕ配線の表面に、前記絶縁膜との密着面積及
び密着強度を増加させるための凹凸を有することを特徴
とする半導体装置。1. A semiconductor device having an Au wiring, wherein the Au wiring has a hole having a depth of 0.2 μm or more on the Au wiring, and is covered with an insulating film including the inside of the hole. On the surface of the Au wiring, the adhesion area with the insulating film
A semiconductor device having irregularities for increasing the contact strength .
工程と、絶縁膜形成工程とを有し、半導体装置にＡｕ配
線を形成する半導体装置の製造方法であって、 前記Ａｕ配線工程は少なくとも半導体基板上にＡｕ配線
を形成するものであり、前記熱処理工程は前記Ａｕ配線
に熱処理を施すものであり、 前記凹凸処理工程は前記熱処理された前記Ａｕ配線の表
面に凹凸を形成するものであり、 前記絶縁膜形成工程は、凹凸が形成されたＡｕ配線上に
絶縁膜を形成するものであることを特徴とする半導体装
置の製造方法。2. A method of manufacturing a semiconductor device, comprising: an Au wiring step, a heat treatment step, an unevenness processing step, and an insulating film forming step, wherein the Au wiring step is performed on the semiconductor device. At least an Au wiring is formed on a semiconductor substrate, and the heat treatment step is performed on the Au wiring.
Heat treatment is performed on the surface of the Au wiring that has been subjected to the heat treatment, and the insulating film forming step includes forming an insulating film on the Au wiring having the protrusions and depressions. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device;
ホールを形成後に、前記凹凸処理工程を有することを特
徴とする請求項２に記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming the concave / convex portions after forming a hole having a depth of 0.2 μm or more on the Au wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4261838A JP3049964B2 (en) | 1992-09-30 | 1992-09-30 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4261838A JP3049964B2 (en) | 1992-09-30 | 1992-09-30 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06112204A JPH06112204A (en) | 1994-04-22 |
| JP3049964B2 true JP3049964B2 (en) | 2000-06-05 |
Family
ID=17367450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4261838A Expired - Fee Related JP3049964B2 (en) | 1992-09-30 | 1992-09-30 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3049964B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3615205B2 (en) | 2002-07-01 | 2005-02-02 | 株式会社東芝 | Semiconductor device and manufacturing method of semiconductor device |
| KR100892338B1 (en) * | 2007-10-31 | 2009-04-08 | 주식회사 하이닉스반도체 | Semiconductor device |
| CN108028234B (en) * | 2015-12-04 | 2021-12-31 | 瑞萨电子株式会社 | Semiconductor chip, semiconductor device, and electronic device |
| CN108300999A (en) * | 2017-01-11 | 2018-07-20 | 佛山市同心珠宝首饰有限公司 | A kind of gold ornament surface treatment liquid and its processing method |
-
1992
- 1992-09-30 JP JP4261838A patent/JP3049964B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06112204A (en) | 1994-04-22 |
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