JPH06104370A - Lead frame and semiconductor device - Google Patents

Lead frame and semiconductor device

Info

Publication number
JPH06104370A
JPH06104370A JP4249750A JP24975092A JPH06104370A JP H06104370 A JPH06104370 A JP H06104370A JP 4249750 A JP4249750 A JP 4249750A JP 24975092 A JP24975092 A JP 24975092A JP H06104370 A JPH06104370 A JP H06104370A
Authority
JP
Japan
Prior art keywords
lead frame
resin
die stage
semiconductor chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4249750A
Other languages
Japanese (ja)
Inventor
Hiroyuki Kitasako
弘幸 北迫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP4249750A priority Critical patent/JPH06104370A/en
Publication of JPH06104370A publication Critical patent/JPH06104370A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a lead frame capable of avoiding the cracking in a resin due to the generated heat during the packaging step thereof especially on a printed board, etc., in relation to the lead frame having a die stage whereto a semiconductor chip fixed with a bonding material is to be sealed with a resin. CONSTITUTION:Within this lead frame composed of a die stage 21 whereto a semiconductor chip material fixed with a bonding material is to be sealed with a resin as well as support bars 23 holding this die stage 21, trenches 21a in parallel with the direction of the support bars 23 and reaching the same 23 are formed on the surface while films 21b having feeble bond strength onto a resin 33 are to be formed inside the trenches 21a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体チップを接着材
で固定して樹脂により封止されるダイステージを有する
リードフレーム、特にプリント板等への実装時の加熱に
より樹脂にクラックを発生させることのないリードフレ
ームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame having a die stage in which a semiconductor chip is fixed with an adhesive and sealed with a resin, and in particular, cracks are generated in the resin by heating during mounting on a printed board or the like. About leadframes that never happen.

【０００２】[0002]

【従来の技術】次に、従来のリードフレームについて図
２を参照して説明する。図２は、従来のリードフレーム
の説明図であって、図２(a) はリードフレームの要部平
面図、図２(b) は半導体装置の要部側断面図である。2. Description of the Related Art Next, a conventional lead frame will be described with reference to FIG. 2A and 2B are explanatory views of a conventional lead frame, FIG. 2A is a plan view of a main part of the lead frame, and FIG. 2B is a side sectional view of the main part of the semiconductor device.

【０００３】図２(a),(b) で示すように従来のリードフ
レーム10は、表面に半導体チップ31を接着材32 (例え
ば、銀の微粒子をエポキシ系の樹脂に分散させてなる銀
ペースト等) で固定して樹脂33により封止されるダイス
テージ11、このダイステージ11の周辺に配列されたイン
ナーリード12及びダイステージ11を吊るようにして保持
するサポートバー13等で構成されている。As shown in FIGS. 2 (a) and 2 (b), the conventional lead frame 10 has a semiconductor chip 31 on the surface of which an adhesive 32 (for example, a silver paste in which fine silver particles are dispersed in an epoxy resin). Etc.) and is sealed with resin 33, the inner stage 12 arranged around the die stage 11 and the support bar 13 for holding the die stage 11 in a suspended manner. .

【０００４】[0004]

【発明が解決しようとする課題】したがって、半導体装
置 (図２(b) 参照) をプリント板等に実装する際の加熱
により樹脂33内に入り込んだ水分が気体となってその体
積を急激に膨張し、樹脂33にクラックを発生させること
が少なくなかった。Therefore, when the semiconductor device (see FIG. 2 (b)) is mounted on a printed board or the like, the moisture that has entered the resin 33 due to heating becomes a gas and its volume expands rapidly. However, it was not rare that the resin 33 was cracked.

【０００５】本発明は、このような問題を解消するため
になされたものであって、その目的はプリント板等への
実装時における加熱により樹脂にクラックを発生させな
いリードフレームの提供を目的とする。The present invention has been made to solve such a problem, and an object thereof is to provide a lead frame which does not cause cracks in the resin due to heating during mounting on a printed board or the like. .

【０００６】[0006]

【課題を解決するための手段】前記目的は図１に示すよ
うに、表面に半導体チップを接着材で固定して樹脂によ
り封止されるダイステージと、このダイステージを保持
するサポートバーとを含んでなるリードフレームにおい
て、サポートバー23の方向と平行かつこのサポートバー
23に至る溝21a をダイステージ21の表面に設けるととも
に、樹脂33との接着力が弱い被膜21b を溝21a 内に形成
したことを特徴とするリードフレームにより達成され
る。As shown in FIG. 1, the above object is to provide a die stage in which a semiconductor chip is fixed on the surface with an adhesive and sealed with a resin, and a support bar for holding the die stage. In the lead frame that comprises, parallel to the direction of the support bar 23 and
This is achieved by a lead frame characterized in that a groove 21a extending to 23 is provided on the surface of the die stage 21, and a coating 21b having a weak adhesive force with the resin 33 is formed in the groove 21a.

【０００７】[0007]

【作用】本発明のリードフレームは、図１に示すように
ダイステージ21の表面にサポートバー23に至る溝21a を
設けるとともに、この溝21a 内に樹脂33との接着力の弱
い被膜21b を形成している。In the lead frame of the present invention, as shown in FIG. 1, a groove 21a reaching the support bar 23 is provided on the surface of the die stage 21, and a coating 21b having a weak adhesive force with the resin 33 is formed in the groove 21a. is doing.

【０００８】したがって、ダイステージ21の表面に半導
体チップ31を接着材32で接着し、ダイステージ21と半導
体チップ31とを樹脂33で封止して構成した半導体装置を
プリント基板等への実装のために加熱した際に、この樹
脂33に入り込んだ水分は蒸気となって体積を急激に膨張
するものの、この蒸気は樹脂33と被膜21b との界面を剥
離させながら外 (樹脂33の外) に抜けるために、樹脂33
にクラックが発生することはない。Therefore, a semiconductor device constituted by adhering the semiconductor chip 31 to the surface of the die stage 21 with the adhesive 32 and encapsulating the die stage 21 and the semiconductor chip 31 with the resin 33 is mounted on a printed circuit board or the like. When heated for this reason, the water that has entered the resin 33 becomes vapor and expands rapidly in volume, but this vapor is released to the outside (outside the resin 33) while peeling the interface between the resin 33 and the coating film 21b. To escape, resin 33
No cracks will occur in the.

【０００９】[0009]

【実施例】以下、本発明の一実施例のリードフレームに
ついて図１を参照しながら説明する。図１は、本発明の
一実施例のリードフレームの説明図であって、図１(a)
はリードフレームの要部平面図、図１(b) はＡ−Ａ線断
面図、図１(c) は半導体装置の要部側断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lead frame according to an embodiment of the present invention will be described below with reference to FIG. FIG. 1 is an explanatory view of a lead frame according to an embodiment of the present invention, and FIG.
1A is a plan view of a main part of a lead frame, FIG. 1B is a cross-sectional view taken along the line AA, and FIG. 1C is a cross-sectional view of a main part of a semiconductor device.

【００１０】なお、本明細書においては、同一部品、同
一材料等に対しては全図をとおして同じ符号を付与して
ある。図１(a),(b) で示すように本発明の一実施例のリ
ードフレーム20は、図２を参照して説明した従来のリー
ドフレーム10と同様に、ダイステージ21、インナーリー
ド22及びサポートバー23を含んで構成したものである。In the present specification, the same parts, the same materials and the like are designated by the same reference numerals throughout the drawings. As shown in FIGS. 1 (a) and 1 (b), the lead frame 20 according to the embodiment of the present invention is similar to the conventional lead frame 10 described with reference to FIG. The support bar 23 is included.

【００１１】しかしながら、本発明の一実施例のリード
フレーム20のダイステージ21の表面には、サポートバー
23の方向と平行かつこのサポートバー23に至る溝21a を
設けるとともに、この溝21a 内に樹脂33との接着力が弱
い被膜、テフロン膜21b を被着させている。However, on the surface of the die stage 21 of the lead frame 20 of the embodiment of the present invention, the support bar is
A groove 21a parallel to the direction of 23 and extending to the support bar 23 is provided, and a film having a weak adhesive force with the resin 33, a Teflon film 21b, is deposited in the groove 21a.

【００１２】したがって、ダイステージ21の表面に半導
体チップ31を接着材32で固定し、このダイステージ21及
び半導体チップ31とを樹脂33で封止することにより外見
上は図２で説明した従来の半導体装置と何ら変わること
のない半導体装置 (図１(c)参照) を構成することがで
きる。Therefore, the semiconductor chip 31 is fixed to the surface of the die stage 21 with the adhesive material 32, and the die stage 21 and the semiconductor chip 31 are sealed with the resin 33, so that the appearance of the conventional one described with reference to FIG. A semiconductor device (see FIG. 1C) that is no different from the semiconductor device can be formed.

【００１３】ところが、この半導体装置においては、ダ
イステージ21の溝21a 内に被着したテフロン膜21b と溝
21a 内に侵入した樹脂33との接着力が弱い。このため本
発明のリードフレームを使用してなる半導体装置をプリ
ント板等に実装するために加熱した際に、その樹脂33に
入り込んだ水分は蒸気となって体積を急激に膨張するも
のの、樹脂33と被膜21b との界面を剥離させながら外
(樹脂33の外) に抜けるために樹脂33にクラックが発生
することはない。However, in this semiconductor device, the Teflon film 21b deposited in the groove 21a of the die stage 21 and the groove
The adhesive strength with the resin 33 that has penetrated into 21a is weak. Therefore, when the semiconductor device using the lead frame of the present invention is heated to be mounted on a printed board or the like, the moisture that has entered the resin 33 becomes vapor to expand the volume rapidly. While peeling off the interface between the
Since it escapes to the outside of the resin 33, the resin 33 does not crack.

【００１４】[0014]

【発明の効果】以上説明したように本発明は、プリント
板等への実装時の加熱で樹脂にクラックを発生させるこ
とのないリードフレームの提供を可能にする。As described above, the present invention makes it possible to provide a lead frame that does not cause cracks in the resin due to heating during mounting on a printed board or the like.

【００１５】したがって、本発明のリードフレームを採
用してなる半導体装置により電子機器等を構成すれば、
その信頼度が大幅に向上する。Therefore, if an electronic apparatus or the like is constructed by the semiconductor device adopting the lead frame of the present invention,
The reliability is greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】は、本発明の一実施例のリードフレームの説明
図、FIG. 1 is an explanatory diagram of a lead frame according to an embodiment of the present invention,

【図２】は、従来のリードフレームの説明図である。FIG. 2 is an explanatory diagram of a conventional lead frame.

【符号の説明】 10,20 は、リードフレーム、 11,21 は、ダイステージ、 21a は、溝、 21b は、テフロン膜 (被膜) 、 12,22 は、インナーリード、 13,23 は、サポートバー、 31は、半導体チップ、 32は、接着材、 33は、樹脂、[Explanation of symbols] 10,20 is a lead frame, 11,21 is a die stage, 21a is a groove, 21b is a Teflon film (coating), 12,22 is an inner lead, 13,23 is a support bar , 31 is a semiconductor chip, 32 is an adhesive, 33 is a resin,

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 表面に半導体チップを接着材で固定して
樹脂により封止されるダイステージと、このダイステー
ジを保持するサポートバーとを含んでなるリードフレー
ムにおいて、 前記サポートバー(23)の方向と平行かつこのサポートバ
ー(23)に至る溝(21a)を前記ダイステージ(21)の表面に
設けるとともに、前記樹脂(33)との接着力が弱い被膜(2
1b) を前記溝(21a) 内に形成したことを特徴とするリー
ドフレーム。1. A lead frame comprising a die stage in which a semiconductor chip is fixed to the surface with an adhesive and sealed with a resin, and a support bar for holding the die stage, wherein the support bar (23) comprises: A groove (21a) parallel to the direction and reaching the support bar (23) is provided on the surface of the die stage (21), and a film (2) having a weak adhesive force with the resin (33) is provided.
A lead frame characterized in that 1b) is formed in the groove (21a). 【請求項２】 請求項１記載のリードフレームのダイス
テージ(21)に搭載した半導体チップ(31)を樹脂(33)で封
止してなることを特徴とする半導体装置。2. A semiconductor device, characterized in that a semiconductor chip (31) mounted on the die stage (21) of the lead frame according to claim 1 is sealed with a resin (33).
JP4249750A 1992-09-18 1992-09-18 Lead frame and semiconductor device Withdrawn JPH06104370A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4249750A JPH06104370A (en) 1992-09-18 1992-09-18 Lead frame and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4249750A JPH06104370A (en) 1992-09-18 1992-09-18 Lead frame and semiconductor device

Publications (1)

Publication Number Publication Date
JPH06104370A true JPH06104370A (en) 1994-04-15

Family

ID=17197669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4249750A Withdrawn JPH06104370A (en) 1992-09-18 1992-09-18 Lead frame and semiconductor device

Country Status (1)

Country Link
JP (1) JPH06104370A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100377346C (en) * 2004-12-23 2008-03-26 旺宏电子股份有限公司 Encapsulation piece

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100377346C (en) * 2004-12-23 2008-03-26 旺宏电子股份有限公司 Encapsulation piece

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