JPH03191552A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03191552A JPH03191552A JP1332066A JP33206689A JPH03191552A JP H03191552 A JPH03191552 A JP H03191552A JP 1332066 A JP1332066 A JP 1332066A JP 33206689 A JP33206689 A JP 33206689A JP H03191552 A JPH03191552 A JP H03191552A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- internal
- semiconductor element
- water
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000010409 thin film Substances 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 13
- 229920005989 resin Polymers 0.000 claims abstract description 13
- 239000000853 adhesive Substances 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 6
- 239000010408 film Substances 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000035939 shock Effects 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 238000004299 exfoliation Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 1
- 239000012528 membrane Substances 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000005219 brazing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、 導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device, Regarding conductor devices.
特に樹脂封止型中
〔従来の技術〕
従来、樹脂封止型半導体装置は、第４図に示すように、
銀ペースト等のろう材４０で、半導体素子搭載部３０上
に固着された半導体素子１４を金線などの金属細線１７
で、内部リード３２と電気的に接続した後、モールド樹
脂１８により封止していた。Particularly in resin-sealed type semiconductor devices [Prior art] Conventionally, resin-sealed semiconductor devices are as shown in FIG.
The semiconductor element 14 fixed on the semiconductor element mounting part 30 with a brazing material 40 such as silver paste is bonded to a thin metal wire 17 such as a gold wire.
After electrically connecting with the internal leads 32, the molding resin 18 was used to seal it.
上述した従来の半導体装置では、プリント基板への実装
時における熱ショックにより、半導体素子搭載部と樹脂
の界面に溜まった水分が気化・膨張するため、界面の剥
離や樹脂のクラックが生じる欠点がある。The above-mentioned conventional semiconductor devices have the disadvantage that moisture accumulated at the interface between the semiconductor element mounting area and the resin evaporates and expands due to thermal shock during mounting on a printed circuit board, resulting in delamination at the interface and cracks in the resin. .
特に、近年要求が高まっている載面実装型パッケージで
は、上記の欠点に伴う品質劣化は深刻な問題になってい
る。Particularly in surface mount packages, for which demand has been increasing in recent years, quality deterioration due to the above-mentioned drawbacks has become a serious problem.
本発明の目的は、半導体素子搭載部と樹脂界面の剥離や
樹脂のクラックに伴う品質劣化のない半導体装１ｔを提
供することにある。An object of the present invention is to provide a semiconductor device 1t that is free from deterioration in quality due to peeling between the semiconductor element mounting portion and the resin interface and cracks in the resin.
本発明は、モールド樹脂により封止される半導体装置に
おいて、少なくとも１本の半導体素子搭載用内部リード
と、該内部リード上面に位置する薄膜と、前記内部リー
ド下面に位置する透水性薄膜と、前記内部リードと前記
薄膜と前記透水性薄膜とによって前記半導体素子の下部
く形成された排水腔とを有し、該排水腔が外部へ通じる
空間を治している。The present invention provides a semiconductor device sealed with a molding resin, including at least one internal lead for mounting a semiconductor element, a thin film located on the upper surface of the internal lead, a water permeable thin film located on the lower surface of the internal lead, and a thin film located on the lower surface of the internal lead. The semiconductor device has a drainage cavity formed under the semiconductor element by an internal lead, the thin film, and the water-permeable thin film, and the drainage cavity defines a space leading to the outside.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例のリードフレームの平面
図、第２図（ａｌ 、 （ｂ）は本発明の第１の実施例
の縦断面図及びＡ−Ａ’ｉ断面図である。FIG. 1 is a plan view of a lead frame according to a first embodiment of the present invention, and FIGS. be.
第１の実施例は、第１図及び第２図（ａｌ 、 （ｂｌ
に示すように、リードフレーム１１の２本の半導体素子
搭載用内部リード１２Ａに囲まれた面を榎うように、両
面接着剤を有するＰＡ１６Ｂを内部リード１２Ａの上面
に１透水性薄膜１５を内部リード１２Ａの下面に貼る。The first embodiment is shown in FIGS. 1 and 2 (al, (bl)
As shown in the figure, a water-permeable thin film 15 is coated on the top surface of the internal leads 12A with PA16B having double-sided adhesive so as to cover the surface of the lead frame 11 surrounded by the two internal leads 12A for mounting semiconductor elements. Paste it on the bottom surface of lead 12A.
その際、排水腔１９をふさぐことのないようにする。ま
た、内部リード１２Ａに囲まれた面をすき間なく榎うこ
とが重要である。At that time, be careful not to block the drainage cavity 19. Further, it is important to cover the surface surrounded by the internal leads 12A without any gaps.
その後、内部リード１２Ａの上面に貼られた膜１６Ｂの
接着面１６Ａを介して半導体素子１４を固着し、金属側
ａ１７により半導体素子１４と外部リード１３に接続す
る内部リード１２Ｂを電気的に接続し、さらに、モール
ド樹脂１８で封止する。Thereafter, the semiconductor element 14 is fixed via the adhesive surface 16A of the film 16B attached to the upper surface of the internal lead 12A, and the internal lead 12B connected to the semiconductor element 14 and the external lead 13 is electrically connected by the metal side a17. , and further sealed with mold resin 18 .
内部リード１２Ａ上の膜１６Ｂ及び透水性薄膜１５は、
内部リード１２Ａとの接着性、樹脂との密着性が良好な
ものであれは、絶縁性でも導電性でも構わない。The membrane 16B and the water permeable thin membrane 15 on the internal lead 12A are
It may be insulative or conductive as long as it has good adhesion to the internal lead 12A and good adhesion to the resin.
第３図は本発明の第２の実施例のリードフレームの平面
図である。FIG. 3 is a plan view of a lead frame according to a second embodiment of the present invention.
第２の実施例は、第３図に示すように、膜及び透水性薄
膜が貼りつけられる内部リード２２Ａが入りくんだ構造
をしているため、膜との接着面積が増し、接着力が向上
するという利点がある。As shown in Fig. 3, the second embodiment has a structure in which the internal lead 22A to which the membrane and water-permeable thin membrane are attached is inserted, increasing the adhesive area with the membrane and improving adhesive strength. There is an advantage to doing so.
また、排水腔となる空間が樹脂封止の際、押しつぶされ
てしまうのを防ぐことができる。Moreover, it is possible to prevent the space serving as the drainage cavity from being crushed during resin sealing.
以上説明したように本発明は、半導体素子搭載用内部リ
ードとこの内部リード上面に有する膜とこの内部リード
下面に有する透水性薄膜により半導体素子の下部に形成
された排水腔を有し、該排水腔が外部に通ずる空間を有
することにより、プリント基板に実装する際の熱ショッ
クにより発生する水蒸気をパッケージ外部に排出し、パ
ッケージ内部に発生するクラックや界面剥離の欠陥を防
止でき、品質を向上させることができる効果がある。As explained above, the present invention has a drainage cavity formed under the semiconductor element by an internal lead for mounting a semiconductor element, a film provided on the upper surface of this internal lead, and a water-permeable thin film provided on the lower surface of this internal lead. By having a space that communicates with the outside, water vapor generated by thermal shock during mounting on a printed circuit board can be discharged to the outside of the package, preventing defects such as cracks and interfacial peeling that occur inside the package, and improving quality. There is an effect that can be done.
第１図は本発明の第１の実施例のリードフレームの平面
図、第２図（ａｌ 、 （ｂｌは本発明の第１の実施例
の縦断面図及びＡ−Ａ’線断面、第３図は本発明の第２
の実施例のリードフレームの平面図、第４図は従来の半
導体装置の一例の縦断面図である。
１１．２１・・・リードフレーム、１２Ａ、１２Ｂ。
２２Ａ、２２Ｂ、３２ ・・・内部リード、 １３，
２３゜３３・・・外部リード、１４・・・半導体素子、
１５・・・透水性薄膜、１６Ａ、１６Ｃ・・・接着面、
１６Ｂ・・・膜、１７・・・金楓細線、１８・・・モー
ルド樹脂、１９・・・排水腔、３０・・・半導体素子搭
載部、４０・・・ろう材。FIG. 1 is a plan view of a lead frame according to a first embodiment of the present invention, FIGS. The figure shows the second aspect of the present invention.
FIG. 4 is a plan view of the lead frame of the embodiment, and FIG. 4 is a longitudinal sectional view of an example of a conventional semiconductor device. 11.21...Lead frame, 12A, 12B. 22A, 22B, 32...internal lead, 13,
23°33...External lead, 14...Semiconductor element,
15...Water permeable thin film, 16A, 16C...Adhesive surface,
16B... Membrane, 17... Gold maple thin wire, 18... Mold resin, 19... Drainage cavity, 30... Semiconductor element mounting portion, 40... Brazing material.
Claims (1)
なくとも１本の半導体素子搭載用内部リードと、該内部
リード上面に位置する薄膜と、前記内部リード下面に位
置する透水性薄膜と、前記内部リードと前記薄膜と前記
透水性薄膜とによつて前記半導体素子の下部に形成され
た排水腔とを有し、該排水腔が外部へ通じる空間を有す
ることを特徴とする半導体装置。In a semiconductor device sealed with a mold resin, at least one internal lead for mounting a semiconductor element, a thin film located on the upper surface of the internal lead, a water-permeable thin film located on the lower surface of the internal lead, the internal lead and the A semiconductor device comprising a drainage cavity formed under the semiconductor element by a thin film and the water-permeable thin film, and the drainage cavity has a space communicating with the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1332066A JPH03191552A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1332066A JPH03191552A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03191552A true JPH03191552A (en) | 1991-08-21 |
Family
ID=18250767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1332066A Pending JPH03191552A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03191552A (en) |
-
1989
- 1989-12-20 JP JP1332066A patent/JPH03191552A/en active Pending
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