JPH05166967A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05166967A
JPH05166967A JP3336791A JP33679191A JPH05166967A JP H05166967 A JPH05166967 A JP H05166967A JP 3336791 A JP3336791 A JP 3336791A JP 33679191 A JP33679191 A JP 33679191A JP H05166967 A JPH05166967 A JP H05166967A
Authority
JP
Japan
Prior art keywords
plating layer
printed wiring
semiconductor device
section
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3336791A
Other languages
Japanese (ja)
Other versions
JP2712967B2 (en
Inventor
Kazufumi Terachi
和文 寺地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3336791A priority Critical patent/JP2712967B2/en
Publication of JPH05166967A publication Critical patent/JPH05166967A/en
Application granted granted Critical
Publication of JP2712967B2 publication Critical patent/JP2712967B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PURPOSE:To enable a printed wiring to be protected against disconnection at an environmental test or the like by a method wherein a nickel plating layer and a gold plating layer which cove a copper wiring and a resist layer which covers a record surface are provided. CONSTITUTION:A semiconductor device is equipped with a printed wiring board 3 which includes a first surface section composed of semiconductor mounting 1 and a wire bonding section 2, a second surface section of the rest, and a copper wiring section 4 laid or the second surface section. Especially, a nickel plating layer 6 and a gold plating layer 7 covering the copper wiring section 4 and a solder resist 5 which covers the second surface section are provided. A sealing frame 10 used for sealing up the upside of the printed wiring board 3 is arranged on the nickel plating layer 6 and the gold plating layer 7. By this setup, the disconnection of the copper wiring 4 caused by a thermal expansion coefficient difference between sealing resin 9 and the printed wiring board 3 can be prevented, and an environmental test can be enhanced in reliability.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
プラスチック・ピン・グリッド・アレイ型の半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a plastic pin grid array type semiconductor device.

【０００２】[0002]

【従来の技術】従来、この種の半導体装置は、半導体素
子搭載部とワイヤーボンディング部を有する印刷配線基
板上に半導体素子を搭載後、封止枠が樹脂で接着され、
エポキシ樹脂、シリコーン樹脂等の樹脂で封止後、封止
部を覆う様にアルミニウム製の金属キャップが樹脂で接
着されていた。2. Description of the Related Art Conventionally, in this type of semiconductor device, after mounting a semiconductor element on a printed wiring board having a semiconductor element mounting portion and a wire bonding portion, a sealing frame is bonded with a resin,
After sealing with a resin such as an epoxy resin or a silicone resin, a metal cap made of aluminum was adhered with the resin so as to cover the sealing portion.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体装置では、印刷配線基板上の銅配線部上
に封止枠が接着されているので、温度サイクルやＰＣＴ
（プレッシャー・クッカー・テスト）等の環境試験で印
刷配線が断線する不良があった。However, in the above-mentioned conventional semiconductor device, since the sealing frame is adhered on the copper wiring portion on the printed wiring board, the temperature cycle and the PCT are reduced.
There was a defect that the printed wiring was broken in the environmental test such as (pressure cooker test).

【０００４】そこで、本発明の技術的課題は、上記欠点
に鑑み、環境試験等で印刷配線が断線することのない半
導体装置を提供することである。In view of the above-mentioned drawbacks, a technical object of the present invention is to provide a semiconductor device in which printed wiring is not broken in an environmental test or the like.

【０００５】[0005]

【課題を解決するための手段】本発明によれば、半導体
搭載部とワイヤーボンディング部とを有する第１の表面
部と、残部である第２の表面部と、前記第１及び第２の
表面部に配線された銅配線部とを含む印刷配線基盤を有
する半導体装置において、前記銅配線部を覆うニッケル
めっき層及び金めっき層と、前記第２の表面部を覆うソ
ルダーレジストとを有することを特徴とする半導体装置
が得られる。According to the present invention, a first surface portion having a semiconductor mounting portion and a wire bonding portion, a second surface portion that is the remaining portion, and the first and second surfaces are provided. In a semiconductor device having a printed wiring board including a copper wiring portion wired to a portion, a nickel plating layer and a gold plating layer covering the copper wiring portion and a solder resist covering the second surface portion are provided. A characteristic semiconductor device can be obtained.

【０００６】また、本発明によれば、請求項１の半導体
装置において、前記印刷配線基盤上を封止するための封
止枠を、少なくとも前記ニッケルめっき層及び金めっき
層上に配することを特徴とする半導体装置が得られる。According to the present invention, in the semiconductor device of claim 1, a sealing frame for sealing the printed wiring board is provided at least on the nickel plating layer and the gold plating layer. A characteristic semiconductor device can be obtained.

【０００７】即ち、本発明の半導体装置は、半導体素子
搭載部、ワイヤーボンディング部を有する印刷配線基板
上に半導体素子を搭載後、封止枠が樹脂で接着されてエ
ポキシ樹脂、シリコーン樹脂等の樹脂で封止後、封止部
を覆う様にアルミニウム製の金属キャップが樹脂で接着
されたプラスチック・ピン・グリッド・アレイ型の半導
体装置において、前記印刷配線基板上の銅配線上にニッ
ケル、金めっきを行なった後、半導体素子搭載部、ワイ
ヤーボンディング部以外の基板表面をエポキシ樹脂、ポ
リイミド樹脂等のソルダーレジストで被覆した構造とな
っている。That is, according to the semiconductor device of the present invention, after mounting the semiconductor element on the printed wiring board having the semiconductor element mounting portion and the wire bonding portion, the sealing frame is adhered with the resin and the resin such as epoxy resin or silicone resin In a plastic pin grid array type semiconductor device in which a metal cap made of aluminum is adhered with resin so as to cover the sealing part after sealing with nickel, gold plating on the copper wiring on the printed wiring board. After that, the substrate surface other than the semiconductor element mounting portion and the wire bonding portion is covered with a solder resist such as epoxy resin or polyimide resin.

【０００８】[0008]

【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.

【０００９】図１は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

【００１０】半導体素子搭載部１、ワイヤーボンディン
グ部２を有し、エポキシ系ガラス布やポリイミド系ガラ
ス布やトリアジン系ガラス布等から成り、０．８〜３mm
厚の印刷配線基板３の印刷配線である銅配線４上にニッ
ケルめっき部６（５μm ）、金めっき部７（０．５μm
）を施した後、半導体搭載部１、ワイヤーボンディン
グ部２以外の基板表面をエポキシ樹脂、ポリイミド樹脂
等のソルダーレジスト５で被覆されている。このように
銅配線上にニッケル、金めっきを行なったことにより、
環境試験時の応力集中があってもめっきで補強されてい
るので信頼性を向上することができる。It has a semiconductor element mounting portion 1 and a wire bonding portion 2 and is made of epoxy glass cloth, polyimide glass cloth, triazine glass cloth or the like, and has a thickness of 0.8 to 3 mm.
On the copper wiring 4 which is the printed wiring of the thick printed wiring board 3, the nickel plated portion 6 (5 μm) and the gold plated portion 7 (0.5 μm)
2) is applied, the surface of the substrate other than the semiconductor mounting portion 1 and the wire bonding portion 2 is covered with a solder resist 5 such as an epoxy resin or a polyimide resin. By plating nickel and gold on the copper wiring in this way,
Even if there is stress concentration during environmental testing, reliability can be improved because it is reinforced by plating.

【００１１】[0011]

【発明の効果】以上説明したように本発明は、樹脂で封
入される箇所の基板配線を銅配線のでなくニッケル、金
めっきを行ない補強することにより、封入樹脂と基板と
の熱膨張係数の差による配線の断線を防止し、環境試験
の信頼性が向上できるという効果がある。As described above, according to the present invention, the difference in the coefficient of thermal expansion between the encapsulating resin and the substrate is obtained by reinforcing the substrate wiring at the portion sealed with the resin by plating with nickel or gold instead of copper wiring. There is an effect that the disconnection of the wiring due to is prevented and the reliability of the environmental test can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例の断面図。FIG. 1 is a sectional view of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体素子搭載部 ２ ワイヤーボンディング部 ３ 印刷配線基板 ４ 銅配線 ５ ソルダーレジスト ６ ニッケルめっき部 ７ 金めっき部 ８ 半導体素子 ９ 封止樹脂 １０ 封止枠 １１ 金属キャップ １２ 外部リード端子 1 Semiconductor Element Mounting Section 2 Wire Bonding Section 3 Printed Wiring Board 4 Copper Wiring 5 Solder Resist 6 Nickel Plating Section 7 Gold Plating Section 8 Semiconductor Element 9 Sealing Resin 10 Sealing Frame 11 Metal Cap 12 External Lead Terminal

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体搭載部とワイヤーボンディング部
とを有する第１の表面部と、残部である第２の表面部
と、前記第１及び第２の表面部に配線された銅配線部と
を含む印刷配線基盤を有する半導体装置において、 前記銅配線部を覆うニッケルめっき層及び金めっき層
と、 前記第２の表面部を覆うソルダーレジストとを有するこ
とを特徴とする半導体装置。1. A first surface portion having a semiconductor mounting portion and a wire bonding portion, a second surface portion which is the remaining portion, and a copper wiring portion wired on the first and second surface portions. A semiconductor device having a printed wiring board including: a nickel plating layer and a gold plating layer that cover the copper wiring portion; and a solder resist that covers the second surface portion. 【請求項２】 請求項１の半導体装置において、前記印
刷配線基盤上を封止するための封止枠を、少なくとも前
記ニッケルめっき層及び金めっき層上に配することを特
徴とする半導体装置。2. The semiconductor device according to claim 1, wherein a sealing frame for sealing the printed wiring board is provided on at least the nickel plating layer and the gold plating layer.
JP3336791A 1991-12-19 1991-12-19 Semiconductor device Expired - Lifetime JP2712967B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3336791A JP2712967B2 (en) 1991-12-19 1991-12-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3336791A JP2712967B2 (en) 1991-12-19 1991-12-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH05166967A true JPH05166967A (en) 1993-07-02
JP2712967B2 JP2712967B2 (en) 1998-02-16

Family

ID=18302724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3336791A Expired - Lifetime JP2712967B2 (en) 1991-12-19 1991-12-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2712967B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6088233A (en) * 1994-04-28 2000-07-11 Fujitsu Limited Semiconductor device and assembly board having through-holes filled with filling core
US6347037B2 (en) 1994-04-28 2002-02-12 Fujitsu Limited Semiconductor device and method of forming the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3122542U (en) * 2006-04-05 2006-06-15 得欽 何 Mop structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3122542U (en) * 2006-04-05 2006-06-15 得欽 何 Mop structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6088233A (en) * 1994-04-28 2000-07-11 Fujitsu Limited Semiconductor device and assembly board having through-holes filled with filling core
US6184133B1 (en) 1994-04-28 2001-02-06 Fujitsu Limited Method of forming an assembly board with insulator filled through holes
US6347037B2 (en) 1994-04-28 2002-02-12 Fujitsu Limited Semiconductor device and method of forming the same

Also Published As

Publication number Publication date
JP2712967B2 (en) 1998-02-16

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