JPS59207646A - Semiconductor device and lead frame - Google Patents
Semiconductor device and lead frameInfo
- Publication number
- JPS59207646A JPS59207646A JP58081963A JP8196383A JPS59207646A JP S59207646 A JPS59207646 A JP S59207646A JP 58081963 A JP58081963 A JP 58081963A JP 8196383 A JP8196383 A JP 8196383A JP S59207646 A JPS59207646 A JP S59207646A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead
- lead frame
- heat sink
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は樹脂封止型の半導体装置と、これを製造するだ
めのリードフレームの改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device and an improvement in a lead frame for manufacturing the same.
第１図は従来の半導体装置の一例を示す断面図である。 FIG. 1 is a sectional view showing an example of a conventional semiconductor device.
同図において、１はベッド部である。In the figure, 1 is a bed section.
該ベッド部１上には銀−エポキシ系接着剤等のマウント
剤２を介して半導体チッｆ３がマウントされている。こ
の半導体チップ３の表面に形成された内部端子は、デン
ディングワイヤ４を介してベッド部１の周囲に配設され
たリード５に接続されている。そして、ベッド部１、半
導体ベレット３、ビンディングワイヤ４およＵ’）−ド
５の一部はエポキシ樹脂等の樹脂モールド層６で封止さ
れている。また、リード５は樹脂モールド層５の側壁か
ら外部に延出され、下方に折シ曲けられている。A semiconductor chip f3 is mounted on the bed portion 1 via a mounting agent 2 such as a silver-epoxy adhesive. Internal terminals formed on the surface of this semiconductor chip 3 are connected to leads 5 disposed around the bed portion 1 via leading wires 4 . The bed portion 1, the semiconductor pellet 3, the binding wire 4, and a portion of the U'-domain 5 are sealed with a resin mold layer 6 such as epoxy resin. Further, the leads 5 extend outward from the side walls of the resin mold layer 5 and are bent downward.
上記従来の樹脂封止型半導体装置は第２図に示すような
リードフレーム７を用いて製造される。このリードフレ
ーム７は銅あるいはＮｉ／Ｆｅ合金等の導電性金属板を
プレス加工、エツチング加工等によって所定の／４’タ
ーン形状としたものである。第２図のリードフレーム７
では、外枠８によって３つの領域に区画され、夫々の領
域内に同一のパターンが形成されている。即ち、左端の
単位パターンに示すように、夫々の領域の略中夫にはベ
ッド部１が配置され、該ベッド部１はタイバー９１を介
して外枠８に連結され、支持されている。ベッド部１の
周囲には多数のリード５・・・がベッド部を取り囲んで
配設され、該リード５・・・は夫々外枠８に連結されて
いる。The conventional resin-sealed semiconductor device described above is manufactured using a lead frame 7 as shown in FIG. This lead frame 7 is made of a conductive metal plate made of copper or Ni/Fe alloy or the like and formed into a predetermined /4' turn shape by pressing, etching, or the like. Lead frame 7 in Figure 2
In this case, the area is divided into three areas by the outer frame 8, and the same pattern is formed in each area. That is, as shown in the unit pattern at the left end, a bed portion 1 is arranged approximately at the center of each region, and the bed portion 1 is connected to and supported by the outer frame 8 via tie bars 91. A large number of leads 5 are arranged around the bed part 1, surrounding the bed part, and each lead 5 is connected to an outer frame 8.
また、同じ方向に延出されるリード５・・・はタイバー
９２で連結され、該タイバー９２は外枠８に連結されて
いる。このタイバー９．を境にして、リード５・・・は
内部リード５１ と外部リード５２とに分けられている
。Further, the leads 5 extending in the same direction are connected by tie bars 92, and the tie bars 92 are connected to the outer frame 8. This tie bar9. The leads 5 are divided into an internal lead 51 and an external lead 52.
第２図のリードフレームにより第１図の樹脂封止型半導
体装置を製造するには、まず第２図における中間の単位
パターンに示したように、ベッド部１上に半導体チップ
３をマウントする。In order to manufacture the resin-sealed semiconductor device shown in FIG. 1 using the lead frame shown in FIG. 2, the semiconductor chip 3 is first mounted on the bed portion 1 as shown in the middle unit pattern in FIG.
続いて、デンディングワイヤ４で？ンディングパッドと
内部リード５１の先端部との間を接続した後、右端の単
位・母ターンに示すように所定領域を樹脂モールド層６
で封止する。次に、タイバー９１ｍ９＊を切除すると共
に、外部リード５．を外枠８から切シ離した後、分離さ
れた夫々の外部リード５２を所定方向に折シ曲げれば第
１図の構造をもった樹脂封止型半導体装置が得られる。Next up, Dending Wire 4? After connecting the landing pad and the tip of the internal lead 51, a predetermined area is covered with the resin mold layer 6 as shown in the rightmost unit/mother turn.
Seal with. Next, the tie bar 91m9* is cut out, and the external lead 5. After separating from the outer frame 8, each separated external lead 52 is bent in a predetermined direction to obtain a resin-sealed semiconductor device having the structure shown in FIG.
このように、リードフレームは半導体チップ３とリード
５とを所定の位置関係に保持し、特にデンディングワイ
ヤ４による接続を確実に行々う機能を有するもので、樹
脂封止型半導体装置を製造するだめの直接的な器具に類
するものである。As described above, the lead frame has the function of holding the semiconductor chip 3 and the leads 5 in a predetermined positional relationship, and in particular, ensuring the connection by the ending wires 4, and is useful for manufacturing resin-sealed semiconductor devices. It is similar to the direct instrument of sudame.
なお、ベッド部１を支持しているタイバー９１も樹脂封
止されて第１図の半導体装置内に残存し、かつその切断
面は樹脂モールド層６の端面に露出するととになる。そ
して、このタイバーの露出した切断面は基板バイアスを
加えて動作させる半導体装置においては基板電位を測定
するために利用されている。Note that the tie bars 91 supporting the bed portion 1 are also sealed with resin and remain within the semiconductor device shown in FIG. 1, and their cut surfaces are exposed at the end surfaces of the resin mold layer 6. The exposed cut surface of the tie bar is used to measure the substrate potential in a semiconductor device that is operated by applying a substrate bias.
ところで、上記の樹脂封止型半導体装置は一般に外囲器
の放熱性が低いという問題があった。Incidentally, the resin-sealed semiconductor device described above generally has a problem in that the heat dissipation of the envelope is low.
このため、半導体チップ３の消費電力が大きい場合には
、樹脂モールド層６を熱抵抗の小さい樹脂材料で形成す
るとか、第３図に示すように樹脂モールド層６０頂面に
放熱板１０を接着剤で外付けする等の対策が従来とられ
ている。Therefore, if the power consumption of the semiconductor chip 3 is large, the resin mold layer 6 may be formed of a resin material with low thermal resistance, or the heat sink 10 may be bonded to the top surface of the resin mold layer 60 as shown in FIG. Conventionally, countermeasures have been taken such as applying external agents.
しかしながら、熱抵抗の小さい封止樹脂（例えば商標名
８匹−２１０Ｆ）は一般に熱衝撃によ５−
わいため、樹脂モールド９層６にひび割れを生じ易いと
いう問題があった。However, a sealing resin having a low thermal resistance (for example, trade name 8-210F) is generally susceptible to thermal shock, so there is a problem in that the resin mold layer 9 tends to crack.
また、外付は放熱板１０を採用する場合にも、この放熱
板１０を樹脂モールド層６に強固かつ均一に接着するの
が難かしいため、例えばオートハンドラー等で製品テス
トを行なっているときに落下したりすると、その衝撃で
放熱板１０が剥がれてしまうといった問題があった。Furthermore, even when an external heat sink 10 is used, it is difficult to firmly and uniformly adhere the heat sink 10 to the resin mold layer 6, so it is difficult to adhere the heat sink 10 firmly and uniformly to the resin mold layer 6. If the device is dropped, there is a problem in that the heat sink 10 will peel off due to the impact.
他方、従来のリードフレームでは、インナーリード５１
・・・が片持梁で支持されているためその先端に浮き沈
みを生じたシ、タイバー９１が捻れてベッド部１に傾斜
を生じ易く、その結果、ワイヤ２７２７７時にビンディ
ングミスを生じ易いという問題があった。On the other hand, in the conventional lead frame, the inner lead 51
... is supported by a cantilever beam, which causes ups and downs at the tip, and the tie bar 91 tends to twist and cause the bed section 1 to tilt, resulting in a problem that binding errors are likely to occur when wire 27277 is used. there were.
〔発明の目的〕
本発明は上記事情に鑑みてなされたもので、優れた放熱
性を有し、消費電力の大きなＩＣに適した樹脂封止型半
導体装置と、これを製造するためのリードフレームを提
供することを目的とするものである。[Object of the Invention] The present invention has been made in view of the above circumstances, and provides a resin-encapsulated semiconductor device that has excellent heat dissipation properties and is suitable for ICs with large power consumption, and a lead frame for manufacturing the same. The purpose is to provide the following.
６一
また、本発明のもう一つの目的は、インナーリードおよ
びベッド部の安定した上記リードフレームを提供するこ
とである。6. Another object of the present invention is to provide the above-mentioned lead frame in which the inner leads and the bed portion are stable.
本発明による半導体装置は、金属製の放熱板と、該放熱
板の表面に熱良導性のマウント剤を介して連結された半
導体チップと、該半導体チップから離間してその周囲に
配設され、かつ前記放熱板から電気的に絶縁して設けら
れた金属製のリードと、該リードの一端部と前記半導体
チップとを接続するボンディングワイヤと、前記放熱板
、半導体チップ、リードの一端部およびボンディングワ
イヤを封止する樹脂モールド層とを具備し、前記リード
の他端部が前記樹脂モールド層から外方に延出されてい
ることを特徴とするものである。A semiconductor device according to the present invention includes a metal heat sink, a semiconductor chip connected to the surface of the heat sink via a thermally conductive mounting agent, and a semiconductor chip disposed around the semiconductor chip at a distance from the semiconductor chip. , and a metal lead provided electrically insulated from the heat sink, a bonding wire connecting one end of the lead to the semiconductor chip, the heat sink, the semiconductor chip, one end of the lead, and and a resin mold layer for sealing the bonding wire, and the other end of the lead extends outward from the resin mold layer.
上記本発明による半導体装置は、熱良導性のマウント剤
を介して半導体チップに連結された放熱板が設けられて
いるため、この放熱板の寄与によって優れた熱放散性を
有している。しかも、この放熱板は樹脂モールド層に埋
設されているから従来の外付は放熱板のように脱落する
ことがない。The semiconductor device according to the present invention has a heat dissipation plate connected to the semiconductor chip via a heat-conducting mounting agent, and therefore has excellent heat dissipation due to the contribution of the heat dissipation plate. Furthermore, since this heat sink is embedded in the resin mold layer, it will not fall off like conventional external heat sinks.
一方、本発明によるリードフレームは、リードフレ−ム
を支持固定する金属製の外枠と、該外枠に連結支持され
てこの外枠で囲まれた領域内に延設され、かつその先端
が半導体チップの設置予定領域を取シ囲むように配設さ
れた多数の金属製リードフレ−ムと、該リード・臂ター
ンの片面側に耐熱性合成樹脂からなる絶縁性のフィルム
乃至薄板を介して接着固定され、かつ前記半導体チップ
の設置予定領域を覆って設けられた金属製の放熱板とを
具備し、前記半導体チップの設置予定領域の少なくとも
一部において前記放熱板表面が露出されていることを特
徴とするものである。On the other hand, the lead frame according to the present invention includes a metal outer frame that supports and fixes the lead frame, and a metal outer frame that is connected and supported by the outer frame and extends within an area surrounded by the outer frame, and whose tip end is connected to a metal outer frame that supports and fixes the lead frame. A large number of metal lead frames are arranged to surround the area where the chip is to be installed, and an insulating film or thin plate made of heat-resistant synthetic resin is adhesively fixed to one side of the lead/arm turn. and a metal heat sink provided to cover the area where the semiconductor chip is scheduled to be installed, the surface of the heat sink being exposed in at least a part of the area where the semiconductor chip is expected to be installed. That is.
上記本発明のリードフレームによれば本発明の半導体装
置を製造することができ、また各リードノやターンの先
端部が絶縁性のフィルム乃至薄板を介して前記放熱板に
固定されているから、リード・ぐターン先端部の浮き沈
みといった変形を防止できる。According to the above lead frame of the present invention, the semiconductor device of the present invention can be manufactured, and since the tip of each lead knot or turn is fixed to the heat sink through an insulating film or thin plate, the lead - Prevents deformation such as ups and downs of the tip of the turn.
以下、第４図〜第９図を参照して本発明による半導体装
置およびリードフレームの実施例を説明する。Embodiments of the semiconductor device and lead frame according to the present invention will be described below with reference to FIGS. 4 to 9.
第４図へ）は本発明によるリードフレームの一実施例を
示す平面図であシ、第４図の）はこのリードフレームに
設けられている放熱板部材の平面図、第４図Ｃ）は同図
伯）のＣ−Ｃ線に沿う断面図である。第４図（Ａ）から
明らかなように、このリードフレーム７は第２図の従来
のリードフレームと略同じパターンを有しており、同一
部分には同一の参照番号を付しである。即ち、１はベッ
ド部、５１はインナーリード、５２は外部リード、８は
外枠、９１ｐ９鵞はタイバーである。そして、この実施
例ではベッド部１に開孔部１１１が形成されている。ま
た、図示のように第４図Φ）（Ｃ）の放熱板部材υがベ
ッド部１、タイバー９１およびインナーリード５！の下
面９−
に接着されている。該放熱板部材１２は、第４図（Ｃ）
に示すように銅、鉄、アルミニウムあるいはこれらの合
金等の熱良導体金属でできた放熱板１２１ と、該放熱
板１２！の片面を被覆して設けられたポリイミド樹脂膜
１２２からなシ、ポリイミド樹脂膜１２２にはベッド部
１に形成された開孔部１１１に連通する開孔部１１２が
形成されている。4) is a plan view showing an embodiment of the lead frame according to the present invention, 4) is a plan view of a heat sink member provided on this lead frame, and 4C) is a plan view showing an embodiment of the lead frame according to the present invention. FIG. As is clear from FIG. 4(A), this lead frame 7 has substantially the same pattern as the conventional lead frame shown in FIG. 2, and the same parts are given the same reference numerals. That is, 1 is a bed part, 51 is an inner lead, 52 is an external lead, 8 is an outer frame, and 91p9 is a tie bar. In this embodiment, an opening 111 is formed in the bed portion 1. In addition, as shown in the figure, the heat sink member υ of FIG. It is glued to the lower surface 9- of the. The heat sink member 12 is shown in FIG. 4(C).
As shown in the figure, a heat sink 121 made of a metal with good thermal conductivity such as copper, iron, aluminum, or an alloy thereof, and a heat sink 12! The polyimide resin film 122 is formed with an opening 112 that communicates with the opening 111 formed in the bed portion 1.
上記実施例のリードフレームによる樹脂封止型半導体装
置の製造について説明すれば次の通りである。The manufacturing of the resin-sealed semiconductor device using the lead frame of the above embodiment will be explained as follows.
第５図は、上記実施例のリードフレーム７の断面構造を
示している。まず、ベッド部１およびポリイミド樹脂膜
１２２を貫通する開孔部１１１．１１．で形成された凹
部１ノ内に銀−エポキシ系のマウント剤２を充填し、該
マウント剤２を介して半導体チップ３をベッド部１上に
マウントする。このとき、マウント剤２の量を開孔部１
１内におさまるようにコントロールすることによって、
マウント剤２が第１図、第１０−
３図に示すような形で半導体チップ３の周囲にはみ出す
のを防止できる。続いてワイヤデンデイングヲ行ない、
デンディングワイヤ４によシ半導体チッゾ３とインナー
リード５１の先端部とを接続する。この場合、ベッド部
１とインナーリード５！とは、両者共に？リイミド樹脂
膜１２！上に接着固定されているため相互に浮き沈みを
生じることなく極めて安定で、従ってミスデンディング
を生じることなく確実なデンディングを行なうことがで
きる。第６図はこうして組み立てられた状態を示す断面
図である。FIG. 5 shows the cross-sectional structure of the lead frame 7 of the above embodiment. First, the openings 111.11. A silver-epoxy mounting agent 2 is filled into the concave portion 1 formed in the step 1, and the semiconductor chip 3 is mounted on the bed portion 1 via the mounting agent 2. At this time, the amount of mounting agent 2 is
By controlling it so that it stays within 1,
It is possible to prevent the mounting agent 2 from protruding around the semiconductor chip 3 in the form shown in FIGS. 1 and 10-3. Next, perform wire ending,
The semiconductor chip 3 and the tip of the inner lead 51 are connected to each other by the dending wire 4 . In this case, bed part 1 and inner lead 5! What do you mean, both? Liimide resin film 12! Since they are adhesively fixed on top of each other, they are extremely stable without causing any ups and downs, and therefore, reliable dending can be performed without causing misdending. FIG. 6 is a sectional view showing the thus assembled state.
第７図は、第６図の状態に組み立てた後、従来と同様に
樹脂モールド層６による封止工程およびリードフォーミ
ング工程を経て製造された本発明の一実施例になる樹脂
封止型半導体装置を示している。この場合、図示のよう
に熱良導体であるマウント剤２を介して放熱板１２１が
半導体チップ３に接続されているため、該放熱板１２．
の寄与によって優れた放熱性が得られる。従って、樹脂
モールド層６の熱抵抗性は特に考慮する必要がなく、耐
熱衝撃性の大きい封止樹脂を選択できるため、樹脂モー
ルド層６の割れを防止して信頼性を向上することができ
る。FIG. 7 shows a resin-molded semiconductor device according to an embodiment of the present invention, which is assembled into the state shown in FIG. 6 and then manufactured through a sealing process with a resin mold layer 6 and a lead forming process as in the conventional method. It shows. In this case, since the heat sink 121 is connected to the semiconductor chip 3 via the mounting agent 2, which is a good thermal conductor, as shown in the figure, the heat sink 12.
Excellent heat dissipation is obtained by the contribution of . Therefore, there is no need to particularly consider the heat resistance of the resin mold layer 6, and a sealing resin with high thermal shock resistance can be selected, so that cracking of the resin mold layer 6 can be prevented and reliability can be improved.
また、放熱板１２！が樹脂モールド層６で封止されてい
るため、第３図で説明した従来の外付は放熱板１θのよ
うな脱落を生じない。従って、テスト工程において、従
来放熱板が剥離することによって生じていたトラブルの
防止を図ることができる。Also, heat sink 12! Since it is sealed with the resin mold layer 6, the conventional external attachment explained in FIG. 3 does not fall off like the heat sink 1θ. Therefore, it is possible to prevent troubles that conventionally occur due to peeling of the heat sink during the test process.
更に、上記実施例の樹脂封止型半導体装置では、既述の
ようにマウント剤２が半導体チップ３の周囲にはみ出す
のを防止できるため、耐湿性が向上するといった効果が
得られる。即ち、樹脂モールド層６の外部から侵入した
水分がマウント剤２に接触すると、マウント剤２に含ま
れるハロゲノおよびアルカリイオン〔Ｃ１、Ｎａ 。Furthermore, in the resin-sealed semiconductor device of the above embodiment, as described above, the mounting agent 2 can be prevented from protruding around the semiconductor chip 3, so that the moisture resistance can be improved. That is, when moisture that has entered from the outside of the resin mold layer 6 comes into contact with the mounting agent 2, the halogen and alkali ions [C1, Na2] contained in the mounting agent 2 are removed.
Ｋａ＋等〕が活性化され、半導体チップ３表面のＡｔ配
線やＰａｄの腐蝕を促進することになる。この点におい
て、上記実施例の半導体装置ではマウント剤２のはみ出
しが防止されているから、侵入して来た水分とマウント
剤２との接触が阻止され、従って耐温性の向上が図れる
。Ka+, etc.] are activated, which promotes corrosion of the At wiring and pads on the surface of the semiconductor chip 3. In this respect, in the semiconductor device of the above embodiment, since the mounting agent 2 is prevented from protruding, the intruding moisture is prevented from coming into contact with the mounting agent 2, and therefore the temperature resistance can be improved.
第８図体）は本発明によるリードフレームの他の実施例
を示す平面図であり、第８図Φ）はこのリードフレーム
に設けられている放熱板部材の平面図、第８図Ｃ）は同
図Φ）のＣ−Ｃ線に沿う断面図である。図示のように、
このリードフレーム７はベッド部１が設けられていない
点を除き、総て第４図（Ａ）〜Ｃ）のリードフレームと
同じ構成になっている。Fig. 8 (body) is a plan view showing another embodiment of the lead frame according to the present invention, Fig. 8 (Φ) is a plan view of a heat sink member provided on this lead frame, and Fig. 8 (c) is a plan view of the same. It is a sectional view taken along line CC of figure Φ). As shown,
This lead frame 7 has the same structure as the lead frame shown in FIGS. 4(A) to 4(C), except that the bed portion 1 is not provided.
上記実施例のリードフレームによる樹脂封止型半導体装
置の製造は、半導体チップをポリイミド樹脂膜１１２上
にマウントする点を除き、第５図および第６図について
説明したのと同様にして行なう。この場合、既述したと
同じ効果が得られる他、第６図においてベッド部１が存
在しないことから明らかなように、ポンディングワイヤ
４がベッド部１に接触して生じる所謂ベッドタッチシロ
ートを防止できるという効果が得られる。The resin-sealed semiconductor device using the lead frame of the above embodiment is manufactured in the same manner as described with reference to FIGS. 5 and 6, except that the semiconductor chip is mounted on the polyimide resin film 112. In this case, in addition to obtaining the same effect as described above, as is clear from the absence of the bed part 1 in FIG. You can get the effect that you can.
１３−
第９図は、第８図（Ａ）〜Ｃ）のリードフレームによシ
製造された本発明による樹脂封止型半導体装置の他の実
施例を示す断面図である。図示の構造から明らかなよう
に、この樹脂封止型半導体装置は放熱性、信頼性および
耐湿性等の点で第７図について説明したのと同じ効果を
得ることができる。また、ベッド部１が存在しないこと
から、従来ベッド部１と樹脂モールド層６との熱膨張率
差によシ、特にベッド部１の周縁に沿って発生しやすか
った樹脂モールド層６のひび割れを防止できるという効
果が得られる。13- FIG. 9 is a sectional view showing another embodiment of the resin-sealed semiconductor device according to the present invention manufactured using the lead frame shown in FIGS. 8(A) to 8(C). As is clear from the illustrated structure, this resin-sealed semiconductor device can achieve the same effects as explained with reference to FIG. 7 in terms of heat dissipation, reliability, moisture resistance, and the like. In addition, since the bed part 1 does not exist, cracks in the resin mold layer 6, which conventionally tend to occur particularly along the periphery of the bed part 1 due to the difference in thermal expansion coefficient between the bed part 1 and the resin mold layer 6, can be prevented. The effect is that it can be prevented.
第１０図は第８図（Ａ）〜（Ｃ）の変形例になるリード
フレームの平面図である。このリードフレームでは、ポ
リイミド樹脂膜１２．に形成された開孔部１１鵞が半導
体チップ３の面積よりも大きくなっており、その他の構
成は第８図へ）〜（Ｃ）の実施例と同様である。従って
、このリードフレームによって製造された樹脂封止型半
導体装置は第１１図に示す構造となる。これらの変形例
によっても、本発明の基本的な効果が得られ１４−
ることは明らかである。即ち、ポリイミド樹脂膜１２２
に要求される最低限の機能は、リード５と放熱板１２１
との間を電気的に絶縁することである。従って、ポリ
イミド樹脂膜１２２は最低限インナーリード５１と放熱
板１２１接着面にのみ介在して設けられていればよい。FIG. 10 is a plan view of a lead frame that is a modification of FIGS. 8(A) to 8(C). In this lead frame, a polyimide resin film 12. The area of the opening 11 formed in the semiconductor chip 3 is larger than that of the semiconductor chip 3, and the other configurations are the same as those of the embodiment shown in FIGS. Therefore, a resin-sealed semiconductor device manufactured using this lead frame has the structure shown in FIG. 11. It is clear that the basic effects of the present invention can be obtained even with these modifications. That is, the polyimide resin film 122
The minimum functions required are the leads 5 and the heat sink 121.
It is to electrically insulate between the Therefore, it is sufficient that the polyimide resin film 122 is provided at least only on the bonding surfaces of the inner leads 51 and the heat sink 121.
なお、第４図（Ａ）〜（Ｃ）、第８図（Ａ）〜（Ｃ）お
よび第１０図に示したリードフレームにおいて、何れの
場合にもタイバー９１は設けなくてもよい。Note that in the lead frames shown in FIGS. 4(A) to 4(C), FIGS. 8(A) to 10(C), and FIG. 10, the tie bar 91 may not be provided in any case.
即ち、本発明のり−Ｐフレームでは、従来のようにベッ
ド部１を支持するためのタイバー９１は不要だからであ
る。That is, the glue-P frame of the present invention does not require the tie bars 91 for supporting the bed portion 1 as in the conventional case.
以上詳述したように、本発明によれば放熱性、信頼性お
よび耐湿性に優れた樹脂封止型半導体装置と、これを製
造するための形状安定性に優れたリードフレームを提供
できるものである。As detailed above, according to the present invention, it is possible to provide a resin-sealed semiconductor device with excellent heat dissipation, reliability, and moisture resistance, and a lead frame with excellent shape stability for manufacturing the same. be.
第１図は従来の一般的な樹脂封止型半導体装置を示す断
面図、第２図は従来のリードフレームと、該リードフレ
ームによる樹脂封止型半導体装置の製造工程を説明する
だめの平面図、第３図は放熱性を改善した従来の樹脂封
止型半導体装置を示す断面図、第４図（ト）は本発明の
一実施例になるリードフレームの平面図であシ、第４図
Φ）はこのリードフレームに設けられた放熱板部材の平
面図、第４図（Ｃ）は同図０３）のＣ−Ｃ＠に沿う断面
図、第５図および第６図は第４図（Ａ）〜Ｃ）のリード
フレームによる樹脂封止型半導体装置の製造工程を説明
するだめの断面図、第７図は本発明の一実施例になる樹
脂封止型半導体装置を示す断面図、第８図（Ａ）〜（Ｃ
）は本発明によるリードフレームの他の実施例を示す第
４図■〜（Ｃ）と同様の平面図、第９図は本発明による
樹脂封止型半導体装置の他の実施例を示す断面図、第１
０図は第８図（Ａ）〜（Ｃ）のリードフレームの変形例
を示す平面図、第１１図は第９図の樹脂封止型半導体装
置の変形例を示す断面図である。
１・・・ベッド部、２・・・マウント剤、３・・・半導
体チップ、４・・・？ンディングワイヤ、５・・・リー
ド５Ｉ ・・・インナーリード、５２・・・外部リード
、６・・・樹脂モールド層、？・・・リードフレーム、
８・・・外枠、９１＊９２・・・タイバー、１０・・・
外付は放熱板、１１．ｌｌｔ 、１１２・・・開孔部
、す・・・放熱板部材、１２！・・・放熱板、１２２・
・・、ｊ？ ＩＪイミド樹脂膜。
出願人代理人 弁理士 鈴 江 武 彦１７一FIG. 1 is a sectional view showing a conventional general resin-sealed semiconductor device, and FIG. 2 is a plan view illustrating a conventional lead frame and the manufacturing process of a resin-sealed semiconductor device using the lead frame. , FIG. 3 is a sectional view showing a conventional resin-sealed semiconductor device with improved heat dissipation, and FIG. 4 (G) is a plan view of a lead frame according to an embodiment of the present invention. Φ) is a plan view of the heat dissipation plate member provided on this lead frame, FIG. FIG. 7 is a cross-sectional view illustrating the manufacturing process of a resin-sealed semiconductor device using a lead frame in A) to C), and FIG. 7 is a cross-sectional view showing a resin-sealed semiconductor device according to an embodiment of the present invention. Figure 8 (A)-(C
) is a plan view similar to FIGS. 4 - (C) showing another embodiment of the lead frame according to the present invention, and FIG. 9 is a sectional view showing another embodiment of the resin-sealed semiconductor device according to the present invention. , 1st
0 is a plan view showing a modification of the lead frame shown in FIGS. 8A to 8C, and FIG. 11 is a sectional view showing a modification of the resin-sealed semiconductor device shown in FIG. 9. 1...Bed part, 2...Mounting agent, 3...Semiconductor chip, 4...? Ending wire, 5... Lead 5I... Inner lead, 52... External lead, 6... Resin mold layer, ? ···Lead frame,
8...Outer frame, 91*92...Tie bar, 10...
External heat sink, 11. llt, 112...opening part,...heat sink member, 12! ...heat sink, 122・
..., j? IJ imide resin film. Applicant's agent Patent attorney Takehiko Suzue 171
Claims (2)
マウント剤を介して連結された半導体チップと、該半導
体チップから離間してその周囲に配設され、かつ前記放
熱板から電気的に絶縁して設けられた金属製のリードと
、該リードの一端部と前記半導体チップとを接続するが
ンディングワイヤと、前記放熱板、半導体チップ、リー
ドの一端部およびデンディングワイヤを封止する樹脂モ
ールド層とを具備し、前記リードの他端部が前記樹脂モ
ールド層から外方に延出されていることを特徴とする半
導体装置。(1) A metal heat sink, a semiconductor chip connected to the surface of the heat sink via a thermally conductive mounting agent, and a semiconductor chip disposed around the semiconductor chip and spaced apart from the semiconductor chip, and the heat sink A metal lead provided electrically insulated from the plate, a ending wire connecting one end of the lead to the semiconductor chip, the heat sink, the semiconductor chip, one end of the lead, and the ending wire. a resin mold layer for sealing the semiconductor device, the other end of the lead extending outward from the resin mold layer.
と、該外枠に連結支持されてこの外枠で囲まれた領域内
に延設され、かつその先端が半導体チップの設置予定領
域を取り囲むように配設された多数の金属製リードパタ
ーンと、該リードフレ−ムの片面側に耐熱性合成樹脂か
らなる絶縁性のフィルム乃至薄板を介して接着固定され
、かつ前記半導体チッグの設置予定領域を覆って設けら
れた金属製の放熱板とを具備し、前記半導体チップの設
置予定領域の少なくとも一部において前記放熱板表面が
露出されていることを特徴とするリードフレーム。(2) A metal outer frame that supports and fixes the lead frame, and a metal outer frame that is connected and supported by the outer frame and extends into the area surrounded by the outer frame, and whose tip extends into the area where the semiconductor chip is to be installed. A large number of metal lead patterns arranged to surround the lead frame are adhesively fixed to one side of the lead frame via an insulating film or thin plate made of heat-resistant synthetic resin, and the area where the semiconductor chip is planned to be installed. 1. A lead frame comprising: a metal heat dissipation plate provided to cover the lead frame, the surface of the heat dissipation plate being exposed in at least a portion of an area where the semiconductor chip is to be installed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58081963A JPS59207646A (en) | 1983-05-11 | 1983-05-11 | Semiconductor device and lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58081963A JPS59207646A (en) | 1983-05-11 | 1983-05-11 | Semiconductor device and lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59207646A true JPS59207646A (en) | 1984-11-24 |
Family
ID=13761153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58081963A Pending JPS59207646A (en) | 1983-05-11 | 1983-05-11 | Semiconductor device and lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59207646A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344750A (en) * | 1986-08-12 | 1988-02-25 | Shinko Electric Ind Co Ltd | Manufacture of resin-sealed type semiconductor device and lead frame for semiconductor device |
| US4855868A (en) * | 1987-01-20 | 1989-08-08 | Harding Ade Yemi S K | Preformed packaging arrangement for energy dissipating devices |
| JPH02174152A (en) * | 1988-12-26 | 1990-07-05 | Mitsui High Tec Inc | Semiconductor device and its manufacture |
| JPH03126233A (en) * | 1989-10-02 | 1991-05-29 | Advanced Micro Devices Inc | Integrated circuit package capsuled by plastics and method of making the same |
| US5559369A (en) * | 1989-10-02 | 1996-09-24 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
| US5616958A (en) * | 1995-01-25 | 1997-04-01 | International Business Machines Corporation | Electronic package |
| US5783860A (en) * | 1996-01-31 | 1998-07-21 | Industrial Technology Research Institute | Heat sink bonded to a die paddle having at least one aperture |
| US6261867B1 (en) | 1998-03-13 | 2001-07-17 | Stratedge Corporation | Method of making a package for microelectronic devices using iron oxide as a bonding agent |
-
1983
- 1983-05-11 JP JP58081963A patent/JPS59207646A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344750A (en) * | 1986-08-12 | 1988-02-25 | Shinko Electric Ind Co Ltd | Manufacture of resin-sealed type semiconductor device and lead frame for semiconductor device |
| US4855868A (en) * | 1987-01-20 | 1989-08-08 | Harding Ade Yemi S K | Preformed packaging arrangement for energy dissipating devices |
| JPH02174152A (en) * | 1988-12-26 | 1990-07-05 | Mitsui High Tec Inc | Semiconductor device and its manufacture |
| JPH03126233A (en) * | 1989-10-02 | 1991-05-29 | Advanced Micro Devices Inc | Integrated circuit package capsuled by plastics and method of making the same |
| US5559369A (en) * | 1989-10-02 | 1996-09-24 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
| US5616958A (en) * | 1995-01-25 | 1997-04-01 | International Business Machines Corporation | Electronic package |
| US5728606A (en) * | 1995-01-25 | 1998-03-17 | International Business Machines Corporation | Electronic Package |
| US5783860A (en) * | 1996-01-31 | 1998-07-21 | Industrial Technology Research Institute | Heat sink bonded to a die paddle having at least one aperture |
| US6261867B1 (en) | 1998-03-13 | 2001-07-17 | Stratedge Corporation | Method of making a package for microelectronic devices using iron oxide as a bonding agent |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59207645A (en) | Semiconductor device and lead frame | |
| US5311060A (en) | Heat sink for semiconductor device assembly | |
| US7994633B2 (en) | Substrate for electrical device | |
| TWI272705B (en) | Heat spreader and package structure utilizing the same | |
| JP2978861B2 (en) | Molded BGA type semiconductor device and manufacturing method thereof | |
| US5598031A (en) | Electrically and thermally enhanced package using a separate silicon substrate | |
| KR0158868B1 (en) | Semiconductor device | |
| US20020079570A1 (en) | Semiconductor package with heat dissipating element | |
| JPH0777258B2 (en) | Semiconductor device | |
| JPS60167454A (en) | Semiconductor device | |
| JP2586835B2 (en) | Semiconductor integrated circuit | |
| JPS59207646A (en) | Semiconductor device and lead frame | |
| JP2501953B2 (en) | Semiconductor device | |
| JP2905609B2 (en) | Resin-sealed semiconductor device | |
| JP2908330B2 (en) | Lead frame, semiconductor device, and method of manufacturing semiconductor device | |
| JPH0917910A (en) | Semiconductor device and its manufacture, inspection method and mounting board | |
| JP3052899B2 (en) | Semiconductor device | |
| JP3454192B2 (en) | Lead frame, resin-sealed semiconductor device using the same, and method of manufacturing the same | |
| JPH0563113A (en) | Resin-sealed semiconductor device | |
| KR100373891B1 (en) | Semiconductor device and method of its fabrication | |
| JP3356566B2 (en) | Semiconductor package and mounting method thereof | |
| JPS6089945A (en) | Sealed semiconductor device | |
| JPS635253Y2 (en) | ||
| JPS635250Y2 (en) | ||
| KR0152902B1 (en) | Structure of bottom lead package and method for manufacturing the same |