JPH02174152A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH02174152A JPH02174152A JP32854888A JP32854888A JPH02174152A JP H02174152 A JPH02174152 A JP H02174152A JP 32854888 A JP32854888 A JP 32854888A JP 32854888 A JP32854888 A JP 32854888A JP H02174152 A JPH02174152 A JP H02174152A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead frame
- semiconductor
- lead
- element mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000011347 resin Substances 0.000 claims abstract description 25
- 229920005989 resin Polymers 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims abstract description 10
- 230000017525 heat dissipation Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体装置およびその製造方法に係り、特に半
導体装置の実装に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to packaging of a semiconductor device.
（従来の技術）
半導体素子の実装方法としては、封止用のパッケージ材
料として金属を用いる方法、セラミックを用いる方法、
樹脂を用いる方法等がある。(Prior art) Methods for mounting semiconductor elements include methods using metal as a package material for sealing, methods using ceramics,
There are methods such as using resin.
これらの方法のうち、樹脂を用いる方法では、例えば、
第４図に示すように、リードフレーム１のダイパッド２
に、半導体素子３を固着し、この半導体素子３のポンデ
ィングパッドとリードフレームのインナーリード４とを
金線あるいはアルミ線のボンディングワイＡ７５によっ
て結線し、更にこれらを樹脂パッケージ６内に封止する
ことにより製造されている。Among these methods, methods using resin include, for example,
As shown in FIG. 4, the die pad 2 of the lead frame 1
Then, the semiconductor element 3 is fixed, the bonding pads of the semiconductor element 3 and the inner leads 4 of the lead frame are connected with bonding wires A75 made of gold or aluminum wire, and these are further sealed in the resin package 6. It is manufactured by.
また、ここで用いられるリードフレームは、第５図に１
例を示す如く、半導体素子を搭Ｍ、するためのダイパッ
ド２と、先端が該ダイパッドをとり囲むように延在せし
められたインナーリード４と、該インナーリードとほぼ
直交する方向に延びこれらインナーリードを一体的に支
持するタイバー７と、該タイバーの外側に前記各インナ
ーリードに接続するように配設せしめられたアウターリ
ード８とダイパッド２を支持するサポートパー９とから
構成されている。The lead frame used here is shown in Figure 5.
As shown in the example, there is a die pad 2 for mounting a semiconductor element, an inner lead 4 whose tip extends so as to surround the die pad, and these inner leads which extend in a direction substantially perpendicular to the inner lead. It is composed of a tie bar 7 that integrally supports the die pad 2, an outer lead 8 disposed outside the tie bar so as to be connected to each of the inner leads, and a support par 9 that supports the die pad 2.
このような樹脂による封止方法は、安価でかつ実装作業
性が良好であることから、広く利用されている。Such a resin sealing method is widely used because it is inexpensive and has good mounting workability.
ところで、半導体装置の高集積化に伴い、半導体素子（
以下半導体チップ）からの発熱量が増え、これによる信
頼性低下が問題となっている。By the way, with the increasing integration of semiconductor devices, semiconductor elements (
The amount of heat generated from semiconductor chips (hereinafter referred to as semiconductor chips) has increased, and this has led to a reduction in reliability, which has become a problem.
このような半導体装置の放熱対策として、第６図に示す
ごとく、半導体素子搭載部（以下パッドと指称す）の裏
面に複数の凹部０を設け、表面積を増大せしめて放熱効
果を高めるようにしたもの、あるいは第７図に示すよう
に、パッド部分をリードフレーム本体と異なる敢然性の
良好な材質で構成し、嵌合部ｋを設けて両者を一体化す
るようにしたものなど種々の提案がなされている。As a heat dissipation measure for such semiconductor devices, as shown in Figure 6, a plurality of recesses are provided on the back surface of the semiconductor element mounting area (hereinafter referred to as pads) to increase the surface area and enhance the heat dissipation effect. Various proposals have been made, such as one in which the pad part is made of a material with good durability different from that of the lead frame main body, and a fitting part k is provided to integrate the two, as shown in Figure 7. being done.
しかしながら、前者の構造では凹部０の形成により、パ
ッドが変形し易くなり、歩留まり低下の原因となってい
た。However, in the former structure, the pad is easily deformed due to the formation of the recess 0, causing a decrease in yield.
また、後者の構造では、パッド部分とリードフレーム本
体との嵌合不良により、ワイヤボンディング後、パッド
部分とリードフレーム本体とが分裂し、ワイヤの切断や
チップの破損というような不具合が発生することがたび
たびであった。In addition, in the latter structure, due to poor fitting between the pad part and the lead frame body, the pad part and the lead frame body may separate after wire bonding, resulting in problems such as wire breakage and chip damage. was frequent.
（発明が解決しようとする課題）
このように、従来の樹脂封止型半導体装置においては、
放熱性の改善のための構造が提案されてはいるが、かえ
ってこの構造が歩留まり低下の原因となり、信頼性の高
いものを得ることができないという問題があった。(Problem to be solved by the invention) As described above, in the conventional resin-sealed semiconductor device,
Although a structure for improving heat dissipation has been proposed, there is a problem in that this structure actually causes a decrease in yield, making it impossible to obtain a highly reliable product.
本発明は、前記実情に鑑みてなされたもので、敢然性が
良好で信頼性の高い半導体装置を提供することを目的と
する。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device with good robustness and high reliability.
〔発明の構成］
（課題を解決するための手段）
そこで本発明の半導体装置では、樹脂パッケージ内に、
半導体素子固着工程よりも面積が大きくなるように形成
された半導体素子搭載部と、該半導体素子搭載部に搭載
された半導体素子と、該半導体素子搭載部の周縁部上に
インナーリード先端が絶縁物質を介して貼着固定される
と共に、ワイヤを介して半導体素子と電気的接続がなさ
れるように構成され、さらにこのインナーリードに連設
されるアウターリードの先端を樹脂パッケージ外に導出
せしめてなるリードフレーム本体とを、具備するよ・う
にしている。[Structure of the Invention] (Means for Solving the Problems) Therefore, in the semiconductor device of the present invention, in the resin package,
A semiconductor element mounting part formed to have a larger area than in the semiconductor element fixing process, a semiconductor element mounted on the semiconductor element mounting part, and an inner lead tip formed with an insulating material on the peripheral edge of the semiconductor element mounting part. The resin package is configured such that it is adhered and fixed through the resin package, and is electrically connected to the semiconductor element through wires, and furthermore, the tips of the outer leads connected to the inner leads are led out of the resin package. A lead frame body is provided.
すなわち、本発明では、半導体素子搭載部の面積が半導
体素子載置領域よりも大きくなるように形成され、該半
導体素子搭載部の周縁部上に半導体素子を囲むようにイ
ンナーリード先端を絶縁物質を介して貼着固定するよう
にしている。That is, in the present invention, the area of the semiconductor element mounting part is formed to be larger than the semiconductor element mounting area, and the tip of the inner lead is coated with an insulating material so as to surround the semiconductor element on the peripheral edge of the semiconductor element mounting part. It is fixed by pasting it in place.
上記構成において望ましくは、半導体素子搭載部をリー
ドフレーム本体よりも放熱性の良好な材料で構成するよ
うにする。In the above configuration, the semiconductor element mounting portion is preferably made of a material with better heat dissipation than the lead frame body.
また、本発明の半導体装置では、樹脂パッケージの表裏
両面のうち少なくとも一方に窪みを設けるようにしてい
る。Further, in the semiconductor device of the present invention, a depression is provided on at least one of the front and back surfaces of the resin package.
さらに望旗しくは、この半導体素子載置領域上に絶縁材
料を介して半導体素子を固着すると共に、裏面側の窪み
を深くし半導体素子搭載部が露呈するように構成してい
る。More preferably, the semiconductor element is fixed onto the semiconductor element mounting area via an insulating material, and the recess on the back side is made deep so that the semiconductor element mounting portion is exposed.
また、本発明の方法では、複数のインナ１−リードおよ
びアウターリードを有する単位リードフレームパターン
が複数連設された第１のリードフレームと、該第１のリ
ードフレームのインナーリード先端に囲まれた領域より
も外縁が外側にくるように形成された半導体素子搭載部
を有する単位リードフレームパターンが複数連設された
第２のリードフレームとを用意し、該半導体素子搭載部
の周縁部上にインナーリード先端がくるようにこれらを
位置決めし、絶縁物質を介して第１および第２のリード
フレームを貼着固定したのち、半導体素子を該半導体素
子搭載部に固着すると共に、ワイヤポンディングを行い
樹脂封止を行うようにしている。Further, in the method of the present invention, a first lead frame in which a plurality of unit lead frame patterns each having a plurality of inner 1-leads and an outer lead are arranged in series; A second lead frame is prepared in which a plurality of unit lead frame patterns each having a semiconductor element mounting part formed in such a way that the outer edge is located outside the area is prepared, and an inner lead frame pattern is provided on the peripheral edge of the semiconductor element mounting part. After positioning these so that the lead tips are aligned and pasting and fixing the first and second lead frames via an insulating material, the semiconductor element is fixed to the semiconductor element mounting part, and wire bonding is performed to bond the resin. I am trying to seal it.
（作用）
本発明によれば、インナーリードの先端が半導体素子搭
載部の周縁部上に貼着固定されているため、高集積化に
際してリード幅の微細化が進んだ場合にも、インナーリ
ードの先端は位置ずれもなく良好に維持される。(Function) According to the present invention, since the tips of the inner leads are adhered and fixed on the periphery of the semiconductor element mounting area, even when the lead width becomes finer due to higher integration, the inner leads can be fixed. The tip is well maintained without misalignment.
また、半導体素子搭載部をリードフレーム本体よりも放
熱性の良好な材料で構成するようにすれば、高集積化に
際して発熱部が増大しても、放熱面積が＾いため、熱に
よる素子の劣化を防止することが可能となる。In addition, if the semiconductor element mounting part is made of a material with better heat dissipation than the lead frame body, even if the number of heat generating parts increases due to high integration, the heat dissipation area will be small, which will prevent deterioration of the elements due to heat. It becomes possible to prevent this.
さらに、樹脂パッケージの表裏両面のうち少なくとも一
方に窪みを設けるようにしているため、発熱部ができる
だけ、外雰囲気に近い位置にあり、またパッケージの表
面積が大きくなり、熱の放散性が良好となる６
さらにまた、裏面側の窪みを深くし半導体素子搭載部が
露呈するようにすれば、ざらに熱放散性が向上する。Furthermore, since the resin package has a recess on at least one of the front and back surfaces, the heat generating part is located as close to the outside atmosphere as possible, and the surface area of the package is increased, which improves heat dissipation. 6. Furthermore, if the recess on the back surface side is deepened so that the semiconductor element mounting portion is exposed, the heat dissipation property can be roughly improved.
また、本発明の方法では、第１のリードフレームのイン
ナーリード先端５ｆｆｉ２のリードフレーム上に固定さ
れた状態で、ワイヤボンディングがなされるようになっ
ているため、位置ずれのない良好なボンディングが可能
となり、また実装後においても変形の虞もなく信頼性の
高い半導体装置を提供することができる。Further, in the method of the present invention, wire bonding is performed with the inner lead tip 5ffi2 of the first lead frame fixed on the lead frame, so good bonding without positional deviation is possible. Therefore, it is possible to provide a highly reliable semiconductor device with no risk of deformation even after mounting.
（実施例）
以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。(Example) Hereinafter, examples of the present invention will be described in detail with reference to the drawings.
この半導体装置は、第１図に示すように、樹脂パッケー
ジ内６内に、半導体素子Ｕ置領域よりも面積が大きくな
るように形成された半導体素子搭載部すなわちダイパッ
ド２２と、該ダイパッド２２に搭載された半導体チップ
３と、該半導体チップ搭載領域の周縁部上にインナーリ
ード４先端が絶縁性物質であるエポキシ樹脂を介して貼
着固定されると共に、ワイヤ５を介して半導体チップ３
と電気的接続がなされるように構成され、さらにこのイ
ンナーリード４に連設されるアウターリード８の先端を
樹脂パッケージ６外に導出せしめてなることを特徴とす
るものである。As shown in FIG. 1, this semiconductor device includes a semiconductor element mounting portion, that is, a die pad 22, formed in a resin package 6 so as to have a larger area than a semiconductor element U placement area, and a die pad 22 mounted on the die pad 22. The tip of the inner lead 4 is adhered and fixed onto the peripheral edge of the semiconductor chip mounting area through the epoxy resin, which is an insulating material, and the semiconductor chip 3 is attached to the semiconductor chip 3 through the wire 5.
The resin package 6 is configured such that an electrical connection is made with the resin package 6, and the tip of an outer lead 8 connected to the inner lead 4 is led out of the resin package 6.
次に、この半導体装置の製造方法について説明する。Next, a method for manufacturing this semiconductor device will be explained.
第２図（ａ）乃至第２図（ｆ）は、本発明実施例の半導
体装置の製造工程を示す図である。FIGS. 2(a) to 2(f) are diagrams showing the manufacturing process of a semiconductor device according to an embodiment of the present invention.
まず、第２図（ａ＞に示すように、スタンピング法によ
り、ニッケルからなる帯状材料を加工し、インナ−リー
ド４先端部の平坦幅を確保するためのコイニング処理、
インナーリード先端部にめっきを行うめっき工程など通
常の処理工程を経てダイパッドのない第１のリードフレ
ーム１１を形成する。First, as shown in FIG. 2 (a), a strip material made of nickel is processed by a stamping method, and a coining process is performed to ensure a flat width at the tip of the inner lead 4.
A first lead frame 11 without a die pad is formed through normal processing steps such as a plating step in which the tips of the inner leads are plated.
一方、第２図（ｂ）に示すように、放熱性の良好な銅を
主成分とする合金からなる帯状材料を同様に、スタンピ
ング法により加工し、サイドバーにサポートパー９を介
して一体的に接続されるダイパッド２２を有する第２の
リードフレーム２１を形成する。なお、このダイパッド
は、半導体チップ搭載部の面積が半導体チップ載置領域
よりも大きくなるように形成されている。なおこれら第
１及び第２のリードフレームには互いに対応する位置に
位置決め用のパイロットホールＨが形成されている。On the other hand, as shown in Fig. 2(b), a strip-shaped material made of an alloy whose main component is copper, which has good heat dissipation properties, is similarly processed by the stamping method, and is integrally attached to the side bar via a support par 9. A second lead frame 21 having a die pad 22 connected to the second lead frame 21 is formed. Note that this die pad is formed such that the area of the semiconductor chip mounting portion is larger than the semiconductor chip mounting region. Note that pilot holes H for positioning are formed in the first and second lead frames at positions corresponding to each other.
この後、第２図（Ｃ）に示すように、該パイロットホー
ルＨＳｆｆｉなるように第２のリードフレーム２１上に
第１のリードフレーム１１を出ね、第２図（ｄ）に示す
ように、エポキシ樹脂１２を介してこれらを互いに固着
する。これにより第１のリードフレームのインナーリー
ド４の先端はダイパッド２３上に固着される。After that, as shown in FIG. 2(C), the first lead frame 11 is placed on the second lead frame 21 so that the pilot hole HSffi is formed, and as shown in FIG. 2(d), These are fixed to each other via epoxy resin 12. As a result, the tips of the inner leads 4 of the first lead frame are fixed onto the die pad 23.
さらにこの後、第２図（ｅ）に示すように、ダイパッド
２２上に半導体チップ３をエポキシ樹脂１２によって固
着し、ワイヤボンディング法により、各インナ−リード
４先端部のボンディングエリアと半導体チップ３のポン
ディングパッドとをワイヤボンディング法によりワイヤ
５を介して結線する。Further, as shown in FIG. 2(e), the semiconductor chip 3 is fixed onto the die pad 22 using the epoxy resin 12, and the bonding area at the tip of each inner lead 4 is bonded to the semiconductor chip 3 using the wire bonding method. The bonding pads are connected via wires 5 by wire bonding.
そして、第２図（ｆ）に示すように、エポキシ樹脂を用
いて樹脂封止を行い、アウターリード先端部を残して該
リードフレーム構体を封止する。Then, as shown in FIG. 2(f), resin sealing is performed using epoxy resin to seal the lead frame structure, leaving the outer lead tips intact.
最後に、タイバー７を切除し、アウターリード８の先端
を分離すると共に、所望の方向に折り曲げ成型し、第１
図に示した半導体装置が完成する。Finally, the tie bar 7 is cut out, the tip of the outer lead 8 is separated, and the tip is bent in a desired direction to form the first
The semiconductor device shown in the figure is completed.
このようにして形成された半導体装置では、ダイパッド
２２が放熱性の良好な材料で形成されると共に大きく形
成されているため、高集積化に際して発熱量が増大して
も、放熱面積が高いため、熱による素子の劣化を防止す
ることが可能となる。In the semiconductor device formed in this manner, the die pad 22 is made of a material with good heat dissipation properties and is large, so even if the amount of heat generated increases due to high integration, the heat dissipation area is large. It becomes possible to prevent deterioration of the element due to heat.
また、インナーリードの先端が半導体素子搭載部の周縁
部上に貼着固定されているため、インナーリードの先端
は位置ずれもなく良好に維持さ机る。Furthermore, since the tips of the inner leads are adhered and fixed onto the peripheral edge of the semiconductor element mounting portion, the tips of the inner leads can be maintained well without any displacement.
また、本発明実施例の半導体装置の製造方法では、第１
のリードフレーム１１のインナーリード先端が第２のリ
ードフレーム２１上に固定された状態で、ワイヤボンデ
ィングがなされるようになっているため、位置ずれのな
い良好なボンディングが可能となり、また実装後におい
ても変形の虞もなく信頼性の高い半導体装置を提供する
ことができる。Further, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the first
Since wire bonding is performed with the inner lead tips of the lead frame 11 fixed on the second lead frame 21, good bonding without positional deviation is possible, and also after mounting. Accordingly, it is possible to provide a highly reliable semiconductor device without any risk of deformation.
なお、前記実施例では、第１及び第２のリードフレーム
を固着するのにエポキシ樹脂を用いるようにしたが、ポ
リイミド樹脂など絶縁性の樹脂であればよく、また、ポ
リイミドフィルムなど絶縁性のフィルム状体を所望の形
状に切断しておきこれを第１及び第２のリードフレーム
の間に挾んで加熱し固着するようにしても良い。In the above embodiment, epoxy resin was used to fix the first and second lead frames, but any insulating resin such as polyimide resin may be used, and insulating film such as polyimide film may also be used. Alternatively, the shaped body may be cut into a desired shape and then sandwiched between the first and second lead frames and fixed by heating.
また、第２のリードフレームの形状加工後、実装に先立
ち、ダイパッドの表面を電気的絶縁性が良好で、熱伝導
性の良好な７＃膜で被覆しておくようにしてもよい。Further, after processing the shape of the second lead frame and prior to mounting, the surface of the die pad may be covered with a 7# film having good electrical insulation and good thermal conductivity.
さらに、本発明の変形例として、第３図に示すように樹
脂パッケージ６の表面および裏面に凹部を形成し、半導
体チップができるだけ、外界囲気に近い位置にくるよう
に形成しても良い。ここでは、裏面はダイパッド２２が
露呈するように深い凹部を形成したが、必ずしも露呈せ
しめる必要はない。Furthermore, as a modification of the present invention, as shown in FIG. 3, recesses may be formed on the front and back surfaces of the resin package 6 so that the semiconductor chip is located as close to the external environment as possible. Here, a deep recess is formed on the back surface so that the die pad 22 is exposed, but it is not necessarily necessary to expose it.
上記構成により、さらに熱放散性が向上し、信頼性の高
い半導体装置を得ることが可能となる。The above configuration further improves heat dissipation and makes it possible to obtain a highly reliable semiconductor device.
加えて、放熱性をあまり考慮しないならば、第２のリー
ドフレームを剛性を有する絶縁性部材で構成し、インナ
ーリード先端を支持するようにしてもよい。In addition, if heat dissipation is not much of a consideration, the second lead frame may be made of a rigid insulating member to support the tips of the inner leads.
以上説明してきたように、本発明によれば、インナーリ
ードの先端が半導体素子搭載部の周縁部上に貼着固定さ
れているため、高集積化に際してリード幅の微細化が進
んだ場合にも、放熱性が良好で信頼性の高い半導体装置
を得ることが可能となる。As explained above, according to the present invention, since the tips of the inner leads are fixedly adhered to the peripheral edge of the semiconductor element mounting area, even when the lead width becomes finer due to higher integration, , it becomes possible to obtain a semiconductor device with good heat dissipation and high reliability.
さらに、樹脂パッケージの表裏両面のうち少なくとも一
方に窪みを設けるようにしているため、熱の放散性が良
好となり、信頼性の向上を計ることが可能となる。Furthermore, since the resin package is provided with a recess on at least one of the front and back surfaces, heat dissipation is improved and reliability can be improved.
また、本発明の方法では、第１のリードフレームのイン
ナーリード先端が第２のリードフレーム上に固定された
状態で、ワイヤポンディングがなされるようになってい
るため、位置ずれのない良好なボンディングが可能とな
り、また実装後においても変形の虞もなく信頼性の高い
半導体装置を提供することが可能となる。In addition, in the method of the present invention, wire bonding is performed with the inner lead tips of the first lead frame fixed on the second lead frame, so that good wire bonding is performed without misalignment. Bonding becomes possible, and a highly reliable semiconductor device can be provided without the risk of deformation even after mounting.
第１図は本発明実施例の半導体装置を示す図、第２図（
ａ）乃至第２図（ｆ）は本発明実施例の半導体装置の製
造工程を示す図、第３図は本発明実施例の半導体装置の
変形例を示す図、第４図は従来例の半導体装置を示す図
、第５図乃至第７図は従来例のリードフレームを示す図
である。
１・・・リードフレーム、２・・・ダイパッド、３・・
・半導体素子、４・・・インナーリード、５・・・ボン
ディングワイヤ、６・・・樹脂、７・・・タイバー、８
・・・アウターリード、９・・・サポートパー １１・
・・第１のリードフレーム、２１・・・第２のリードフ
レーム、２２・・・ダイパッド、１２・・・エポキシ樹
脂。
第２図（ｂ）
第２図（ａ）
第２図（ｃ）
ｚ２
第２図
（ｄ）
第２図（ｆ）
第
図
第５図FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention, and FIG.
Figures a) to 2(f) are diagrams showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, Figure 3 is a diagram showing a modification of the semiconductor device according to an embodiment of the present invention, and Figure 4 is a diagram showing a conventional semiconductor device. Figures 5 to 7 showing the apparatus are diagrams showing conventional lead frames. 1...Lead frame, 2...Die pad, 3...
- Semiconductor element, 4... Inner lead, 5... Bonding wire, 6... Resin, 7... Tie bar, 8
...Outer lead, 9...Support par 11.
... first lead frame, 21 ... second lead frame, 22 ... die pad, 12 ... epoxy resin. Figure 2 (b) Figure 2 (a) Figure 2 (c) z2 Figure 2 (d) Figure 2 (f) Figure 5
Claims (5)
ワイヤを介して半導体素子と電気的接続がなされるよう
に構成され、さらにこのインナーリードに連設されるア
ウターリードの先端を樹脂パッケージ外に導出せしめて
なるリードフレーム本体とを具備したことを特徴とする
半導体装置。(1) In a resin-sealed semiconductor device, a semiconductor element mounting part formed in a resin package so as to have a larger area than a semiconductor element mounting area, and a semiconductor element mounted in the semiconductor element mounting part. , the tips of the inner leads are adhered and fixed onto the peripheral edge of the semiconductor element mounting portion via an insulating material, and
The lead frame body is configured to be electrically connected to a semiconductor element via a wire, and further includes a lead frame body in which the tips of outer leads connected to the inner leads are led out of the resin package. semiconductor device.
１のリードフレームよりも放熱性の 良好な材料で構成され半導体素子搭載部を有する第２の
リードフレームとから構成されていることを特徴とする
請求項（１）記載の半導体装置。(2) The lead frame body includes a first lead frame having an inner lead and an outer lead connected thereto, and a semiconductor element mounting portion made of a material with better heat dissipation than the first lead frame. 2. The semiconductor device according to claim 1, further comprising a second lead frame having a second lead frame.
置。(3) The semiconductor device according to claim 2, wherein the resin package has a depression on at least one of the front and back surfaces.
る程度に深く形成されており、 前記半導体素子は、 前記半導体素子載置部の半導体素子載置領 域上に絶縁材料を介して固着せしめられていることを特
徴とする請求項（３）記載の半導体装置。(4) The recess is formed deep enough to expose the semiconductor element mounting portion on the back side, and the semiconductor element is fixed onto the semiconductor element mounting area of the semiconductor element mounting portion via an insulating material. 4. The semiconductor device according to claim 3, wherein the semiconductor device is
する単位リードフレームパターンが複数連設された第１
のリードフレームを形成する第１のリードフレーム形成
工程と、 該第１のリードフレームのインナーリード 先端に囲まれた領域よりも外縁が外側にくるように形成
された半導体素子搭載部を有する単位リードフレームパ
ターンが複数連設された第２のリードフレームを形成す
る第２のリードフレーム形成工程と、 該半導体素子搭載部の周縁部上にインナー リード先端がくるように第１及び第２のリードフレーム
を位置決めし、第１および第２のリードフレームを貼着
固定するリードフレーム組み立て工程と、 半導体素子を該半導体素子搭載部に固着す る半導体素子固着工程と、 ワイヤボンディングを行うワイヤボンディ ング工程と、 樹脂封止工程とを具備したことを特徴とす る半導体装置の製造方法。(5) A first unit lead frame pattern in which a plurality of unit lead frame patterns each having a plurality of inner leads and outer leads are arranged in series.
a first lead frame forming step for forming a lead frame; and a unit lead having a semiconductor element mounting portion formed such that an outer edge thereof is located outside a region surrounded by an inner lead tip of the first lead frame. a second lead frame forming step of forming a second lead frame in which a plurality of frame patterns are arranged in series, and forming the first and second lead frames so that the tips of the inner leads are placed on the peripheral edge of the semiconductor element mounting part. a lead frame assembly step in which the first and second lead frames are positioned and fixed by adhesion; a semiconductor element fixing step in which the semiconductor element is fixed to the semiconductor element mounting portion; a wire bonding step in which wire bonding is performed; 1. A method for manufacturing a semiconductor device, comprising a sealing step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32854888A JPH02174152A (en) | 1988-12-26 | 1988-12-26 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32854888A JPH02174152A (en) | 1988-12-26 | 1988-12-26 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02174152A true JPH02174152A (en) | 1990-07-05 |
Family
ID=18211511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32854888A Pending JPH02174152A (en) | 1988-12-26 | 1988-12-26 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02174152A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4922787A (en) * | 1972-05-12 | 1974-02-28 | ||
| JPS59207646A (en) * | 1983-05-11 | 1984-11-24 | Toshiba Corp | Semiconductor device and lead frame |
-
1988
- 1988-12-26 JP JP32854888A patent/JPH02174152A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4922787A (en) * | 1972-05-12 | 1974-02-28 | ||
| JPS59207646A (en) * | 1983-05-11 | 1984-11-24 | Toshiba Corp | Semiconductor device and lead frame |
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