JPH05129512A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH05129512A
JPH05129512A JP3285776A JP28577691A JPH05129512A JP H05129512 A JPH05129512 A JP H05129512A JP 3285776 A JP3285776 A JP 3285776A JP 28577691 A JP28577691 A JP 28577691A JP H05129512 A JPH05129512 A JP H05129512A
Authority
JP
Japan
Prior art keywords
lead frame
metal layer
dimples
lead
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3285776A
Other languages
Japanese (ja)
Inventor
Katsumi Okuaki
勝己 奥秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3285776A priority Critical patent/JPH05129512A/en
Publication of JPH05129512A publication Critical patent/JPH05129512A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide an improved lead frame wherein it hardly absorbs humidity until the mounting operation of an SMD after the manufacture of the SMD, it is not stripped due to a shearing force generated at the bonding interface inside a package in a heating operation and, as a result, a package crack is not caused. CONSTITUTION:A second metal layer 4a whose etch rate is slow as compared with that of a first metal layer 1a for a lead-frame main body is formed on a face opposite to the semiconductor chip mounting face of the lead frame; inverted-pot-shaped dimples 5a which pass the second metal layer 4a and which have been etched up to the inside of the first metal layer 1a for the lead-frame main body are provided. Since the dimples have an inverted-pot-shaped structure, a resin the inside of the dimples is bonded firmly to the lead frame. As a result, the bonding interface between the resin and the lead frame is sufficiently strong against a shearing force and the lead frame is not stripped. Consequently, it is possible to obtain an effect that the generation of a package crack is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はリードフレームに関し、
特にパッケージクラックを改善できる効果の高いリード
フレームに関する。FIELD OF THE INVENTION The present invention relates to a lead frame,
Particularly, the present invention relates to a lead frame having a high effect of improving package cracks.

【０００２】[0002]

【従来の技術】最近、電子機器の小型・高機能化にとも
ない、表面実装半導体デバイス（Ｓｕｒｆａｃｅ Ｍｏ
ｕｎｔｉｎｇ Ｄｅｖｉｃｅ 以下ＳＭＤという）は広
く普及している。2. Description of the Related Art Recently, surface mount semiconductor devices (Surface Mo
Unting Device (hereinafter referred to as SMD) is widely used.

【０００３】ＳＭＤはリフロー方式（クリームはんだを
印刷したプリント配線板上にチップを搭載後、搭載面全
体を加熱することではんだ接合する）により、効率のよ
い実装が可能になった。しかしその反面実装時にパッケ
ージ全体がはんだの融点以上に加熱されるために、パッ
ケージ内の接着剥離、パッケージクラックが発生すると
いう問題点がある。パッケージクラックは次のような過
程を経て起る。The SMD can be mounted efficiently by a reflow method (a chip is mounted on a printed wiring board on which cream solder is printed and then soldered by heating the entire mounting surface). However, on the other hand, since the entire package is heated to the melting point of the solder or higher at the time of mounting, there is a problem that peeling of the adhesive in the package and cracking of the package occur. Package cracking occurs through the following process.

【０００４】まず、雰囲気中の水分がＳＭＤ製造後から
実装前までの保管中にレジン内に拡散（吸湿）する。加
熱時には、パッケージ内の接着界面に剪断力で剥離が生
じ、その剥離部に高温下で拡散速度を速めた（拡散速度
は室温の数千倍）水分がレジン中から水蒸気として吹き
出し、次第に圧力が上昇することで剥離部が拡大し、応
力が集中した箇所が破壊するものである。First, the moisture in the atmosphere diffuses (absorbs moisture) in the resin during storage from the SMD production to the mounting. At the time of heating, peeling occurs at the adhesive interface in the package due to shearing force, and the diffusion rate is accelerated at high temperature (diffusion rate is several thousand times as high as room temperature) at the peeled portion. As it rises, the peeled portion expands and the portion where the stress is concentrated breaks.

【０００５】そこでリードフレームとレジンの接着性を
良くする目的から従来この種のリードフレームは例えば
図２に示すように半導体チップ搭載面と反対の面にディ
ンプル４ｂを設けたものが知られている。Therefore, for the purpose of improving the adhesiveness between the lead frame and the resin, a lead frame of this type is conventionally known in which dimples 4b are provided on the surface opposite to the semiconductor chip mounting surface, as shown in FIG. 2, for example. ..

【０００６】[0006]

【発明が解決しようとする課題】この従来のリードフレ
ームではレジンとリードフレームとの接着性が充分でな
いため、ＳＭＤ実装の加熱時にレジンとリードフレーム
接着界面の剪断力により剥離が生じ、パッケージクラッ
クに対して弱いという問題点があった。In this conventional lead frame, since the adhesiveness between the resin and the lead frame is not sufficient, peeling occurs due to the shearing force of the adhesive interface between the resin and the lead frame during heating of SMD mounting, which causes package cracks. There was a problem that it was weak.

【０００７】本発明の目的は、ＳＭＤ製造後から実装ま
でに吸湿することがなく、加熱時にはパッケージ内の接
着界面に生じる剪断力による剥離を生じることがなく、
その結果パッケージクラックを生ずることのない改良さ
れたリードフレームを提供することにある。The object of the present invention is to prevent moisture from being absorbed after the SMD is manufactured and before mounting, and to prevent peeling due to a shearing force generated at an adhesive interface in the package during heating.
The result is to provide an improved lead frame that is free of package cracks.

【０００８】[0008]

【課題を解決するための手段】本発明のリードフレーム
は半導体チップ搭載面と反対の面に、リードフレーム本
体の第１の金属層に比べエッチング速度が遅い第２の金
属層が設けられたリードフレームを使用することによ
り、前記第２の金属層を貫通、前記リードフレーム本体
の第１の金属層内部迄エッチングされた逆テーパーのデ
ィンプルを備えている。In the lead frame of the present invention, a lead having a second metal layer having a slower etching rate than the first metal layer of the lead frame body is provided on the surface opposite to the semiconductor chip mounting surface. By using a frame, a reverse taper dimple that penetrates through the second metal layer and is etched to the inside of the first metal layer of the lead frame body is provided.

【０００９】[0009]

【実施例】次に本発明の実施例について図面を参照して
説明する。図１は本発明の一実施例を示す断面図であ
る。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention.

【００１０】図１に於いて、リードフレームの半導体チ
ップ搭載面と反対の面に、リードフレーム本体の第１の
金属層１ａに比べエッチング速度の遅い第２の金属層４
ａが設けられ、前記第２の金属層を貫通、前記リードフ
レーム本体の第１の金属層内部迄エッチングされた逆つ
ぼ状のディンプル５ａを有している。In FIG. 1, a second metal layer 4 having a slower etching rate than the first metal layer 1a of the lead frame body is formed on the surface of the lead frame opposite to the semiconductor chip mounting surface.
a is provided, and has an inverted-vessel-shaped dimple 5a penetrating the second metal layer and etched to the inside of the first metal layer of the lead frame body.

【００１１】前記第２の金属層４ａは前記リードフレー
ム本体の第１の金属層１ａに比べ、エッチング速度が遅
いことから、ある大きさで第２の金属層を貫通し、リー
ドフレーム本体の第１の金属層内部迄エッチングすれ
ば、逆つぼ状のディンプル５ａが形成される。ディンプ
ルが逆つぼ状の構造をしていることより、ディンプル内
部のレジンはリードフレームに強固に接着されている。
その結果ＳＭＤ実装の加熱時にレジンとリードフレーム
接着界面で起こる剪断力に対して充分強く剥離は生じな
い。従ってパッケージクラック発生を改善することが可
能となる。Since the second metal layer 4a has a lower etching rate than the first metal layer 1a of the lead frame body, the second metal layer 4a penetrates the second metal layer in a certain size to form the first metal layer 1a of the lead frame body. When the inside of the first metal layer is etched, the inverted dimple 5a is formed. The resin inside the dimples is firmly bonded to the lead frame because the dimples have an inverted vase-like structure.
As a result, peeling does not occur sufficiently strong against the shearing force generated at the adhesive interface between the resin and the lead frame when the SMD mounting is heated. Therefore, it is possible to improve the occurrence of package cracks.

【００１２】[0012]

【発明の効果】以上説明したように、本発明は、半導体
チップ搭載面と反対の面に、リードフレーム本体の第１
の金属層に比べエッチング速度が遅い第２の金属層が設
けられているリードフレームに於いて、前記第２の金属
層を貫通、前記リードフレーム本体の第１の金属層内部
迄エッチングされたディンプルを具備する。As described above, according to the present invention, the first side of the lead frame body is provided on the surface opposite to the semiconductor chip mounting surface.
In a lead frame provided with a second metal layer having an etching rate slower than that of the first metal layer, the dimples penetrating the second metal layer and being etched to the inside of the first metal layer of the lead frame body. It is equipped with.

【００１３】前記第２の金属層として、前記リードフエ
ーム本体の第１の金属層に比べ、エッチング速度が遅い
ものを適用し、ある大きさで第２の金属層を貫通、リー
ドフレーム本体の第１の金属層内部迄エッチングすれ
ば、逆つぼ状のディンプルが形成される。ディンプルが
逆つぼ状の構造をしていることより、ディンプル内部の
レジンはリードフレームに強固に接着されている。その
結果ＳＭＤ実装の加熱時にレジンとリードフレーム接着
界面で起こる剪断力に対して充分強く剥離は生じない。
従ってパッケージクラック発生を改善することが可能に
なるという効果を有する。As the second metal layer, one having a slower etching rate than that of the first metal layer of the lead film body is applied, and the second metal layer penetrates the second metal layer with a certain size, and the first metal layer of the lead frame body is formed. If the inside of the metal layer is etched, an inverted-vessel-shaped dimple is formed. The resin inside the dimples is firmly bonded to the lead frame because the dimples have an inverted vase-like structure. As a result, peeling does not occur sufficiently strong against the shearing force generated at the adhesive interface between the resin and the lead frame when the SMD mounting is heated.
Therefore, there is an effect that it is possible to improve the occurrence of package cracks.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を使用して製造された樹脂封
止型半導体装置の断面図である。FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device manufactured by using an embodiment of the present invention.

【図２】ディンプルを有する従来のリードフレームを使
用して製造された樹脂封止型半導体装置の断面図であ
る。FIG. 2 is a sectional view of a resin-sealed semiconductor device manufactured using a conventional lead frame having dimples.

【符号の説明】[Explanation of symbols]

１ａ，１ｂ リードフレーム（第１の金属層） ２ａ，２ｂ 半導体チップ ３ａ，３ｂ レジン ４ａ 第２の金属層 ５ａ，５ｂ ディンプル 1a, 1b Lead frame (first metal layer) 2a, 2b Semiconductor chip 3a, 3b Resin 4a Second metal layer 5a, 5b Dimple

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップ搭載面の反対の面に、ディ
ンプルを有するリードフレームに於いて、リードフレー
ム本体の第１の金属層に比べエッチング速度が遅い第２
の金属層が設けられ、前記第２の金属層を貫通し前記リ
ードフレーム本体の第１の金属層内部迄エッチングされ
た逆テーパーのディンプルを備えることを特徴とするリ
ードフレーム。1. In a lead frame having dimples on the surface opposite to the semiconductor chip mounting surface, the second etching rate is slower than that of the first metal layer of the lead frame body.
And a reverse taper dimple that penetrates through the second metal layer and is etched to the inside of the first metal layer of the lead frame body.
JP3285776A 1991-10-31 1991-10-31 Lead frame Pending JPH05129512A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3285776A JPH05129512A (en) 1991-10-31 1991-10-31 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3285776A JPH05129512A (en) 1991-10-31 1991-10-31 Lead frame

Publications (1)

Publication Number Publication Date
JPH05129512A true JPH05129512A (en) 1993-05-25

Family

ID=17695921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3285776A Pending JPH05129512A (en) 1991-10-31 1991-10-31 Lead frame

Country Status (1)

Country Link
JP (1) JPH05129512A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5753535A (en) * 1991-09-18 1998-05-19 Fujitsu Limited Leadframe and resin-sealed semiconductor device
JP2016152384A (en) * 2015-02-19 2016-08-22 三菱マテリアル株式会社 Manufacturing method of substrate for power module and manufacturing method of power module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5753535A (en) * 1991-09-18 1998-05-19 Fujitsu Limited Leadframe and resin-sealed semiconductor device
JP2016152384A (en) * 2015-02-19 2016-08-22 三菱マテリアル株式会社 Manufacturing method of substrate for power module and manufacturing method of power module

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