JP3345759B2 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP3345759B2 JP3345759B2 JP12262993A JP12262993A JP3345759B2 JP 3345759 B2 JP3345759 B2 JP 3345759B2 JP 12262993 A JP12262993 A JP 12262993A JP 12262993 A JP12262993 A JP 12262993A JP 3345759 B2 JP3345759 B2 JP 3345759B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- back surface
- dicing
- length
- blade
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置とその製造方
法、さらに詳しくはＴＡＢを用いて半導体素子を組立し
た半導体装置とその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a semiconductor element is assembled using TAB and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】図５は従来のＴＡＢを用いた半導体装置
を示す断面図である。図に於いて半導体素子１１はバン
プ１２を介してリードフィンガー１３とＴＡＢ（テープ
オートメイテッド ボンデイング）にて接続されてい
る。リードフィンガーは可撓性絶縁性基板も含めて封止
樹脂１５で成形されており半導体素子の裏面は成形樹脂
裏面に露出している。フォーミングリード２４は樹脂封
止後ハンダメッキ処理されリード形状を成形されてい
た。バンプは最初半導体素子側に成形しておいても良
く、リードフィンガー側に成形しても良い。2. Description of the Related Art FIG. 5 is a sectional view showing a conventional semiconductor device using TAB. In the figure, a semiconductor element 11 is connected to a lead finger 13 via a bump 12 by TAB (tape automated bonding). The lead finger is molded with the sealing resin 15 including the flexible insulating substrate, and the back surface of the semiconductor element is exposed on the molding resin back surface. The forming lead 24 was solder-plated after resin sealing to form a lead shape. The bump may be formed first on the semiconductor element side, or may be formed on the lead finger side.
【０００３】[0003]
【発明が解決しようとする課題】しかし、前述の従来技
術では半導体装置をリフローハンダ付けなどの高温にさ
らしたとき、半導体素子と封止樹脂の熱膨張係数の差に
よりその間にギャップが生じた。このギャップ間に空気
中の水分が侵入してアルミ配線あるいはアルミパッドを
腐食させ信頼性が低下する原因となった。すなわち半導
体素子の材料であるシリコンの熱膨張係数は ０．００
０００２（１/゜Ｃ）に対し、封止樹脂の熱膨張係数は
０．００００２〜０．００００７（１/ ゜Ｃ）程度で
あり、約１０倍ことなっているためである。However, in the prior art described above, when the semiconductor device was exposed to a high temperature such as reflow soldering, a gap was formed between the semiconductor device and the sealing resin due to a difference in thermal expansion coefficient between the semiconductor element and the sealing resin. Moisture in the air invades between the gaps, corroding the aluminum wiring or the aluminum pad and causing a reduction in reliability. That is, the thermal expansion coefficient of silicon, which is a material of a semiconductor element, is 0.00
0002 (1 / ゜ C), the thermal expansion coefficient of the sealing resin is
This is because it is about 0.00002 to 0.00007 (1 / ° C), which is about 10 times.
【０００４】そこで本発明はこのような問題を解決する
ためのものでその目的とするところは半導体装置をリフ
ローハンダ付けの時、熱膨張差による大きなギャップを
生じさせず水分の発生を防止することにより信頼性の高
い半導体装置を提供することにある。SUMMARY OF THE INVENTION Accordingly, the present invention is to solve such a problem, and an object of the present invention is to prevent the generation of moisture without causing a large gap due to a difference in thermal expansion during reflow soldering of a semiconductor device. To provide a semiconductor device with higher reliability.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
半導体素子をＴＡＢにて、インナーリードとボンデイン
グパッドとを接続し、半導体素子の裏面が露出するよう
にして樹脂成形したパッケージの半導体素子の側面形状
に於いて、能動面側の長さが裏面側の長さよりも長い事
を特徴とする。According to the present invention, there is provided a semiconductor device comprising:
The length of the active surface side of the semiconductor element is TAB, and the length of the active surface side is the rear side. It is longer than the length.
【０００６】そのために、ダイシング工程に於いて、ダ
イシングブレードの刃先の厚さが、回転中心側より薄く
成形したダイシングブレードで、ウエハの裏面よりカッ
トする事を特徴とする。For this purpose, in the dicing process, the dicing blade is cut from the back surface of the wafer with a dicing blade formed so that the cutting edge thereof is thinner than the center of rotation.
【０００７】さらに、ダイシング工程に於いて、カット
の最初にウエハの裏面よりハーフカットを行い、次に１
回目のダイシングブレードよりも薄いブレードで完全に
カットする事を特徴とする。Further, in the dicing step, a half-cut is first made from the back surface of the wafer,
It is characterized by completely cutting with a blade thinner than the first dicing blade.
【０００８】[0008]
【実施例】図１は本発明の実施例における断面図であっ
てある。図において半導体素子１１はバンプ１２を介し
てリードフィンガー１３とＴＡＢにて接続されている。
リードフィンガーはリードフレーム１４とアウターリー
ドボンデイングしたあと封止樹脂１５で樹脂封止されて
おり半導体素子の裏面は成形樹脂裏面に露出している。
半導体素子の能動面側の長さＬ２は 裏面側の長さＬ１
よりも長く形成されている。アウターリード１６は樹脂
封止後ハンダメッキ処理されリード形状を成形されてい
た。バンプは最初半導体素子側に成形しておいても良
く、リードフィンガー側に成形しても良い。FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, a semiconductor element 11 is connected to a lead finger 13 via a bump 12 by TAB.
The lead fingers are resin-sealed with a sealing resin 15 after being bonded to the lead frame 14 and the outer lead, and the back surface of the semiconductor element is exposed on the back surface of the molding resin.
The length L2 of the active surface side of the semiconductor element is the length L1 of the back surface side.
It is formed longer. The outer leads 16 were solder-plated after resin sealing to form leads. The bump may be formed first on the semiconductor element side, or may be formed on the lead finger side.
【０００９】図２は本発明の他の実施例における断面図
である。半導体素子の裏面側に切り欠き部２５を形成す
る事のより、能動面側の長さを、裏面側の長さよりも長
く形成している。リードフィンガー１３は可撓性絶縁性
基板２１も含めて封止樹脂１５で成形されており半導体
素子の裏面は成形樹脂裏面に露出している。リードフィ
ンガーは封止樹脂１５より直接、導出されておりフオー
ミングリード２４として、ハンダメッキ後フォーミング
されている。FIG. 2 is a sectional view showing another embodiment of the present invention. By forming the notch 25 on the back surface side of the semiconductor element, the length of the active surface side is formed longer than the length of the back surface side. The lead finger 13 is molded with the sealing resin 15 including the flexible insulating substrate 21, and the back surface of the semiconductor element is exposed on the back surface of the molding resin. The lead fingers are directly led out of the sealing resin 15 and are formed as forming leads 24 after solder plating.
【００１０】以上のような構成において半導体装置をリ
フローハンダ付けなどの高温にさらしたとき、半導体素
子と封止樹脂の熱膨張係数の差によりその間にギャップ
が生じることがなくなった。従って半導体素子と封止樹
脂のギャップ間に空気中の水分が侵入してアルミ配線あ
るいはアルミパッドを腐食させ信頼性を低下させる事も
なくなった。When the semiconductor device is exposed to a high temperature such as reflow soldering in the above configuration, no gap is formed between the semiconductor device and the sealing resin due to a difference in thermal expansion coefficient between them. Therefore, the moisture in the air does not enter between the gap between the semiconductor element and the sealing resin, corroding the aluminum wiring or the aluminum pad, and reducing the reliability.
【００１１】図３、図４は半導体素子の能動面側の長さ
を、裏面側の長さよりも長く形成するためのダイシング
の方法である。FIGS. 3 and 4 show a dicing method for forming the length of the semiconductor element on the active surface side longer than the length on the rear surface side.
【００１２】図３において半導体素子１１の能動面３４
に保護部材３１を形成し、能動面を下方にしてダイシン
グテーブルに固定する。ダイシングブレードの刃先の厚
さＷ１は 回転中心側よりの厚さＷ２よりも薄く成形し
たダイシングブレード３２で、ウエハの裏面よりカット
する。こうしたダイシングの方法によりダイシング溝３
５を形成し、能動面側の長さが裏面側の長さよりも長い
半導体素子を形成する事が可能となる。ダイシングライ
ンの位置はウエハの外形からの距離により決める。In FIG. 3, the active surface 34 of the semiconductor element 11 is shown.
Then, a protective member 31 is formed, and is fixed to a dicing table with the active surface facing downward. The thickness W1 of the blade edge of the dicing blade is cut from the back surface of the wafer by a dicing blade 32 formed thinner than the thickness W2 from the rotation center side. The dicing groove 3 is formed by such a dicing method.
5, it is possible to form a semiconductor element in which the length of the active surface side is longer than the length of the back surface side. The position of the dicing line is determined by the distance from the outer shape of the wafer.
【００１３】図４においては最初にダイシングブレード
がＷ４の厚さのものでウエハ裏面側よりハーフカットし
たあと、Ｗ３の厚さのもので完全にカットする。In FIG. 4, first, a dicing blade having a thickness of W4 is half-cut from the back side of the wafer, and then a dicing blade having a thickness of W3 is completely cut.
【００１４】こうしたダイシングの方法により、能動面
側の長さが裏面側の長さよりも長い半導体素子を形成す
る事が可能となる。According to such a dicing method, it is possible to form a semiconductor element in which the length of the active surface is longer than the length of the back surface.
【００１５】[0015]
【発明の効果】以上のように本発明によれば 半導体素
子をＴＡＢにて、インナーリードとボンデイングパッド
とを接続し、半導体素子の裏面が露出するようにして樹
脂成形したパッケージの半導体素子の側面形状に於い
て、能動面側の長さが裏面側の長さよりも長く形成す
る。その製造方法として ダイシング工程に於いて、ダ
イシングブレードの刃先の厚さが 回転中心側より薄く
成形したダイシングブレードで、ウエハの裏面よりカッ
トする。As described above, according to the present invention, the semiconductor device is connected to the inner lead and the bonding pad by TAB, and the side surface of the semiconductor device of the package molded by resin so that the back surface of the semiconductor device is exposed. In the shape, the length of the active surface side is formed longer than the length of the back surface side. As a manufacturing method, in the dicing step, the dicing blade is cut from the back surface of the wafer with a dicing blade formed so that the cutting edge thereof is thinner than the rotation center side.
【００１６】さらに、カットの最初にウエハの裏面より
ハーフカットを行い、次に１回目のダイシングブレード
よりも薄いブレードで完全にカットする。Further, at the beginning of the cut, a half cut is performed from the back surface of the wafer, and then the wafer is completely cut with a blade thinner than the first dicing blade.
【００１７】以上のような構成において 半導体装置を
リフローハンダ付けの時 熱膨張差による大きなギャッ
プを生じさせず水分の発生を防止することにより信頼性
の高い半導体装置を提供する事が可能となる。In the above configuration, when a semiconductor device is subjected to reflow soldering, it is possible to provide a highly reliable semiconductor device by preventing generation of moisture without generating a large gap due to a difference in thermal expansion.
【図１】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】本発明の他の実施例を示す断面図。FIG. 2 is a sectional view showing another embodiment of the present invention.
【図３】本発明の製造方法を示す断面図。FIG. 3 is a cross-sectional view illustrating the manufacturing method of the present invention.
【図４】本発明の他の製造方法を示す断面図。FIG. 4 is a sectional view showing another manufacturing method of the present invention.
【図５】従来の半導体装置を示す断面図。FIG. 5 is a cross-sectional view illustrating a conventional semiconductor device.
１１・・・半導体素子 １２・・・バンプ １３・・・リードフィンガー １４・・・リードフレーム １５・・・封止樹脂 ２５・・・切り欠き部 ３１・・・保護部材 ３２・・・ダイシングブレード DESCRIPTION OF SYMBOLS 11 ... Semiconductor element 12 ... Bump 13 ... Lead finger 14 ... Lead frame 15 ... Sealing resin 25 ... Notch part 31 ... Protective member 32 ... Dicing blade
Claims (3)
とボンデイングパッドとを接続し、半導体素子の裏面が
露出するようにして樹脂成形したパッケージの半導体素
子の側面形状に於いて、能動面側の長さが裏面側の長さ
よりも長い事を特徴とする半導体装置。A semiconductor device is connected to an inner lead and a bonding pad by TAB, and the side surface of an active surface side of a resin-molded semiconductor device is formed by exposing the back surface of the semiconductor device. A semiconductor device characterized in that the length is longer than the length on the back side.
ードの刃先の厚さが、回転中心側より薄く成形したダイ
シングブレードで、ウエハの裏面よりカットする事を特
徴とする請求項１記載の半導体装置の製造方法。2. The semiconductor device according to claim 1, wherein, in the dicing step, the dicing blade is cut from the back surface of the wafer with a dicing blade formed so that the thickness of the blade is thinner than the rotation center side. Production method.
裏面よりハーフカットを行い、次に１回目のダイシング
ブレードよりも薄いブレードで完全にカットする事を特
徴とする請求項１記載の半導体装置の製造方法。3. The semiconductor device according to claim 1, wherein in the dicing step, a half cut is first performed from the back surface of the wafer, and then the wafer is completely cut with a blade thinner than the first dicing blade. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12262993A JP3345759B2 (en) | 1993-05-25 | 1993-05-25 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12262993A JP3345759B2 (en) | 1993-05-25 | 1993-05-25 | Semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06334036A JPH06334036A (en) | 1994-12-02 |
| JP3345759B2 true JP3345759B2 (en) | 2002-11-18 |
Family
ID=14840705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12262993A Expired - Fee Related JP3345759B2 (en) | 1993-05-25 | 1993-05-25 | Semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3345759B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003003445A1 (en) * | 2001-06-29 | 2003-01-09 | Fujitsu Limited | Sheet for underfill, method for underfilling semiconductor chip, and method for mounting semiconductor chip |
| US20070111399A1 (en) * | 2005-11-14 | 2007-05-17 | Goida Thomas M | Method of fabricating an exposed die package |
-
1993
- 1993-05-25 JP JP12262993A patent/JP3345759B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06334036A (en) | 1994-12-02 |
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