JPH06103688B2 - 基板の薄化エッチングのための方法 - Google Patents

基板の薄化エッチングのための方法

Info

Publication number
JPH06103688B2
JPH06103688B2 JP3510706A JP51070691A JPH06103688B2 JP H06103688 B2 JPH06103688 B2 JP H06103688B2 JP 3510706 A JP3510706 A JP 3510706A JP 51070691 A JP51070691 A JP 51070691A JP H06103688 B2 JPH06103688 B2 JP H06103688B2
Authority
JP
Japan
Prior art keywords
substrate
etching
light
layer
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3510706A
Other languages
English (en)
Japanese (ja)
Other versions
JPH05507390A (ja
Inventor
ハーベルガー、カール
ブーヘナー、ラインホルト
ボルマン、ディータ
Original Assignee
フラウンホーファー―ゲゼルシャフト・ツア・フォルデルング・デア・アンゲヴァンテン・フォルシュング・エー・ファウ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by フラウンホーファー―ゲゼルシャフト・ツア・フォルデルング・デア・アンゲヴァンテン・フォルシュング・エー・ファウ filed Critical フラウンホーファー―ゲゼルシャフト・ツア・フォルデルング・デア・アンゲヴァンテン・フォルシュング・エー・ファウ
Publication of JPH05507390A publication Critical patent/JPH05507390A/ja
Publication of JPH06103688B2 publication Critical patent/JPH06103688B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/126—Preparing bulk and homogeneous wafers by chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H10P50/644—Anisotropic liquid etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Weting (AREA)
  • Stereophonic Arrangements (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP3510706A 1990-07-06 1991-06-27 基板の薄化エッチングのための方法 Expired - Lifetime JPH06103688B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4021541.5 1990-07-06
DE4021541A DE4021541C1 (https=) 1990-07-06 1990-07-06
PCT/DE1991/000535 WO1992001309A1 (de) 1990-07-06 1991-06-27 Verfahren zum dünnätzen von substraten

Publications (2)

Publication Number Publication Date
JPH05507390A JPH05507390A (ja) 1993-10-21
JPH06103688B2 true JPH06103688B2 (ja) 1994-12-14

Family

ID=6409776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3510706A Expired - Lifetime JPH06103688B2 (ja) 1990-07-06 1991-06-27 基板の薄化エッチングのための方法

Country Status (5)

Country Link
US (1) US5279703A (https=)
EP (1) EP0538279B1 (https=)
JP (1) JPH06103688B2 (https=)
DE (2) DE4021541C1 (https=)
WO (1) WO1992001309A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8870548B2 (en) 2005-12-02 2014-10-28 Entegris, Inc. System and method for pressure compensation in a pump
US9309872B2 (en) 2005-12-02 2016-04-12 Entegris, Inc. System and method for position control of a mechanical piston in a pump
US9399989B2 (en) 2005-11-21 2016-07-26 Entegris, Inc. System and method for a pump with onboard electronics

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4317721C1 (de) * 1993-05-27 1994-07-21 Siemens Ag Verfahren zur Vereinzelung von Chips aus einem Wafer
DE4332057A1 (de) * 1993-09-21 1995-03-30 Siemens Ag Integrierte mikromechanische Sensorvorrichtung und Verfahren zu deren Herstellung
US5674758A (en) * 1995-06-06 1997-10-07 Regents Of The University Of California Silicon on insulator achieved using electrochemical etching
US5919607A (en) * 1995-10-26 1999-07-06 Brown University Research Foundation Photo-encoded selective etching for glass based microtechnology applications
US6391744B1 (en) * 1997-03-19 2002-05-21 The United States Of America As Represented By The National Security Agency Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same
US7122126B1 (en) * 2000-09-28 2006-10-17 Materials And Technologies Corporation Wet processing using a fluid meniscus, apparatus and method
AUPR174800A0 (en) * 2000-11-29 2000-12-21 Australian National University, The Semiconductor processing
CA2381028A1 (en) * 2001-04-09 2002-10-09 Marc Nantel Photo processing of materials
MY144264A (en) * 2001-11-29 2011-08-29 Transform Solar Pty Ltd Semiconductur texturing process
US20060046499A1 (en) * 2004-08-20 2006-03-02 Dolechek Kert L Apparatus for use in thinning a semiconductor workpiece
US7354649B2 (en) 2004-08-20 2008-04-08 Semitool, Inc. Semiconductor workpiece
US7193295B2 (en) * 2004-08-20 2007-03-20 Semitool, Inc. Process and apparatus for thinning a semiconductor workpiece
US7288489B2 (en) * 2004-08-20 2007-10-30 Semitool, Inc. Process for thinning a semiconductor workpiece
US20060040111A1 (en) * 2004-08-20 2006-02-23 Dolechek Kert L Process chamber and system for thinning a semiconductor workpiece
JP4876019B2 (ja) * 2007-04-25 2012-02-15 株式会社日立ハイテクノロジーズ 欠陥検査装置およびその方法
CN104759753B (zh) * 2015-03-30 2016-08-31 江苏大学 多系统自动化协调工作提高激光诱导空化强化的方法
CN117373915B (zh) * 2023-12-08 2024-04-05 合肥晶合集成电路股份有限公司 半导体结构减薄方法及结构

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2841477A (en) * 1957-03-04 1958-07-01 Pacific Semiconductors Inc Photochemically activated gaseous etching method
US3830665A (en) * 1972-12-07 1974-08-20 Motorola Inc Method for delineating semiconductor junctions
DE2951938A1 (de) * 1979-12-22 1981-07-02 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zum elektrochemischen aetzen von n- und p-dotiertem silicium
US4518456A (en) * 1983-03-11 1985-05-21 At&T Bell Laboratories Light induced etching of InP by aqueous solutions of H3 PO4
JPH0642456B2 (ja) * 1984-11-21 1994-06-01 株式会社日立製作所 表面光処理方法
US4838989A (en) * 1987-08-25 1989-06-13 The United States Of America As Represented By The United States Department Of Energy Laser-driven fusion etching process
US4861421A (en) * 1988-06-01 1989-08-29 Texas Instruments Incorporated Photochemical semiconductor etching
JP2716152B2 (ja) * 1988-08-04 1998-02-18 日本電気アイシーマイコンシステム株式会社 ラテラルトランジスタ
JPH0244728A (ja) * 1988-08-05 1990-02-14 Matsushita Electric Ind Co Ltd 半導体製造装置および半導体装置の製造方法
JPH0244729A (ja) * 1988-08-05 1990-02-14 Fuji Electric Co Ltd 半導体素子の製造方法
US5057184A (en) * 1990-04-06 1991-10-15 International Business Machines Corporation Laser etching of materials in liquids

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9399989B2 (en) 2005-11-21 2016-07-26 Entegris, Inc. System and method for a pump with onboard electronics
US8870548B2 (en) 2005-12-02 2014-10-28 Entegris, Inc. System and method for pressure compensation in a pump
US9309872B2 (en) 2005-12-02 2016-04-12 Entegris, Inc. System and method for position control of a mechanical piston in a pump

Also Published As

Publication number Publication date
JPH05507390A (ja) 1993-10-21
EP0538279B1 (de) 1994-07-20
EP0538279A1 (de) 1993-04-28
DE59102282D1 (de) 1994-08-25
DE4021541C1 (https=) 1991-12-19
WO1992001309A1 (de) 1992-01-23
US5279703A (en) 1994-01-18

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