JPH0581188A - Three state buffer circuit - Google Patents

Abstract

PURPOSE:To reduce a layout area, to improve integration degree and to speed up in operation mode by constituting circuits with less transistors related to three state buffer circuits of semiconductor integrated circuits. CONSTITUTION:This system is provided with P type MOS transistors TP1, TP2, TP3, TP4 and TP5 and N type MOSS transistors TN1, TN2, TH3, TH4, and TN5. These transistors are connected with nodes 1, 2, 3, and 4, a power source and a GND in series/parallel. An input signal D, a control signal CNTRL and some nodes act as gate inputs. By using this as a bus driver when an external buffer and bus lines such as a data bus, etc., are shared, a layout area is reduced, integration degree is improved and speed-up is realized in operation mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-state buffer circuit, and more particularly to an output three-state buffer circuit used as a bus driver when sharing a bus line such as a data bus or used as a signal output portion of an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as this type of three-state buffer circuit, a circuit as shown in FIG. 2 has been used. In FIG. 2, the input signal D passes through the inverter 11 and is 2NA.
Input to the ND gate 13 and the 2NOR gate 12, and 2
The other input of the NAND gate 13 and the 2NOR gate 12 receives the control signal CNTRL from the 2NAND gate 1
3. The inverted CNTRL of the control signal (through the inverter 16) is input to the 2NOR gate 12 respectively. The outputs of the 2NAND gate 13 and the 2NOR gate 12 are input to the inverters 15 and 14, respectively, and the outputs thereof are input to the P-type MOS transistor TP of the source power supply voltage VDD and the N-type MOS transistor TN of the source GND, and the MOS transistor TP. The drain of -TN serves as the output Out terminal of the output buffer.

Next, the operation will be described. Control signal CN
When TRL is at high level (hereinafter referred to as “H”), 2
“H” is input to the input of the NAND gate 13 and 2NO
Since the low level (hereinafter referred to as "L") which is the inversion of the control signal is input to the input of the R gate 12, the inversion of the input signal is output to the gate inputs A and B of FIG.

When the input signal D is "L", the input of the 2NAND gate 13 is "H" of the control signal CNTRL and the inverted level "H" of the input signal D, so that the level of the input B is "L". H ". 2 NOR gate 1
2 inputs the level "L" of the control signal and the input signal D
Since the inversion level "H" is input, the level at the point A becomes "H".

Therefore, the "H" level at the point B is N type M
The OS transistor TN is turned on and "L" is transmitted to the output. Next, when the input signal D is “H”, “L” is input to the inputs of the 2NOR gate 12 and the 2NAND gate 13. The level of the gate input A is 2 NOR gate 12
Input is the inversion level “L” of the input signal D and the control signal CN.
Since the inverted level "L" of TRL is input, it becomes "L".

The inverted level "L" of the input signal D and the level "H" of the control signal CNTRL are input to the inputs of the 2NAND gate 12, and the level of the gate input B is "L".
Becomes Therefore, the MOS transistor TP whose gate signal is the “L” level of the gate input A is turned on, and the “H” level is transmitted to the output.

When the control signal CNTRL is "L", 2N
Input to AND gate 13 is "L" and 2 NOR gate 1
Since the inverted level "H" of the control signal is input to the input of the transistor 2, the gate input A becomes "H", the gate input B becomes "L", and the transistor T is a gate input.
Both P and TN are turned off, and the output becomes high impedance.

When the input signal D is "L", the inverted level "H" of the input signal D and the level "L" of the control signal CNTRL are input to the inputs of the 2NAND gate 13.
The gate input B becomes "L".

The inverted level "H" of the input signal D and the inverted level "H" of the control signal are input to the inputs of the 2NOR gate 12. Since the gate input A becomes "H", the transistors TP and
TN is turned off and the output terminal becomes high impedance.

When the input signal D is "H", the inversion level "L" of the input signal D and the level "L" of the control signal CNTRL are input to the inputs of the 2NAND gate 13, so that the level of the gate input B is It becomes "L".

Further, since the inversion level "L" of the input signal D and the inversion level "H" of the control signal CNTRL are input to the input of the 2NOR gate 12, the level of the gate input A becomes "H", and the gate Both the transistors TP and TN whose inputs A and B are gate inputs are turned off, and the output becomes high impedance.

[0012]

In the conventional three-state buffer circuit described above, the inverter 11 for producing the inverted signal of the input signal D, the 2NAND gate 13 and the 2NOR gate 12, and the outputs of the respective inverters 11 and 2 are provided to accelerate the switching. Inverters 4, 5 and the last two P's,
It is composed of a total of 18 MOS transistors called N-type MOS transistors TP and TN.

In recent years, there has been a remarkable trend toward higher integration in semiconductor integrated circuits, and there is a demand for a high-speed mode in terms of operating speed as well, which is an obstacle to circuits requiring a large number of elements.

An object of the present invention is to provide a three-state buffer circuit which solves the above-mentioned drawbacks and does not require a large number of elements.

[0015]

A three-state buffer circuit according to the present invention has a first transistor connected to a first power supply and a first node serving as an output, the first node and the first node. A second transistor connected to the second power supply,
Third and fourth transistors connected in parallel to the first power supply and the second node, and fifth and sixth transistors connected in parallel to the second power supply and the third node When,
Seventh and eighth transistors connected in parallel to the second node and the third node, a ninth transistor connected to the second node and a fourth node, and the fourth transistor. Node and a tenth transistor connected to the second power supply, the first node being an output terminal, and the second node
Is connected to the gate of the first transistor,
The third node is connected to the gate of the second transistor, the fourth node is connected to the gates of the sixth and eighth transistors, and the fourth, seventh, ninth and tenth nodes are connected.
A control signal is applied to the gates of the transistors, and an input signal is applied to the gates of the third and fifth transistors.

[0016]

1 is a circuit diagram showing a three-state buffer circuit according to an embodiment of the present invention.

In FIG. 1, in this embodiment, a P-type MOS transistor TP5 is connected between the node 1 and the power supply voltage VDD, and a P-type MOS transistor TP1 and a P-type MOS transistor TP3 are connected to the node 2 and the power supply voltage VDD. Connected in parallel between.

The N-type MOS transistor TN5 has a node 1
And the ground (GND), and the N-type MOS transistor TN2 and the N-type MOS transistor TN4 are connected in parallel between the node 3 and GND.

N-type MOS transistor TN1 and P-type MO
The S transistor TP2 is connected in parallel between the node 2 and the node 3, and the P-type MOS transistor TP4 is connected to the node 4
Connected to the node 2 and connected to the N-type MOS transistor T
N3 is connected between node 4 and GND.

The node 1 serves as an output Out terminal, the node 2 is input to the gate of the P-type MOS transistor TP5, and the node 3 is input to the gate of the N-type MOS transistor TN5.
Node 4 is a P-type MOS transistor TP2 and an N-type MOS
Input to the gate of the transistor TN4.

The control signal CNTRL is a P-type MOS.
Input signals D are input to the gates of the transistors TP3 and TP4 and the N-type MOS transistors TN2 and TN3, respectively, and are input to the P-type MOS transistor TP1 and the N-type MOS transistor TN2.

The operation of this embodiment will be described below. Control signal CN
When TRL is "H", N-type MOS transistor TN
3, the TN1 and the P-type MOS transistor TP2 are turned on, and the nodes 2 and 3 are brought into conduction.

At this time, when the input signal D is "L", the P-type MOS transistor TP1 is turned on and the N-type MO transistor TP1 is turned on.
The S transistor TN2 is turned off, and the P of the N-type MOS transistor TN5 at the level "H" from the power supply voltage VDD
To the MOS transistor TP5, the N-MOS transistor TN5 is turned on, and the level "L" from GND is output.

When the input signal D is "H", the P-type MO
The S transistor TP1 is turned off, the N-type MOS transistor TN2 is turned on, the level "L" of GND is transmitted to the P-type MOS transistor TP5 and the N-type MOS transistor TN5, the P-type MOS transistor TP5 is turned on, and the power supply voltage VDD level is reached. Output "H".

When the control signal CNTRL is "L", the P-type MOS transistors TP3 and TP4 are turned on, "H" is transmitted to the node 2 and the node 4, and the node 4 serves as a gate.
The OS transistor TN4 is turned on, and the level "L" from GND is transmitted to the gate of the N-type MOS transistor TN5. Further, the node 2 is from the "H" level to the P-type MOS.
"H" is transmitted to the gate of the transistor TP5, and the N-type MO
S transistor TN5 and P-type MOS transistor TP
Both 5 are turned off, and the output becomes high impedance regardless of the level of the input signal.

[0026]

As described above, according to the present invention, the number of elements of the 18 P and N type MOS transistors required for the conventional three-state buffer circuit is, for example, 10 P and N type MOS transistors. By reducing the number of elements and configuring a three-state buffer circuit,
When used as a bus driver when sharing a bus line such as an external output buffer or a data bus, there is an effect that the layout area can be reduced, and further, the integration degree can be improved and the speed can be improved even in the operation mode.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a three-state buffer circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional three-state buffer circuit.

[Explanation of symbols]

A Gate input of P-type MOS transistor of source power supply voltage VDD B Gate input of N-type MOS transistor of source GND 1, 2, 3, 4 Nodes TP1, TP2, TP3, TP4, TP5 P-type MO
S transistor TN1, TN2, TN3, TN4, TN5 N type MO
S transistor

Claims (2)

[Claims] 1. A first transistor connected to a first power supply and a first node serving as an output, a second transistor connected to the first node and a second power supply, and Third and fourth terminals connected in parallel to the first power source and the second node
Transistor, a fifth and a sixth transistor connected in parallel with the second power source and the third node, and the second transistor.
7th and 8th transistors connected in parallel to the second node and the third node, a ninth transistor connected to the second node and the fourth node, and a fourth node A first transistor connected to the second power supply, the first node being an output terminal, the second node being connected to the gate of the first transistor, and the third node being The fourth node is connected to the gates of the second transistors, the fourth node is connected to the gates of the sixth and eighth transistors, and the gates of the fourth, seventh, ninth, and tenth transistors are controlled. A three-state buffer circuit, wherein a signal is applied and an input signal is applied to the gates of the third and fifth transistors. 2. The first, third, fourth, eighth and ninth transistors are P-channel type, and the second, fifth, sixth, seventh and tenth transistors are N-channel type. The three-state buffer circuit according to claim 1.