JPH0637624A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To attain the high speed of a level conversion, and to reduce a chip occupancy area by reducing the number of steps by controlling a flip flop constituted of P and N type MOS transistors by controlling one gate and the other source of the two MOS transistors of the flip flop. CONSTITUTION:A CMOS invertor which receives a low voltage input signal is constituted of MOS transistors M11 and M21, and connected to a low voltage power source Vcc. The capacity of N channel MOS transistors M21, M22, and M23 is set higher than P channel MOS transistors M11, M12, and M13. When the input of the invertor is a low level, the output is a high level, an output terminal OUT is the high level for the capacity of the M23 is higher than the M13, and a low voltage input level is converted into a high voltage output level. Thus, the invertor of one stage can be obtained, so that the high speed of a converting speed can be attained, and the chip occupancy area can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit for transmitting signals between different power supply voltages.

[0002]

2. Description of the Related Art As a conventional level conversion circuit of this type, for example, one shown in FIG. 2 is known. In the figure, M12 and M13 are P-channel MOS transistors, and M22 and M23 are N-channel MOS transistors. Transistor M12 and transistor M13
The gates of the transistors M22 and M2
3 together with 3 form a flip-flop, and a transistor M
22 and M23 gate low voltage inputs are converted to high voltage outputs.

[0003]

The above-described conventional level conversion circuit is composed of a total of eight transistors, that is, a transistor forming a flip-flop and a transistor forming a two-stage inverter for controlling the flip-flop. There was a drawback that required.

Further, since the number of stages required for level conversion is large, t
There was a drawback that the pd was slow.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel level conversion circuit capable of solving the above-mentioned drawbacks inherent in the conventional technology. To do.

[0006]

In order to achieve the above object, a level conversion circuit according to the present invention is provided with a first power supply, an inverter composed of first and second MOS transistors, and a first inverter. And a fifth and a sixth MOS transistor connected to the drains of the third and fourth transistors, respectively. And a gate of one of the fifth and sixth MOS transistors and a source of the other of the fifth and sixth MOS transistors are connected to the inverter.

[0007]

In the present invention, the flip-flop is controlled by controlling the gate of one of the fifth and sixth MOS transistors constituting the flip-flop and the source of the other, thereby reducing the number of stages required for level conversion and improving tpd. is doing.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of a level conversion circuit according to the present invention.

In the figure, M11, M12 and M13 are P
Channel MOS transistor, M21, M22, M2
Reference numerals 3 denote N-channel MOS transistors, respectively.

The MOS transistors M11 and M21 form a CMOS inverter that receives a low voltage input signal, and are connected to a first low voltage power supply Vcc.

P-channel MOS transistor M12,
The source of M13 is connected to the second high-voltage power supply V _DD , and the gates thereof are connected to the drains of each other so that each drain has N-channel MOS transistors M22, M
The drains of 23 are connected to each other. The gate of the N-channel MOS transistor M22 is connected to the second high-voltage power supply, and the source is connected to the output of the above-mentioned inverter.
The source of the channel MOS transistor M23 is grounded to the common terminal, and the gate is connected to the output of the above-mentioned inverter.

Here, the capability of each transistor is set as follows. That is, the respective capabilities of the series of N-channel MOS transistors M21 and M22 and M23 are set to be larger than those of the P-channel MOS transistors M12 and M13. For example, the channel width of the P-channel MOS transistors M11, M12, M13 is 15 microns, and the channel width of the N-channel MOS transistor is 30 microns.

Now, when the input of the inverter is set to "low" level, the output becomes "high" level, which is an N-channel MOS transistor compared to the P-channel MOS transistor M13.
Output terminal OU due to the large capacity of transistor M23
T becomes "low" level, and the internal node A becomes "high" level. Similarly, when the output of the inverter is at "low" level, the internal node A becomes "low" level and the output terminal OUT becomes "high" level. Thus, the low voltage input level is converted to the high voltage output level by this operation.

In this embodiment, the number of inverters required can be one compared with the conventional circuit shown in FIG. That is, the speed of level conversion can be increased by reducing the number of inverter stages. By the way, when the 1-micron class MOS transistor, which is the current state-of-the-art device, is used, the tpd required for level conversion is about 2.7 nS in the conventional circuit, but about 2.
A speedup of about 20% can be achieved with 5 nS.

Also, the number of transistors used can be reduced from eight to six.

Although OUT is used as the output terminal in the above-mentioned embodiment, it goes without saying that the internal node A is used as the output terminal.
It goes without saying that both nodes can be used as complementary outputs.

[0018]

As described above, according to the present invention, it is possible to speed up the level conversion of signals between different power supply voltages and reduce the area occupied by the chip.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a level conversion circuit according to the present invention.

FIG. 2 is a circuit diagram of a conventional level conversion circuit.

[Explanation of symbols]

M10 to M13 ... P channel MOS transistor M20 to M23 ... N channel MOS transistor A ... Internal node IN ... Input terminal OUT ... Output terminal Vcc ... First power supply voltage terminal V _DD ... Second power supply voltage terminal GND ... Common terminal

Claims (2)

[Claims] 1. A first power source is supplied and first and second power supplies are provided.
An inverter composed of a MOS transistor of
Third and fourth MOS transistors having their respective gates cleared and the fifth and sixth MOS transistors connected to the drains of the respective transistors.
And a flip-flop composed of a transistor,
A level conversion circuit, wherein one of gates and the other sources of the fifth and sixth MOS transistors are connected to the inverter. 2. The inverter is a NOR gate or N
The level conversion circuit according to claim 1, further comprising an AND gate.