JPH0573274B2 - - Google Patents
Info
- Publication number
- JPH0573274B2 JPH0573274B2 JP4187287A JP4187287A JPH0573274B2 JP H0573274 B2 JPH0573274 B2 JP H0573274B2 JP 4187287 A JP4187287 A JP 4187287A JP 4187287 A JP4187287 A JP 4187287A JP H0573274 B2 JPH0573274 B2 JP H0573274B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- resistor
- reference voltage
- voltage generating
- reference resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に並列型Ａ／Ｄ
変換器を搭載する半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a parallel A/D device.
The present invention relates to a semiconductor device equipped with a converter.
並列型Ａ／Ｄ変換器は第３図に示すように、同
一抵抗値による基準電圧発生部と比較器とエンコ
ーダ部及び出力バツフア部で構成されている。図
中ｎは分解能を表わしており2m−１個の比較器
と基準電圧発生用抵抗（以下基準抵抗と言う）を
必要とする。基準抵抗はアルミ配線で形成される
ことが多い。これは、信学会半導体トランジスタ
研資料SSD・82−２ P9（1982）“高速低消費電
力8bit並列型Ａ／Ｄ変換LSI”に記述されている
ように、比較器の入力電流の影響をさける為に分
解能に比例して基準抵抗の値を小さくする必要が
あるからである。例えば8bit分解能では0.2Ω程度
となり、6bit分解能では１〜2Ω程度となる。
As shown in FIG. 3, the parallel A/D converter is composed of a reference voltage generating section having the same resistance value, a comparator, an encoder section, and an output buffer section. In the figure, n represents resolution, and requires 2m-1 comparators and a reference voltage generating resistor (hereinafter referred to as reference resistor). The reference resistor is often formed of aluminum wiring. This is to avoid the influence of the input current of the comparator, as described in IEICE Semiconductor Transistor Research Materials SSD 82-2 P9 (1982) "High-speed, low-power consumption 8-bit parallel A/D conversion LSI" This is because it is necessary to reduce the value of the reference resistance in proportion to the resolution. For example, with 8-bit resolution, it is about 0.2Ω, and with 6-bit resolution, it is about 1 to 2Ω.
通常アルミ配線の層抵抗は30ｍΩ／□程度であ
るから抵抗長は8bit用で100〜300μ程度、6bit用
では500〜1000μ程度になる。従つて分解能の低
いＡ／Ｄ変換器の基準抵抗は抵抗長が長くなる
為、第４図に示すように数回おり返して配置して
いる。図中基準抵抗列１及び配線１Ａ，１Ｂ，１
Ｃ，１Ｄは同一基板上に被着したアルミ膜をパタ
ーニングして形成されており、配線１Ａ，１Ｂ，
１Ｃ，１Ｄは各々比較器へ接続されている。 Normally, the layer resistance of aluminum wiring is about 30 mΩ/□, so the resistance length is about 100 to 300 μ for 8 bits and about 500 to 1000 μ for 6 bits. Therefore, since the reference resistor of an A/D converter with low resolution has a long resistance length, it is arranged in turns several times as shown in FIG. In the figure, reference resistor string 1 and wiring 1A, 1B, 1
C and 1D are formed by patterning an aluminum film deposited on the same substrate, and the wirings 1A, 1B,
1C and 1D are each connected to a comparator.
しかしながら、従来技術により、分解能は５〜
6bitであるが、精度を分解能以上に得たい場合、
以下の様な問題点があつた。第１には、Ａ／Ｄ変
換器の精度を上げるには基準電圧部の発生する電
圧の精度を上げる必要があり、これは基準抵抗
R1〜Ｒ
（2n−１）の相対精度を上げることに帰着
するが、従来例では加工工程においてアルミ膜厚
及び抵抗幅に変化が生じた場合に、Ｘ方向（第４
図）の変化に対しては同一条件で問題ないが、Ｙ
方向に対しては同一条件とはならない為抵抗値に
ずれが生じる。特に低分解能では抵抗長が長くな
る為その影響が大きい。
However, with conventional technology, the resolution is 5~
6bit, but if you want to obtain more precision than the resolution,
The following problems arose. First, in order to improve the accuracy of the A/D converter, it is necessary to increase the accuracy of the voltage generated by the reference voltage section, and this requires increasing the accuracy of the voltage generated by the reference voltage section.
This results in increasing the relative accuracy of R 1 to R (2 n -1), but in the conventional example, when changes occur in the aluminum film thickness and resistance width during the processing process, the
There is no problem under the same conditions for changes in (Fig.), but Y
Since the conditions are not the same in terms of direction, a difference occurs in the resistance value. Particularly at low resolution, the resistance length becomes long, so the effect is large.
第２には、基準抵抗部の基板温度が均一でない
場合には抵抗値変化にずれ生じ精度を低下させる
問題がある。上記基準抵抗の精度低下はＡ／Ｄ変
換器の微分直線性誤差を悪化させる要因となつて
いる。 Secondly, if the substrate temperature of the reference resistance section is not uniform, there is a problem in that resistance value changes are deviated and accuracy is reduced. The decrease in accuracy of the reference resistor is a factor that worsens the differential linearity error of the A/D converter.
本発明の基準抵抗は、当該基準抵抗を包含する
最小面積の四角形の領域内に、当該基準抵抗の両
端に接続される他の基準抵抗の一部が配置されて
いることを特徴とする。
The reference resistor of the present invention is characterized in that a part of another reference resistor connected to both ends of the reference resistor is arranged within a rectangular region of minimum area that includes the reference resistor.
次に、本発明について図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す基準抵抗の平
面図である。図において、基準抵抗列１及び配線
１Ａ，１Ｂ，１Ｃ，１Ｄは従来と同じく同一基板
上に被着したアルミ膜をパターニングして形成さ
れている。ここで配線１Ｂと配線１Ｃ間の基準抵
抗R2（図中斜線図着目すると、基準抵抗R2を包含
する四角形の領域Ｓ内に基準抵抗R1と基準抵抗
R3の一部が入り込んで配置されている点が従来
例と異なつている。 FIG. 1 is a plan view of a reference resistor showing an embodiment of the present invention. In the figure, a reference resistor array 1 and wiring lines 1A, 1B, 1C, and 1D are formed by patterning an aluminum film deposited on the same substrate, as in the conventional case. Here, the reference resistance R 2 between the wiring 1B and the wiring 1C (if you pay attention to the diagonal diagram in the figure, the reference resistance R 1 and the reference resistance
It differs from the conventional example in that a part of R 3 is placed inward.
上記本発明の基準抵抗に対し、従来と同じく加
工工程におけるアルミ膜厚の変化や抵抗幅の変化
が生じた場合を考える。Ｘ方向は従来と同じく変
化に対しすべての基準抵抗が同一条件で問題な
い。Ｙ方向は、基準抵抗R2を基準に見ると、基
準抵抗R2の一部と基準抵抗R1の一部が入れ換つ
ており、同じく基準抵抗R2の一部と基準抵抗R3
の一部も入れ換つている為、その付近での変化に
よる抵抗値変化分は相殺される。従つて、従来例
に比べ抵抗比精度の低下は少ない。又、基板上の
温度変化に対しても上記理由により同様の効果を
得ることが出来る。改善効果の割合は各基準抵抗
を乞含する最小面積の四角形Ｓのオーバラツプの
量に比例するので工程上の変動分に応じてその量
を調整すれば良い。 Let us consider a case where, with respect to the reference resistance of the present invention, a change in aluminum film thickness or a change in resistance width occurs in the processing process as in the conventional case. In the X direction, there is no problem with changes as all reference resistances are under the same conditions as in the conventional case. In the Y direction, when looking at the reference resistance R 2 as a reference, a part of the reference resistance R 2 and a part of the reference resistance R 1 are exchanged, and a part of the reference resistance R 2 and the reference resistance R 3 are also replaced.
Since a part of is also replaced, the change in resistance due to changes in that vicinity is canceled out. Therefore, there is less decrease in resistance ratio accuracy compared to the conventional example. Furthermore, similar effects can be obtained with respect to temperature changes on the substrate for the above reasons. Since the rate of improvement effect is proportional to the amount of overlap of the rectangles S of the minimum area that include each reference resistance, the amount can be adjusted according to the variation in the process.
全並列型Ａ／Ｄ変換器において微分直線性誤差
の悪化は、比較器の基準電圧レベル決めている基
準抵抗の抵抗比のずれに起因することが多く、こ
の様な場合に上記本発明を実施することにより微
分直線性誤差を改善し高精度のＡ／Ｄ変換器を実
現出来る。 Deterioration of the differential linearity error in a fully parallel A/D converter is often caused by a deviation in the resistance ratio of the reference resistor that determines the reference voltage level of the comparator, and in such cases, the present invention can be implemented. By doing so, differential linearity errors can be improved and a highly accurate A/D converter can be realized.
第２図は本発明の第２実施例の平面図である。
第２図は基準抵抗の抵抗長が比較的短い場合の実
施例で、抵抗形状が異なる点以外は第１実施例と
同一である。本例では第１実施例のようにＹ方向
について基準抵抗R2の一部と基準抵抗R1の一部
及び基準抵抗R3の一部と入れ換つている部分は
ないが、基準抵抗R2図中斜視部を包含する最小
面積の四角形Ｓの中に基準抵抗R1及び基準抵抗
R3の一部が入り込んでいる為、Ｙ方向の部分的
な変化に対して同一条件となる部分が生じる。従
つて、抵抗値変化分も従来に比べ少なく抵抗比精
度の改善が可能である。 FIG. 2 is a plan view of a second embodiment of the invention.
FIG. 2 shows an embodiment in which the resistance length of the reference resistor is relatively short, and is the same as the first embodiment except for the difference in the resistance shape. In this example, unlike the first embodiment, there is no part of the reference resistance R 2 replaced with a part of the reference resistance R 1 and a part of the reference resistance R 3 in the Y direction, but the reference resistance R 2 In the figure, the reference resistance R 1 and the reference resistance
Since a portion of R 3 is included, there is a portion where the same conditions apply to partial changes in the Y direction. Therefore, the amount of change in resistance value is also smaller than in the past, making it possible to improve resistance ratio accuracy.
以上説明したように本発明によれば、基準抵抗
の形状を変るだけで、従来に比べ抵抗相対比を改
善出来、高精度Ａ／Ｄ変換器用基準抵抗として有
用である。
As explained above, according to the present invention, by simply changing the shape of the reference resistor, the relative resistance ratio can be improved compared to the conventional one, and the present invention is useful as a reference resistor for high-precision A/D converters.
又、本発明の説明ではアルミ配線による基準抵
抗について説明したが、他の金属あるいは金属シ
リサイド又はシリコン被膜による抵抗及び拡散抵
抗についても同様の効果を得ることが可能であ
る。 Furthermore, although the present invention has been described with reference to a reference resistance made of aluminum wiring, similar effects can be obtained with resistances made of other metals, metal silicides, or silicon films, and with diffused resistances.
第１図は本発明による基準抵抗の平面図、第２
図は本発明の第２実施例による基準抵抗の平面
図、第３図は並列型Ａ／Ｄ変換器の接続回路図、
第４図は従来の基準抵抗の平面図。
１……基準抵抗列、１Ａ，１Ｂ，１Ｃ，１Ｄ…
…配線、Ｓ……領域、R1，R2，R3，R4，Ｒ
（2n
−１）……基準抵抗、C1，C2，C3，C4，Ｃ
（2n−
１）……比較器、VIN……アナログ入力端子。
FIG. 1 is a plan view of a reference resistor according to the present invention, and FIG.
The figure is a plan view of a reference resistor according to the second embodiment of the present invention, and FIG. 3 is a connection circuit diagram of a parallel type A/D converter.
FIG. 4 is a plan view of a conventional reference resistor. 1...Reference resistance series, 1A, 1B, 1C, 1D...
...Wiring, S...Region, R 1 , R 2 , R 3 , R 4 , R (2 n
-1)...Reference resistance, C 1 , C 2 , C 3 , C 4 , C (2 n -
1)...Comparator, V IN ...Analog input terminal.
Claims (1)
成する半導体装置において、前記基準電圧発生用
抵抗を包含する最少面積の四角形の領域内に当該
基準抵抗の両端に接続される他の基準電圧発生用
抵抗の一部が配置されていることにより、前記基
準電圧発生用抵抗と前記他の基準電圧発生用抵抗
との抵抗値の変化分が相殺されることを特徴とす
る半導体装置。1. In a semiconductor device in which a reference voltage generating reference resistor is formed on a semiconductor substrate, another reference voltage generating resistor is connected to both ends of the reference voltage generating resistor within a rectangular region of minimum area that includes the reference voltage generating resistor. A semiconductor device characterized in that a portion of the resistor is arranged so that changes in resistance values between the reference voltage generating resistor and the other reference voltage generating resistor are canceled out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4187287A JPS63207165A (en) | 1987-02-24 | 1987-02-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4187287A JPS63207165A (en) | 1987-02-24 | 1987-02-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63207165A JPS63207165A (en) | 1988-08-26 |
| JPH0573274B2 true JPH0573274B2 (en) | 1993-10-14 |
Family
ID=12620353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4187287A Granted JPS63207165A (en) | 1987-02-24 | 1987-02-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63207165A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW330334B (en) * | 1997-08-23 | 1998-04-21 | Winbond Electronics Corp | Static random access memory polysilicon load structure and manufacturing method |
-
1987
- 1987-02-24 JP JP4187287A patent/JPS63207165A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63207165A (en) | 1988-08-26 |
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