JPH0438602Y2 - - Google Patents
Info
- Publication number
- JPH0438602Y2 JPH0438602Y2 JP1985196662U JP19666285U JPH0438602Y2 JP H0438602 Y2 JPH0438602 Y2 JP H0438602Y2 JP 1985196662 U JP1985196662 U JP 1985196662U JP 19666285 U JP19666285 U JP 19666285U JP H0438602 Y2 JPH0438602 Y2 JP H0438602Y2
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- voltage
- layer
- layers
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000284 extract Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
- Attenuators (AREA)
Description
【考案の詳細な説明】
イ 産業上の利用分野
本考案はデジタル・アナログ（Ｄ／Ａ）変換器
あるいはアナログ・デジタル（Ａ／Ｄ）変換器に
用いられる直列接続された抵抗列による分圧回路
に関し、特に半導体基板上に形成される集積回路
で構成されるものに関する。[Detailed description of the invention] A. Industrial application field This invention is a voltage divider circuit using a series-connected resistor string used in a digital-to-analog (D/A) converter or an analog-to-digital (A/D) converter. In particular, the present invention relates to integrated circuits formed on semiconductor substrates.
ロ 従来の技術
アナログ情報を扱い、デジタルで演算する情報
処理装置においてＡ／Ｄ変換器もしくはＤ／Ａ変
換器はなくてはならないものである。これら変換
器のIC化は既にされている（例えば特公昭60−
17260号公報参照）が、これら変換器に用いられ
る直列接続された抵抗列による分圧回路は集積回
路上では第３図のように構成される。３１は多結
晶シリコンよりなる抵抗層で半導体基板上に絶縁
膜を介して並列に選択的に形成されている。抵抗
層３１の表面は絶縁膜に覆われ、各抵抗層３１の
両端と中間の複数箇所に抵抗層とのコンタクトの
ためのスルーホール３２が絶縁膜に設けられて、
該スルーホール３２部で抵抗層３１とコンタクト
をとる配線層３３が設けられている。抵抗層３１
は配線層３３によつて直列に接続されている。直
列接続された抵抗層の両端に基準電位V1，V2が
印加されて、V1とV2の電位差を分割したものが
配線層３３によつて取り出される。B. Prior Art An A/D converter or a D/A converter is indispensable in an information processing device that handles analog information and performs digital calculations. These converters have already been integrated into ICs (for example,
(See Japanese Patent No. 17260) However, the voltage dividing circuit using series-connected resistor strings used in these converters is configured on an integrated circuit as shown in FIG. Reference numeral 31 denotes a resistance layer made of polycrystalline silicon, which is selectively formed in parallel on the semiconductor substrate with an insulating film interposed therebetween. The surface of the resistance layer 31 is covered with an insulating film, and through holes 32 for contacting the resistance layer are provided in the insulating film at a plurality of locations at both ends and in the middle of each resistance layer 31.
A wiring layer 33 is provided to make contact with the resistance layer 31 at the through hole 32 portion. resistance layer 31
are connected in series by a wiring layer 33. Reference potentials V 1 and V 2 are applied to both ends of the resistive layers connected in series, and a divided potential difference between V 1 and V 2 is extracted by the wiring layer 33 .
第３図はデジタル信号として４ビツトのものに
対応しているもので、単位抵抗としては16（＝24）
個が用意されている。通常ｎビツトのデジタル信
号に対して2n個の抵抗が必要となるため、抵抗層
の数も偶数本用意される事が多い。 Figure 3 corresponds to a 4-bit digital signal, and the unit resistance is 16 (=2 4 ).
pieces are available. Normally, 2n resistors are required for an n-bit digital signal, so an even number of resistor layers is often prepared.
Ｄ／Ａ（あるいはＡ／Ｄ）変換器では、分圧回
路で分割して取り出せれる範囲の電圧のうち中央
付近の電圧が頻繁に選択されるように分圧回路で
の分割電圧範囲が決められて設計される。これは
安定した変換動作を確保するためである。 In a D/A (or A/D) converter, the divided voltage range of the voltage divider circuit is determined so that the voltage near the center of the range of voltages that can be divided and extracted by the voltage divider circuit is frequently selected. Designed with This is to ensure stable conversion operation.
ところが抵抗層が偶数本であると、分圧回路で
取り出せれる電圧の中央は第４図に示す点Ａの位
置である。第４図は第３図の対応回路図である。
点Ａの位置は配線層と抵抗層のコンタクト抵抗
RCや配線層の配線抵抗RAの影響を受ける。抵抗
層と抵抗層を接続するところではコンタクト抵抗
RCと配線抵抗RAが、抵抗層による単位抵抗Ruに
直列和されるので、点Ａのところで分圧誤差が生
じる。つまり、分割されて出力される信号は点Ａ
を境に、分割抵抗の違いから、その前後で分圧誤
差が大きく、Ｄ／Ａ（あるいはＡ／Ｄ）変換器に
用いた場合、変換誤差を大きくする原因となつて
いた。 However, if there is an even number of resistance layers, the center of the voltage that can be taken out by the voltage dividing circuit is at point A shown in FIG. FIG. 4 is a circuit diagram corresponding to FIG. 3.
The position of point A is the contact resistance between the wiring layer and the resistance layer.
It is affected by R C and wiring resistance R A of the wiring layer. Contact resistance occurs where the resistance layers are connected.
Since R C and wiring resistance R A are summed in series with the unit resistance R u formed by the resistance layer, a voltage division error occurs at point A. In other words, the divided and output signal is at point A
Due to the difference in the dividing resistance, there is a large voltage division error before and after the dividing resistor, which causes a large conversion error when used in a D/A (or A/D) converter.
ハ 考案が解決しようとする問題点
上述の如く、従来の分圧回路においては、分割
して取り出せれる範囲の電圧のうち中央付近の電
圧が頻繁に選択されるにもかかわらず、分圧回路
の抵抗列の中央付近で分圧誤差が大きく、Ｄ／Ａ
（あるいはＡ／Ｄ）変換器の変換誤差を大きくす
るという欠点を有していた。C. Problems to be solved by the invention As mentioned above, in conventional voltage divider circuits, the voltage near the center of the range of voltages that can be divided is often selected. The voltage division error is large near the center of the resistor string, and the D/A
(or A/D) converter has the disadvantage of increasing the conversion error.
本考案は、分圧回路の抵抗列の中央付近の抵抗
による分割電圧の分圧誤差の発生を抑え、Ｄ／Ａ
（あるいはＡ／Ｄ）変換器に用いて良好な分圧回
路を提供することを目的とする。 This invention suppresses the occurrence of voltage division errors in the divided voltage due to the resistance near the center of the resistor string of the voltage divider circuit, and
The purpose of this invention is to provide a good voltage dividing circuit for use in (or A/D) converters.
ニ 問題点を解決するための手段
本考案は、基板上に形成された複数本の抵抗層
と、各抵抗層を覆う絶縁層と、該絶縁層に設けら
れた複数のスルーホールを介して前記抵抗層と接
続する複数の配線層とを備え、該配線層によつ
て、抵抗層全てが直列に接続され、且つ直列接続
された抵抗層の両端に印加された基準電位を分割
して、抵抗層から分割電圧を取り出す分圧回路に
おいて、
前記抵抗層は奇数本であり、中央に形成されて
いる抵抗層と接続されている配線層のうち中央の
配線層もしくはそれに相当する２つの配線層を中
心に、基準電位が印加されている夫々の端部まで
の配線層の数は、その両側で等しい分圧回路であ
る。D. Means for Solving the Problems The present invention includes a plurality of resistance layers formed on a substrate, an insulating layer covering each resistance layer, and a plurality of through holes provided in the insulating layer. A plurality of wiring layers are connected to the resistance layer, and all the resistance layers are connected in series by the wiring layer, and a reference potential applied to both ends of the resistance layers connected in series is divided, and the resistance layer is connected to the resistance layer. In a voltage divider circuit that takes out divided voltages from layers, the number of resistor layers is an odd number, and the central wiring layer or two wiring layers corresponding to the central wiring layer are connected to the resistive layer formed in the center. The number of wiring layers from the center to each end to which a reference potential is applied is an equal voltage divider circuit on both sides.
ホ 作用
分圧回路で、分割して取り出される範囲の電圧
のうち、真ん中の電圧値を取り出すための抵抗
は、抵抗層の中央に位置されているため、コンタ
クト抵抗や配線抵抗が分割抵抗に直接係わること
はない。E. Effect In a voltage divider circuit, the resistor for extracting the middle voltage value out of the range of voltages to be divided and extracted is located in the center of the resistance layer, so the contact resistance and wiring resistance are directly connected to the dividing resistor. Nothing to do with it.
ヘ 実施例
第１図は本考案の一実施例の平面パターン図
で、デジタル信号として４ビツトのものに対応す
るものである。１，２，３は多結晶シリコンより
なる抵抗層で、半導体基板上に図示しない絶縁膜
を介して、３本の抵抗層が並列に選択的に形成さ
れている。４は抵抗層１，２，３表面を覆う図示
しない絶縁膜に設けられた抵抗層１，２，３との
コンタクトのためのスルーホール、５は該スルー
ホール２を介して抵抗層１，２，３と接続されて
引出された配線層である。各抵抗層１，２，３は
配線層５によつて直列に繋がれていて、直列接続
された抵抗層の両端には基準電圧V1，V2が印加
されている。そして、配線層５によつて抵抗層の
中途位置あるいは抵抗層間点の電圧が取り出され
る。ここで中央に形成されている抵抗層２の真ん
中の配線層５′から基準電圧V1が印加される配線
層までに設けてある配線層の数と、抵抗層２の真
ん中の配線層５′から基準電圧V2が印加される配
線層までに設けてある配線層の数は等しい。F. Embodiment FIG. 1 is a plane pattern diagram of an embodiment of the present invention, which corresponds to a 4-bit digital signal. Reference numerals 1, 2, and 3 denote resistance layers made of polycrystalline silicon, and three resistance layers are selectively formed in parallel on a semiconductor substrate with an insulating film (not shown) interposed therebetween. Reference numeral 4 indicates a through hole for contacting the resistance layers 1, 2, and 3 provided in an insulating film (not shown) covering the surfaces of the resistance layers 1, 2, and 3; , 3 and are drawn out. The resistance layers 1, 2, and 3 are connected in series by a wiring layer 5, and reference voltages V 1 and V 2 are applied to both ends of the resistance layers connected in series. Then, the wiring layer 5 extracts a voltage at a midway position of the resistance layer or a point between the resistance layers. Here, the number of wiring layers provided from the wiring layer 5' in the middle of the resistance layer 2 formed in the center to the wiring layer to which the reference voltage V1 is applied, and the wiring layer 5' in the middle of the resistance layer 2. The number of wiring layers provided from the wiring layer to the wiring layer to which the reference voltage V 2 is applied is equal.
第２図に第１図の対応回路図を示す。この分圧
回路で取り出すことのできる電圧の中央の電圧は
点Ｂ（配線層５′）である。分圧回路からは取り出
される電圧の中央の電圧（点Ｂ）付近の電圧が頻
繁に選択されるが、点Ｂの付近の電圧が取り出さ
れても、点Ｂ付近で電圧を取り出すための分割抵
抗の中にコンタクト抵抗RCや配線抵抗RAは含ま
れてこない。即ち点Ｂ近傍の分割抵抗の値は等し
く、大きな分圧誤差は生じない。従つて、本考案
の分圧回路を用いたＤ／Ａ（あるいはＡ／Ｄ）変
換器の出力信号は、その頻度の高い電圧付近での
変換誤差を小さいものにすることができる。 FIG. 2 shows a corresponding circuit diagram of FIG. 1. The center voltage of the voltages that can be taken out by this voltage dividing circuit is at point B (wiring layer 5'). A voltage near the center voltage (point B) is often selected from a voltage divider circuit, but even if a voltage near point B is taken out, a dividing resistor is used to take out the voltage near point B. does not include contact resistance R C or wiring resistance R A. That is, the values of the dividing resistors near point B are equal, and no large voltage dividing error occurs. Therefore, the output signal of the D/A (or A/D) converter using the voltage dividing circuit of the present invention can have a small conversion error in the vicinity of the frequently occurring voltage.
尚本実施例では、奇数本ある抵抗層の中央の層
において、単位抵抗Ru（分割抵抗）は偶数個であ
るが、奇数個の場合でも、中央の単位抵抗Ruの
両端に設けられる配線層と夫々に近い基準電圧が
印加される配線層までの間に設けられる配線層の
数を同じにしても、本実施例と同様の効果が得ら
れるのは述べるまでもない。 In this embodiment, there is an even number of unit resistors R u (divided resistors) in the center layer of the odd number of resistance layers, but even in the case of an odd number, the wiring provided at both ends of the central unit resistor R u Needless to say, the same effect as in this embodiment can be obtained even if the number of wiring layers provided between the wiring layer and the wiring layer to which a reference voltage close to each layer is applied is the same.
本実施例はデジタル信号として４ビツトのもの
に対応するものであるが何ビツトのものでもかま
わなく、ビツト数に応じて単位抵抗の数を増やせ
ばよい。 Although this embodiment corresponds to a digital signal of 4 bits, any number of bits may be used, and the number of unit resistors may be increased according to the number of bits.
ト 考案の効果
本考案は以上の説明から明らかな如く、分圧回
路で取り出せれる範囲の電圧のうち中央の電圧を
取り出すための単位抵抗が抵抗層の中央に位置さ
れるので、中央の電圧近傍の電圧を取り出すため
の分割抵抗の中にコンタクト抵抗や配線抵抗の成
分が含まれることはないので、本考案を用いた
Ｄ／Ａ（あるいはＡ／Ｄ）変換器の出力信号は、
分圧回路の分圧誤差による大きな変換誤差をなく
すことができる。G. Effect of the invention As is clear from the above explanation, in the present invention, the unit resistor for extracting the central voltage of the range of voltages that can be extracted by the voltage divider circuit is located at the center of the resistance layer. Since contact resistance and wiring resistance components are not included in the divided resistance for extracting the voltage, the output signal of the D/A (or A/D) converter using the present invention is as follows.
Large conversion errors due to voltage division errors in the voltage divider circuit can be eliminated.
第１図は本考案の一実施例の平面パターン図、
第２図は第１図の対応回路図、第３図は従来の分
圧回路の平面パターン図、第４図は第３図の対応
回路図である。
１，２，３……抵抗層、４……スルーホール、
５，５′……配線層。
FIG. 1 is a plan pattern diagram of an embodiment of the present invention.
2 is a circuit diagram corresponding to FIG. 1, FIG. 3 is a plan pattern diagram of a conventional voltage dividing circuit, and FIG. 4 is a circuit diagram corresponding to FIG. 3. 1, 2, 3...resistance layer, 4...through hole,
5, 5'... Wiring layer.
Claims (1)
層を覆う絶縁層と、該絶縁層に設けられた複数の
スルーホールを介して前記抵抗層と接続する複数
の配線層とを備え、該配線層によつて、抵抗層全
てが直列に接続され、且つ直列接続された抵抗層
の両端に印加された基準電圧を分割して、抵抗層
から分圧電圧を取り出す分圧回路において、 奇数本の前記抵抗層が前記配線層により直列に
接続され、電位的に中間に位置する抵抗層の中心
部近傍に前記配線層が接続されて前記基準電圧の
中間電圧あるいは中間電圧に相当する２電圧が取
り出されると共に、該配線層を中心にしてその他
の複数の配線層が対象に接続されて前記基準電圧
の分圧電圧がそれぞれ取り出されることを特徴と
する分圧回路。[Claims for Utility Model Registration] A plurality of resistance layers formed on a substrate, an insulating layer covering each resistance layer, and a connection to the resistance layer through a plurality of through holes provided in the insulating layer. All of the resistance layers are connected in series through the wiring layers, and a reference voltage applied to both ends of the resistance layers connected in series is divided, and a divided voltage is generated from the resistance layer. In the voltage divider circuit for taking out the reference voltage, an odd number of the resistance layers are connected in series by the wiring layer, and the wiring layer is connected near the center of the resistance layer located in the middle in terms of potential, so that an intermediate voltage of the reference voltage is obtained. Alternatively, two voltages corresponding to the intermediate voltage are taken out, and a plurality of other wiring layers are connected to the wiring layer as a center, and divided voltages of the reference voltage are respectively taken out. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985196662U JPH0438602Y2 (en) | 1985-12-20 | 1985-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985196662U JPH0438602Y2 (en) | 1985-12-20 | 1985-12-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62103317U JPS62103317U (en) | 1987-07-01 |
| JPH0438602Y2 true JPH0438602Y2 (en) | 1992-09-09 |
Family
ID=31155687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985196662U Expired JPH0438602Y2 (en) | 1985-12-20 | 1985-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438602Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111223621A (en) * | 2018-11-26 | 2020-06-02 | 致茂电子(苏州)有限公司 | Resistor with a resistor element |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0728219B2 (en) * | 1988-07-27 | 1995-03-29 | シャープ株式会社 | A / D converter |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57203326A (en) * | 1981-06-09 | 1982-12-13 | Toshiba Corp | Analog-to-digital converter |
-
1985
- 1985-12-20 JP JP1985196662U patent/JPH0438602Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57203326A (en) * | 1981-06-09 | 1982-12-13 | Toshiba Corp | Analog-to-digital converter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111223621A (en) * | 2018-11-26 | 2020-06-02 | 致茂电子(苏州)有限公司 | Resistor with a resistor element |
| CN111223621B (en) * | 2018-11-26 | 2022-07-19 | 致茂电子(苏州)有限公司 | Resistor with a resistor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62103317U (en) | 1987-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4703302A (en) | Resistance ladder network | |
| EP0348918B1 (en) | D/A converter | |
| JP3843942B2 (en) | D / A converter and A / D converter | |
| JPH05206861A (en) | Resistance string circuit | |
| JP3575026B2 (en) | Ladder type resistance circuit, digital-analog converter and semiconductor device using the same | |
| KR860007685A (en) | Resistors and electronic devices using them | |
| JPH0438602Y2 (en) | ||
| JPH08213912A (en) | Resistance string provided with resistance of equal resistance | |
| JP3246541B2 (en) | Semiconductor device | |
| JPH08167847A (en) | Digital/analog converter | |
| JP3028420B2 (en) | Semiconductor integrated device | |
| JPS6329962A (en) | Semiconductor device | |
| US6768440B1 (en) | Digital-to-analog converters with reduced parasitics and associated methods | |
| US5084703A (en) | Precision digital-to-analog converter | |
| JP2663845B2 (en) | Digital to analog converter | |
| US5554989A (en) | A/D converter having folded arrangement of voltage comparator | |
| JPH0728060B2 (en) | Magnetic resistance element | |
| JP2735712B2 (en) | Digital to analog converter | |
| JPH065788A (en) | Semiconductor device | |
| JPH06188371A (en) | Semiconductor integrated circuit device | |
| JPH0578214B2 (en) | ||
| JPS6412103B2 (en) | ||
| JPH01164124A (en) | Digital/analog converter | |
| JPH0448308A (en) | Constant current source circuit | |
| JPS63269621A (en) | Comparison type analog/digital converter |