JPH0728219B2 - A / D converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to an A / D converter having a small conversion error.

<Prior Art> Conventionally, there is an A / D converter as shown in FIG. This A / D converter is a 6-bit parallel comparison type A / D converter, and (2 ⁶ -1) comparators are included so that the area does not become large when configured with an LSI (Large Scale Integrated Circuit). (C1
~ C63) are arranged in two rows, facing each other in half. The two ^six resistors (r1 to r64) to form a ladder resistor connected in series worth distribution corresponding to each comparator above. That is, resistors r1 to r31 and resistors r32 to r6
4 is continuously and linearly connected, and since the resistance r31 and the resistance r32 in the folded portion are separated from each other, they are connected by aluminum wiring.

The open end of the resistor r1 is grounded, and the resistor r1 and a resistor r2 (not shown) are connected to one input terminal of the comparator C1. In the same manner, the two resistors are connected to one terminal of the comparator one after another, and then folded back along the aluminum wiring and finally between the resistors r63 and r64 to one terminal of the comparator C63. It is connected. Then, the reference voltage Vref is applied to the open end of the resistor r64. On the other hand, the analog input voltage Vin is applied to the other input terminal of each comparator (C1 to C63).
Is applied. That is, the comparator C1 has an analog input voltage
Vin compares the comparison voltage Vref-1 / 64, the comparator C29 compares the analog input voltage Vin and the comparison voltage Vref29 / 29/64, and in the same manner, the comparator Cn compares the analog input voltage Vin. The voltage Vref · n / 64 is compared. Therefore, the comparison voltage by the resistors r31 and r32 at the folded portion of the ladder resistor is approximately Vref / 2.

The output terminal of each comparator (C1 to C63) is
~ C63) are connected to one of the input terminals of the (2 ⁶ -1) AND gates (A1 to A63) arranged in an active "L" state, and the AND gate (1 A2-
It is connected to the other input terminal of A63) in the active “H” state.

Bit lines 1 arranged in 6 rows at a right angle between the lines connecting the facing AND gates of the AND gates (A1 to A63) arranged in the above 2 rows and the AND gates arranged in the above 2 rows ~ NFET (n-channel field effect transistor) is arranged at the intersection with the bit line 6. And
The drain terminal of each NFET is connected to the corresponding bit line,
The source terminal is grounded. Furthermore, the output terminal of each AND gate has a drain terminal connected to the bit line of the bit to which "1" is set when the comparison result of the comparator corresponding to the AND gate is expressed by 6-bit conversion data. Connected to the gate terminal of the NFET.

The bit lines 1 to 6 corresponding to the 1st to 6th bits of the A / D converter having the above configuration are precharged to "H", and the analog input voltage Vin is applied to the input terminal. Then, the comparators C1 to C63 compare the comparison voltage value with the analog input voltage value Vin, and as a result, the output of the comparator Cn- ₁ is "H" and the output signal of the comparator Cn is "L". The output signal of the AND gate An becomes "H". Therefore, according to the output signal "H" of the AND gate An, the comparator Cn takes charge of "1" of the 6-bit digital conversion value.
The gate terminal of the NFET whose drain terminal is connected to the bit line corresponding to the bit to be set becomes "H", and the NFET is turned on. Then, only the bit line connected to the drain terminal of the NFET becomes "L", which is inverted by the inverter and converted data "H" is output. Since the other bit lines remain "H", they are inverted by the inverter and the converted data "L" is output.

<Problems to be Solved by the Invention> However, in the conventional A / D conversion device, between the resistors r31 and r32 whose comparison voltage is approximately Vref / 2, in other words,
Between the digital conversion circuit that sets the lower 2 bits of the converted data to be output to "11" and the digital conversion circuit that sets the lower 2 bits to "00". The portion where the ladder resistance is turned up is provided at "from" 00 "), and since the separated resistors r31 and r32 are connected by aluminum wiring,
The layout characteristics of the ends of the resistors in the folded portion are different from the layout characteristics of the ends of the other resistors, so that a folding error is likely to occur due to noise or the like, which causes a problem that a large conversion error occurs.

That is, for example, the value of the analog input voltage Vin is Vin ≈ Vref
In the case of / 2, if there is no aliasing error and it is normal, the comparator C1
The output signals of the comparator C31 are "H", and the output signals of the comparator C32 to the comparator C63 are "L". Therefore, the output signal of only the AND gate A32 becomes "H", and the NFET 8 is turned on. Then, bit line 1 precharged to "H"
~ Of the bit lines 6, only the bit line 6 changes to "L", and the other bit lines remain "H". The signals on the bit lines 1 to 6 are transmitted to the inverters I1 to I, respectively.
The 6-bit conversion data inverted and output by I6 becomes "100000".

However, even though the value of the input voltage Vin is Vin≈Vref / 2, noise or the like is generated due to the layout characteristic near the turnaround between the resistors r31 and r32, and for example, the comparator C1 to the comparator C30. And the output signal of the comparator C32 is "H"
Then, it is assumed that the output signals of the comparator C31 and the comparators C33 to C63 become "L". Then, AND gate
The output signals of the two AND gates A31 and A33 become "H", and NFET9 to NFET14 and NFET15 are turned on. Then, all the bit lines 1 to 6 precharged to "H" change to "L", and the inverter
The 6-bit conversion data which is inverted by I1 to inverter I6 and output is “111111”. Therefore, the conversion error with the correct conversion value "100000" in this case is 31, which is a large conversion error.

Further, for example, it is assumed that the output signals of the comparators C1 to C29 and the comparator C31 are “H”, and the output signals of the comparator C30 and the comparators C32 to C63 are “L”. In that case, the output signals of the two AND gates of AND gate A30 and AND gate A32 become "H", bit lines 2 to 6 change to "L", and the output 6-bit conversion data Becomes "111110". Therefore, the conversion error with the correct conversion value "100000" in this case is as large as 30.

Further, for example, it is assumed that the output signals of the comparators C1 to C31 and the comparator C33 become “H”, and the output signals of the comparator C32 and the comparators C34 to C63 become “L”. In that case, the 6-bit conversion data output in the same manner is "10
0010 ". Therefore, the correct conversion value" 1 "in this case.
The conversion error with 00000 "is 2.

Therefore, an object of the present invention is to provide an A / D conversion device that minimizes a conversion error in a folded portion of a ladder resistance and does not cause a large error.

<Means for Solving the Problems> In order to achieve the above object, the A / D conversion device of the present invention comprises:
The reference voltage is divided by the ladder resistor having only one turn-back portion, and the plurality of comparators that sequentially compare the reference voltage set in stages with the analog input voltage and the highest voltage division among the adjacent two or more comparators are selected. When the output signal of the corresponding comparator is "L" and the output signal of the other comparator is "H", the switching element connected to the predetermined bit line among the pre-charged bit lines is switched. And having an AND gate for outputting a signal for inverting the output signal of the predetermined bit line, in the parallel comparison type A / D conversion device for converting an analog input signal into a digital signal, the converted digital signal An AND gate that outputs a signal for setting the lower 2 bits to “11” and a signal that is adjacent to the AND gate and that sets the lower 2 bits of the converted digital signal to “00” It is characterized in that the folded-back portion of the ladder resistor is provided at a position other than the position corresponding to the AND gate for outputting.

<Operation> When the analog input voltage is input to the plurality of comparators, the reference voltage is divided by the ladder resistor having the folded portion and the comparison voltage set in stages and the analog input voltage are generated by the plurality of comparators. Compared sequentially. When the output signal of the comparator corresponding to the highest voltage division of the two or more adjacent comparators is “L” and the output signals of the other comparators are “H”, the predetermined bit A signal for switching the switching element connected to the line is output by the AND gate. Then, the switching element is switched by the output signal of the AND gate, the signal of the predetermined bit line of the pre-charged bit lines is inverted, and the analog input signal is converted into a digital signal.

At that time, the only folding part in the ladder resistor sets the lower 2 bits of the converted digital signal to "11".
And a gate for outputting a signal to output the signal and a lower 2 of the converted digital signal adjacent to the AND gate.
Since it is provided at a location other than the location corresponding to the AND gate that outputs the signal to set the bit to "00", even if a folding error occurs due to noise etc. at the folding section of the ladder resistance, it will be converted. The digital signal that is output as a result does not have a value that is significantly different from the digital signal that has been correctly converted.

<Example> Hereinafter, the present invention will be described in detail with reference to illustrated examples.

FIG. 1 is a circuit diagram of a 6-bit parallel comparison type A / D converter according to the A / D converter of the present invention.

(2 ⁶ -1) comparators (C1 to C63) are comparators C1 to C
33 and comparators C34 to C63 are divided into two groups. The two groups of comparators are arranged in two rows, and the comparators C1 to C29 and the comparators C34 to C62 are arranged to face each other.
The two ^six resistors (r1 to r64) are connected in series is high value in correspondence with the respective comparators above with ladder resistor are formed. That is, the resistors r1 to r33 and the resistors r34 to r6.
Since 4 is connected continuously and linearly, and the resistors r33 and r34 in the folded portion are separated from each other, they are connected by aluminum wiring.

The open end of the resistor r1 is grounded, and the resistor r1 and a resistor r2 (not shown) are connected to one input terminal of the comparator C1. In the same manner, the two resistors are connected to one input terminal of the comparator one after another, and then folded back along the aluminum wiring and finally between the resistor r63 and the resistor r64 to one terminal of the comparator C63. It is connected. Then, the reference voltage Vref is applied to the open end of the resistor r64. On the other hand, the analog input voltage Vin is applied to the other input terminal of each comparator (C1 to C63).
Is applied. That is, the comparator C1 has an analog input voltage
Compare Vin with the comparison voltage Vref · 1/64, and output “H” if the analog input voltage is higher than the comparison voltage. The comparator C28 compares the input voltage Vin with the comparison voltage Vref · 28/64, and in the same manner, the comparator Cn compares the input voltage Vn with the comparison voltage Vref · n / 64.

The output terminal of each comparator (C1 to C63) is
~ C63) are connected to one of the input terminals of the (2 ⁶ -1) AND gates (A1 to A63) arranged in an active "L" state, and the AND gate (1 A2-
It is connected to the other input terminal of A63) in the active “H” state.

AND gates arranged in the above two rows (A1 to A29 and A34
~ A63) and a line connecting the facing AND gates to each other and the bit lines 21 to 26 arranged in 6 rows at a right angle between the AND gates arranged in the above 2 rows, the NFET is formed at the intersection.
Are arranged. The drain terminal of each NFET is connected to the corresponding bit line, and the source terminal is grounded. In addition, each AND gate (for example, AND gate A2
The output terminal of 8) is connected to the corresponding comparator (for example, comparator C2
The comparison result of 8) is converted into 6-bit conversion data (for example, “011
Bit line (eg, bit line 23 to bit line 2) corresponding to the bit to be set to "1" when expressed by 100 ")
Connected to the gate terminal of the NFET whose drain terminal is connected to 5).

Further, at the intersection of the extension line of the output terminal of the AND gate A30 and the bit line 21 to bit line 26, the corresponding comparator C3
The bit line of the bit to be set to "1" when the result of comparison with the comparator C29 immediately before 0 is represented by the 6-bit conversion data "011100" (that is, the bit lines 22 to 22).
NFET is placed in 25). Then, while the drain terminal of each NFET is connected to the corresponding bit line,
The source terminal of is grounded. The gate terminal is connected to the output terminal of the AND gate A30.

In the same manner, the comparator C31 (C32, C33) and the preceding comparator at the intersection of the extension line of the output terminal of the AND gate A31 (A32, A33) and the bit line 21 to bit line 26 are similarly processed. C30 (C3
NFET is arranged on the bit line corresponding to the bit for which "1" should be set when the comparison result with 1, C32) is expressed by the conversion data of 6 bits. The drain terminal of this NFET is connected to the corresponding bit line, while the source terminal is grounded. Also, the gate terminal is AND gate A31 (A
32, A33) output terminal.

That is, in this A / D converter, the output 6
At the location of the digital conversion circuit (that is, between the resistance r31 and the resistance r32) that sets 1 to the 6th bit which is the MSB (the most significant bit) by setting the lower 2 bits to "00" in the conversion data of the bit. Without turning back the ladder resistance, the resistance r33
Ladder resistance should be folded back between the resistance r34 and the resistance r34.
Then, a digital conversion circuit (comparator C32, AND gate
A32 and NFET27, comparator C33, AND gate A33, NFET2
8 and NFET29) are arranged corresponding to the resistors r32 and r33.

The A / D conversion device having the above configuration operates as follows to perform A / D conversion. First, the bit lines 21 to 26 corresponding to the 1st to 6th bits of the output converted data are precharged to "H", and the analog input voltage Vin is input to the input terminal. Then, each of the comparators C1 to C63 compares the comparison voltage value with the analog input voltage value Vin, and based on the comparison result, the AND of the portion where the output of the comparator changes from “H” to “L”. Set the gate output signal to “H”. That is, for example, assuming that the analog input voltage Vin is higher than or equal to the comparison voltage of the comparator Cn _-1 and lower than or equal to the comparison voltage of the comparator Cn,
The output signal of the comparator Cn- ₁ becomes "H" and the output signal of the comparator Cn becomes "L". When the output signal “H” of the comparator Cn ₋₁ and the output signal “L” of the comparator Cn are input to the input terminal of the AND gate An, the output signal of the AND gate An becomes “H”. Then, "1" of the 6-bit conversion data to be output
The gate terminal of the NFET whose drain terminal is connected to the bit line corresponding to the bit to be set becomes "H". Then, the NFET turns on and only the bit line connected to the source terminal of the NFET becomes "L", and the predetermined bit of the converted data that is inverted and output by the inverter is "H".
It becomes.

Next, A / in the folded portion between the resistor r33 and the resistor r34
The D conversion will be described in detail with a specific example.

For example, when the value of the input voltage Vin is Vin≈Vref / 2, the output signals of the comparators C1 to C33 are “H” and the outputs of the comparators C34 to C63 are normal if there is no folding error and normal. The signal becomes "L". Therefore, the output signal of only the AND gate A34 becomes "H", and the NFET 30 and NFET 31 are turned on. Then, among the bit lines 21 to 26 precharged to "H", the bit line 22 and the bit line 26 change to "L", and the other bit lines remain "H". The signals on the bit lines 21 to 26 are inverted by the inverters I1 to I6, respectively, and the 6-bit conversion data output is "100010".

However, even though the value of the input voltage Vin is Vin≈Vref / 2, noise or the like is generated due to the layout characteristic near the turnaround portion between the resistors r33 and r34. It is assumed that the output signals of C32 and the comparator C34 become "H", and the output signals of the comparator C33 and the comparators C35 to C63 become "L". Then, the output signals of the two AND gates of AND gate A33 and AND gate A35 become "H", and NFET28 and NFET29 and NFET32, NFET3
3 and NFET 34 turn on. Then, of the bit lines 21 to 26 that are precharged to “H”, the bit line
21, the signals of the bit line 22 and the bit line 26 change to "L", and the output 6-bit conversion data becomes "100011". Therefore, in this case, the correct conversion data “10001
The conversion error with 0 "is 1, and only the LSB (least significant bit) is affected.
And the resistance rk + ₁ , the comparators C1 to Ck
_-1 and the output signal of comparator Ck ₊₁ becomes "H", and comparator Ck
And the case where the output signals of the comparator Ck + ₂ to the comparator C63 are "L" is called malfunction pattern 1.

Further, for example, it is assumed that the output signals of the comparators C1 to C31 and the comparator C33 become “H”, and the output signals of the comparator C32 and the comparators C34 to C63 become “L”. In that case, the output signals of the two AND gates of the AND gate A32 and the AND gate A34 become "H", the signals of the bit line 22 and the bit line 26 change to "L", and the output 6-bit The conversion data will be "100010". Therefore, the conversion data has the same value as the correct conversion data “100010” in this case, and no conversion error occurs. Hereafter, in this way, the folded part has resistance rk and resistance
When it is between rk + ₁ , the output signals of the comparator C1 to the comparator Ck _-2 and the comparator Ck become "H", and the output signals of the comparator Ck _-1 and the comparator Ck + ₁ to the comparator C63 become When it becomes "L", it is called malfunction pattern 2.

Further, for example, it is assumed that the output signals of the comparators C1 to C33 and the comparator C35 are “H”, and the output signals of the comparator C34 and the comparators C36 to C63 are “L”. In that case, the 6-bit conversion data output in the same manner as described above is "100110". Therefore, the conversion error with the correct conversion data "100010" in this case is 4.
Hereinafter, when the folded portion is between the resistance rk and the resistance rk + ₁ in this way, the comparator C1 to the comparator Ck and the comparator Ck are used.
+ ₂ of the output signal becomes "H", say comparator Ck + ₁ and comparator Ck + _{3 ~} comparator malfunction pattern 3 if the output signal becomes "L" of the C63.

Table 1 shows malfunction patterns 1, malfunction patterns 2 and malfunction patterns 3 in the A / D converter according to the present invention.
The conversion error in case of and the malfunction pattern 1,
The conversion error in the case of the malfunction pattern 2 and the malfunction pattern 3 is shown. From this table, it can be seen that the A / D converter of this embodiment has a very small conversion error in any malfunction pattern.

As described above, in the present embodiment, when the A / D conversion device is formed into an LSI, the lower 2 bits are from “11” to “00” (in the present embodiment, so that the arrangement of each digital conversion circuit is most efficient). , "011111" to "100000"), the ladder resistance is not folded at the place where the lower 2 bits are "01" to "10"("100001" to "100010" in this embodiment). I'm trying to turn back.

By doing so, even if the output signals of the two AND gates become "H" in each malfunction pattern as described above, the respective 6-bit signals based on the output signals of the two AND gates that become "H" Since all the digital data differ only in the lower bits, the 6-bit converted data that is output by superposing the two digital data does not have a value that is far from the converted data in the normal case. Therefore, in the A / D conversion device of the present invention, the arrangement of each digital conversion circuit is slightly disadvantageous, but the conversion error is greatly advantageous.

The effect of the present invention is achieved by folding the ladder resistance at a position other than the position of the digital conversion circuit in which the lower 2 bits of the conversion data change from "11" to "00".
Therefore, in the above embodiment, the lower 2 bits are "0".
The portion from 1 "to" 10 "is the turning point of the ladder resistance, but the present invention is not limited to this. That is, the lower 2 bits are from" 00 "to" 01 "or the lower 2 It may be folded back at the place where the bit changes from “10” to “11.” Table 1 shows the conversion errors in the case of malfunction pattern 1, malfunction pattern 2 and malfunction pattern 3 in the second and third embodiments. From this table, it can be seen that the conversion error is much smaller than that of the conventional example in any of the embodiments.

Further, in the above-described embodiment, the folding is performed after the location of the digital conversion circuit that sets 1 to MSB, but it may be folded before the location of the digital conversion circuit that sets 1 to MSB. Needless to say.

<Effects of the Invention> As is clear from the above, the A / D conversion device of the present invention is
A digital signal obtained by converting only one folding portion provided in the ladder resistor for dividing the reference voltage and setting it in stages by comparing the analog input voltage with the comparison voltage by a plurality of comparators. AND gate that outputs a signal for setting the lower 2 bits of "11", and an AND gate that is adjacent to the AND gate and that outputs a signal for setting the lower 2 bits of the converted digital signal to "00" Since it is provided at a position other than the position corresponding to between and, even if a folding error occurs due to noise or the like at the folding portion of the ladder resistor, the digital signal converted and output is largely the same as the digital signal when correctly converted. The values do not become distant from each other, and a large conversion error does not occur.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an A / D converter according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional A / D converter. 21,22,23,24,25,26 …… bit line, 27,28,29,30,31,32,3
3,34 …… NFET, r1-r64 …… resistor, C1-C63 …… comparator, A1-A63 …… AND gate, I1-I6 …… inverter.

Claims (1)

[Claims] 1. A plurality of comparators for dividing a reference voltage by a ladder resistor having only one folded portion and sequentially comparing a comparison voltage set in steps with an analog input voltage, and among two or more adjacent comparators. The output signal of the comparator corresponding to the highest voltage division is "L" and the output signals of other comparators are "H".
In the case of, a pre-charged bit line is provided with an AND gate for switching a switching element connected to a predetermined bit line and outputting a signal for inverting the output signal of the predetermined bit line. , In a parallel comparison type A / D converter that converts an analog input signal to a digital signal, an AND gate that outputs a signal for setting the lower 2 bits of the converted digital signal to "11" and adjacent to this AND gate However, the folded portion of the ladder resistor is provided at a position other than a position corresponding to an AND gate that outputs a signal for setting the lower 2 bits of the converted digital signal to "00". A / D conversion device.