JPH0563935B2 - - Google Patents
Info
- Publication number
- JPH0563935B2 JPH0563935B2 JP58065055A JP6505583A JPH0563935B2 JP H0563935 B2 JPH0563935 B2 JP H0563935B2 JP 58065055 A JP58065055 A JP 58065055A JP 6505583 A JP6505583 A JP 6505583A JP H0563935 B2 JPH0563935 B2 JP H0563935B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- insulating film
- mask
- etching mask
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005530 etching Methods 0.000 claims description 55
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 description 36
- 239000011229 interlayer Substances 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法、詳しくは電
極接触用のコンタクトホール形成方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact hole for contacting an electrode.
従来例の構成とその問題点
従来、半導体装置上の絶縁膜に対するコンタク
トホール形成においては、加工寸法の微細化等に
より、近年平行平板型のドライエツチング装置を
用いてサイドエツチのない異方性エツチングが実
用化している。Conventional Structures and Problems Conventionally, in forming contact holes in insulating films on semiconductor devices, due to miniaturization of processing dimensions, anisotropic etching without side etching using a parallel plate type dry etching system has recently become possible. It has been put into practical use.
しかしコンタクトホールの異方性エツチングに
おいてはエツチングマスクとして用いられるホト
レジストマスクの下地被エツチング膜に対する十
分なエツチング選択性が得にくくホトレジストマ
スクのガスプラズマによるダメージが大きく、下
地層間絶縁膜の耐圧低下の原因となつている。ま
た、異方性エツチングによつて成形されたコンタ
クトホールはそのホールエツジが急峻でアルミ配
線の断線を生じやすい問題があつた。 However, in anisotropic etching of contact holes, it is difficult to obtain sufficient etching selectivity for the underlying etching film of the photoresist mask used as an etching mask, which causes significant damage to the photoresist mask due to gas plasma, which causes a drop in breakdown voltage of the underlying interlayer insulating film. It is becoming. Further, the contact hole formed by anisotropic etching has a steep hole edge, which causes a problem in that the aluminum wiring is easily disconnected.
第1図は従来の異方性エツチング法により、コ
ンタクトホールを形成したものの断面図であり、
図中、1はシリコン基板、2はゲート用酸化シリ
コン膜、3はゲート電極であるポリシリコン膜、
4は配線用アルミニウミ膜、5は層間絶縁膜とし
てのCVD酸化シリコン膜、6はコンタクトホー
ルである。ここでコンタクトホール6のパターン
寸法が微細化し、さらに層間絶縁膜5の膜厚が厚
くなると、必然的に深いコンタクトホールを形成
しなけれならず、その結果、ホールエツジでのア
ルミ配線の断線が生じやすい。 Figure 1 is a cross-sectional view of a contact hole formed using a conventional anisotropic etching method.
In the figure, 1 is a silicon substrate, 2 is a silicon oxide film for a gate, 3 is a polysilicon film which is a gate electrode,
4 is an aluminum film for wiring, 5 is a CVD silicon oxide film as an interlayer insulating film, and 6 is a contact hole. As the pattern size of the contact hole 6 becomes finer and the thickness of the interlayer insulating film 5 becomes thicker, a deep contact hole must be formed, and as a result, the aluminum wiring is likely to break at the edge of the hole. .
発明の目的
本発明は、上記の問題点の解決を図つたもので
あり、絶縁膜に対してエツチング選択性の高い第
1のエツチングマスクを使用することにより層間
絶縁膜の耐圧低下のないパターン寸法精度の高い
コンタクトホール形成を行うことができ、さらに
ホトレジストによる第2のエツチングマスクを用
いて、レジストと絶縁膜とのエツチング選択性を
制御することによりテーパーエツチングを行うこ
とのできる半導体装置の製造方法を提供すること
を目的とするものである。Purpose of the Invention The present invention aims to solve the above-mentioned problems, and by using a first etching mask that has high etching selectivity with respect to the insulating film, pattern dimensions can be achieved without reducing the withstand voltage of the interlayer insulating film. A method for manufacturing a semiconductor device that can form contact holes with high precision and further perform taper etching by controlling the etching selectivity between the resist and the insulating film using a second etching mask made of photoresist. The purpose is to provide the following.
発明の構成
本発明は絶縁膜上に第1のエツチングマスク材
料である多結晶シリコン膜あるいはアルミニウム
膜を形成する。これらの膜はエツチング選択性が
ホトレジストマスクに比べて非常に高いためうす
い膜厚で形成でき、かつ異方性エツチングにより
高いパターン寸法精度を有する第1のエツチング
マスクを形成する。次いで、ホトレジストマスク
を用いて第1のエツチングマスクパターン寸法よ
りも小さなコンタクト窓を有する第2のエツチン
グマスクの形成を行う。この後、第1、第2のエ
ツチングマスクをマスクとして、レジストと絶縁
膜とのドライエツチング選択性を低下させる目的
で、フツ素ガスに酸素ガスを添加したガスプラズ
マによるドライエツチングを行い、テーパを有す
る絶縁膜の開口を形成する。Structure of the Invention In the present invention, a polycrystalline silicon film or an aluminum film, which is a first etching mask material, is formed on an insulating film. These films have extremely high etching selectivity compared to a photoresist mask, so they can be formed with a thin film thickness, and the first etching mask having high pattern dimensional accuracy is formed by anisotropic etching. A second etching mask having contact windows smaller than the first etching mask pattern size is then formed using a photoresist mask. After that, using the first and second etching masks as masks, dry etching was performed using gas plasma in which oxygen gas was added to fluorine gas in order to reduce the dry etching selectivity between the resist and the insulating film. An opening in the insulating film is formed.
実施例の説明
本発明の実施例をシリコン基板へコンタクトホ
ールを形成する場合を例にして以下に説明する。
まず第2図aに示すように半導体基板11上の層
間絶縁膜12の表面に第1のエツチングマスクと
なる多結晶シリコン13を2000から5000Å程度を
減圧CVD法により形成する。次に、ホトレジス
ト膜膜14を用いて多結晶シリコン13の異方性
エツチングを行い、多結晶シリコン13による第
1のエツチングマスクマスク形成を行う(同図
b)。さらに、ホトレジスト膜を用い第1のエツ
チングマスク13よりも小さなコンタクト窓を有
する第2のエツチングマスク15をホトリソグラ
フイー工程により形成する(同図c)。このよう
な2層のエツチングマスク13,15を有するパ
ターンに対し、レジストエツチングマスク15の
エツチングを早め、絶縁膜とのエツチング選択性
を低下させる目的で、フツ素ガスによるプラズマ
に酸素ガスを添加したプラズマを用いてエツチン
グを行う。この時、エツチングマスク15は縦方
向のみでなく横方向にもエツチングが進行し、レ
ジストパターンエツジが後退する。このレジスト
パターンエツジの後退を利用することで、絶縁膜
のエツチング形状はテーパ状となる(同図d)。DESCRIPTION OF EMBODIMENTS Embodiments of the present invention will be described below, taking as an example a case where a contact hole is formed in a silicon substrate.
First, as shown in FIG. 2a, polycrystalline silicon 13, which will serve as a first etching mask, is formed to a thickness of about 2000 to 5000 Å on the surface of interlayer insulating film 12 on semiconductor substrate 11 by low pressure CVD. Next, the polycrystalline silicon 13 is anisotropically etched using the photoresist film 14 to form a first etching mask using the polycrystalline silicon 13 (FIG. 3(b)). Furthermore, a second etching mask 15 having a contact window smaller than that of the first etching mask 13 is formed using a photoresist film by a photolithography process (FIG. 3(c)). For such a pattern having two layers of etching masks 13 and 15, oxygen gas was added to the fluorine gas plasma in order to accelerate the etching of the resist etching mask 15 and reduce the etching selectivity with respect to the insulating film. Etching is performed using plasma. At this time, the etching mask 15 is etched not only in the vertical direction but also in the horizontal direction, and the resist pattern edge recedes. By utilizing this receding of the resist pattern edge, the etched shape of the insulating film becomes tapered (see d in the figure).
本実施例では、レジストと絶縁膜とのエツチン
グレート比、すなわち、エツチング選択性が略
1.5対1になるように酸素ガスの添加量を制御し、
コンタクトホールのテーパー角度約70度を得た。
本発明によると、絶縁膜のドライエツチング時に
レジストエツチングマスク15がもし消失した場
合でも、エツチングマスク13が存在し、絶縁膜
のエツチングは進行せず、ピンホール等による層
間絶縁膜の耐圧低下は生じない。次に、第1、第
2のエツチングマスク13,15を除去し、テー
パーを有するコンタクトホール16が得られる
(同図e)。そして、この上に電極のアルミニウム
膜17を形成する(同図f)。 In this example, the etching rate ratio between the resist and the insulating film, that is, the etching selectivity was approximately
Control the amount of oxygen gas added so that the ratio is 1.5:1,
The taper angle of the contact hole was approximately 70 degrees.
According to the present invention, even if the resist etching mask 15 disappears during dry etching of the insulating film, the etching mask 13 exists, and the etching of the insulating film does not proceed, and the breakdown voltage of the interlayer insulating film does not decrease due to pinholes etc. do not have. Next, the first and second etching masks 13 and 15 are removed to obtain a tapered contact hole 16 (see e in the figure). Then, an aluminum film 17 as an electrode is formed on this (FIG. 5f).
発明の効果
本発明の方法によれば、第1のエツチングマス
クは高いエツチング選択性を有するためその膜厚
を薄くすることができ、ホトレジスト膜により微
細なエツチングパターン形成が可能である。また
エツチングマスクが2層構造であるためエツチン
グによる層間絶縁膜への影響を少なくできる。さ
らに、第2のエツチングマスクを用いて、レジス
トと絶縁膜のエツチング選択性を制御すること
で、コンタクトホールのテーパーの角度を独立に
コントロールすることができる。また第2のエツ
チングマスク下には第1のエツチングマスクが形
成されており、第2のエツチングマスクであるホ
トレジスト膜厚を薄くできるため非常に微細なコ
ンタクトの窓のパターニングをホトリソグラフイ
ー工程により容易に行うことができ、層間絶縁膜
のドライエツチングによる耐圧低下及びアルミ配
線の断線、パターン加工寸法精度の向上など半導
体装置の品質を著しく高める効果がある。Effects of the Invention According to the method of the present invention, since the first etching mask has high etching selectivity, its film thickness can be reduced, and a fine etching pattern can be formed using a photoresist film. Furthermore, since the etching mask has a two-layer structure, the influence of etching on the interlayer insulating film can be reduced. Furthermore, by controlling the etching selectivity of the resist and insulating film using the second etching mask, the taper angle of the contact hole can be independently controlled. Furthermore, since the first etching mask is formed under the second etching mask, the thickness of the photoresist film that is the second etching mask can be made thinner, making it easier to pattern very fine contact windows using the photolithography process. This has the effect of significantly improving the quality of semiconductor devices, such as reducing breakdown voltage due to dry etching of interlayer insulating films and breaking aluminum wiring, and improving pattern processing dimensional accuracy.
第1図は従来のコンタクトホール形成方法につ
いて説明するための断面図、第2図a〜fは本発
明の半導体装置の製造方法を示す工程断面図であ
る。
11……半導体基板、12……層間絶縁膜、1
3……第1のエツチングマスク、15……第2の
エツチングマスク、17……アルミニウム膜。
FIG. 1 is a sectional view for explaining a conventional contact hole forming method, and FIGS. 2 a to 2 f are process sectional views showing a method for manufacturing a semiconductor device according to the present invention. 11...Semiconductor substrate, 12...Interlayer insulating film, 1
3...first etching mask, 15...second etching mask, 17...aluminum film.
Claims (1)
クトホール形成用の、ホトレジスト膜よりも高い
エツチング選択性を有する第1のエツチングマス
クを形成する工程、前記第1のエツチングマスク
よりも小さなコンタクトホール形成用窓をあけた
ホトレジスト膜による第2のエツチングマスクを
形成する工程、前記第2のエツチングマスクの窓
に横方向エツチを行いながら、前記絶縁膜をドラ
イエツチングする工程を有することを特徴とする
半導体装置の製造方法。 2 第1のエツチングマスクが多結晶シリコン膜
であることを特徴とする特許請求の範囲第1項に
記載の半導体装置の製造方法。[Claims] 1. A step of forming an insulating film on a semiconductor substrate, and then forming a first etching mask having higher etching selectivity than a photoresist film for forming a contact hole, the first etching a step of forming a second etching mask of a photoresist film with a window for forming a contact hole smaller than the mask; and a step of dry etching the insulating film while performing lateral etching on the window of the second etching mask. A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first etching mask is a polycrystalline silicon film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6505583A JPS59189626A (en) | 1983-04-13 | 1983-04-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6505583A JPS59189626A (en) | 1983-04-13 | 1983-04-13 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59189626A JPS59189626A (en) | 1984-10-27 |
JPH0563935B2 true JPH0563935B2 (en) | 1993-09-13 |
Family
ID=13275880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6505583A Granted JPS59189626A (en) | 1983-04-13 | 1983-04-13 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59189626A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5240978A (en) * | 1975-09-27 | 1977-03-30 | Fujitsu Ltd | Process for production of semiconductor device |
JPS5760851A (en) * | 1980-09-17 | 1982-04-13 | Hitachi Ltd | Dielectric isolation of semiconductor integrated circuit |
-
1983
- 1983-04-13 JP JP6505583A patent/JPS59189626A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5240978A (en) * | 1975-09-27 | 1977-03-30 | Fujitsu Ltd | Process for production of semiconductor device |
JPS5760851A (en) * | 1980-09-17 | 1982-04-13 | Hitachi Ltd | Dielectric isolation of semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS59189626A (en) | 1984-10-27 |
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