JPS59189626A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59189626A
JPS59189626A JP6505583A JP6505583A JPS59189626A JP S59189626 A JPS59189626 A JP S59189626A JP 6505583 A JP6505583 A JP 6505583A JP 6505583 A JP6505583 A JP 6505583A JP S59189626 A JPS59189626 A JP S59189626A
Authority
JP
Japan
Prior art keywords
etching
etching mask
insulating film
film
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6505583A
Other languages
Japanese (ja)
Other versions
JPH0563935B2 (en
Inventor
Takashi Tsukura
津倉 敬
Toru Okuma
徹 大熊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP6505583A priority Critical patent/JPS59189626A/en
Publication of JPS59189626A publication Critical patent/JPS59189626A/en
Publication of JPH0563935B2 publication Critical patent/JPH0563935B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a contact hole which does not allow the dielectric strength of interlayer insulating film and has a high pattern size accuracy for tapered etching by using a first etching mask having a high etching characteristic and a second photo etching mask by the photo resist for an insulating film. CONSTITUTION:A polycrystalline silicon 13 which becomes a first etching mask is formed at the surface of interlayer insulating film 12 on semiconductor substrate 11. The anisotropic etching is carried out to the polycrystalline silicon 13 using a photo resist film 14 and a first etching mask is formed by the polycrystalline silicon 13. Thereafter, a second etching mask 15 having a contact window which is smaller than that of the first etching mask 13 is formed using the photo resist film. The tapered etching is carried out to such a pattern having the etching masks 13, 15 in such a double-layer structure using the plasma obtained by adding oxygen gas to the fluorine gas plasma. Thereafter, the first and the second etching masks 13, 15 are removed and a tapered contact hole 16 can be obtained. An electrode of aluminium film 17 is formed on such hole.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法、詳しくは電極接触用
のコンタクトホール形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact hole for contacting an electrode.

従来例の構成とその問題点 従来−半導体装置上の絶縁膜に対するコンタクトホール
形成においては、加工寸法の微細化等により、近年平行
平板型のドライエツチング装置゛を用いてサイドエッチ
のない異方性エツチングが実用化している。
Conventional configurations and their problems Conventional - Due to the miniaturization of processing dimensions in the formation of contact holes in insulating films on semiconductor devices, in recent years parallel plate type dry etching equipment has been used to achieve anisotropic etching without side etching. Etching is now in practical use.

しかしコンタクトホールの異方性エツチングにおいては
エツチングマスクとして用いられるホトレジストマスク
の下地被エツチング膜に対する十分なエツチング選択性
が得にくくホトレジストマスクのガスプラズマによるダ
メージが大きく、下地層間絶縁膜の耐圧低下の原因とな
っている。また、異方性エツチングによって形成された
コンタクトホールはそのホールエツジが急峻でアルミ配
線の断線を生じやすい問題があった。
However, in anisotropic etching of contact holes, it is difficult to obtain sufficient etching selectivity for the underlying etching film of the photoresist mask used as an etching mask, which causes significant damage to the photoresist mask due to gas plasma, which causes a drop in breakdown voltage of the underlying interlayer insulating film. It becomes. Further, the contact hole formed by anisotropic etching has a steep hole edge, which causes a problem in that the aluminum wiring is easily disconnected.

第1図は従来の異方性エツチング法によシ、コンタクト
ホールを形成したものの断面図であシ、図中、1はシリ
コン基板、2はゲート用酸化シリコン膜、3はゲート電
極であるポリソリコン膜、4は配線用アルミニウム膜、
5は層間絶縁膜としてのCVD酸化シリコン膜、6はコ
ンタクトホールである。ここでコンタクトホール6のパ
ターン寸法が微細化し、さらに層間絶縁膜5の膜厚が厚
くなると、必然的に深いコンタクトホールを形成しなけ
ればならず、その結果、ホールエツジでのアルミ配線の
断線が生じやすい。
Figure 1 is a cross-sectional view of a contact hole formed using a conventional anisotropic etching method. film, 4 is an aluminum film for wiring,
5 is a CVD silicon oxide film as an interlayer insulating film, and 6 is a contact hole. As the pattern size of the contact hole 6 becomes finer and the thickness of the interlayer insulating film 5 becomes thicker, it is necessary to form a deep contact hole, which results in disconnection of the aluminum wiring at the edge of the hole. Cheap.

発明の目的 本発明は、上記の問題点の解決を図ったものであり、絶
縁膜に対してエツチング選択性の高い第1のエツチング
マスクを使用することにより層間絶縁膜の耐圧低下のな
いパターン寸法精度の高いコンタクトホール形成を行う
ことができ、さらにホトレジストによる第2のエツチン
グマスクを用いることによりテーパーエツチングを行う
ことのできる半導体装置の製造方法を提供することを目
的とするものである。
Purpose of the Invention The present invention is an attempt to solve the above-mentioned problems.By using a first etching mask that has high etching selectivity with respect to the insulating film, the pattern size can be improved without reducing the withstand voltage of the interlayer insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form contact holes with high precision and can also perform taper etching by using a second etching mask made of photoresist.

発明の構成 本発明は絶縁膜上に第1のエツチングマスク材料である
多結晶シリコン膜あるいはアルミニウム膜を形成する。
Structure of the Invention In the present invention, a polycrystalline silicon film or an aluminum film, which is a first etching mask material, is formed on an insulating film.

これらの膜はエツチング選択性がホトレジストマスクに
比べて非常に高いためうすい膜厚で形成でき、かつ異方
性エツチングにより高いパターン寸法精度を有する第1
のエツチングマスクを形成する。次いで、ホトレジスト
マスクを用いて第1のエツチングマスクパターン寸法よ
りも小さなコンタクト窓を有する第2のエツチングマス
クの形成を行う。この後、第1.第2のエツチングマス
クをマスクとして、絶縁膜を酸素ガスを添加したガスプ
ラズマによるドライエツチングを行い、テーパを有する
絶縁膜の開口を形成する。
These films have extremely high etching selectivity compared to photoresist masks, so they can be formed with a thin film thickness, and they also have high pattern dimensional accuracy due to anisotropic etching.
Form an etching mask. A second etching mask having contact windows smaller than the first etching mask pattern size is then formed using a photoresist mask. After this, the first. Using the second etching mask as a mask, the insulating film is dry etched using gas plasma containing oxygen gas to form a tapered opening in the insulating film.

実施例の説明 本発明の実施例をシリコン基板へコンタクトボールを形
成する場合を例にして以下に説明する。
DESCRIPTION OF EMBODIMENTS Embodiments of the present invention will be described below, taking as an example a case where a contact ball is formed on a silicon substrate.

まず第2図(−)に示すように半導体基板11上の層間
絶縁膜12の表面に第1のエツチングマスクとなる多結
晶シリコン13を20oOから5000A程歴を減圧C
VD法により形成する。次に、ホトレ     □シス
ト膜14を用いて多結晶シリコン13の異方性エツチン
グを行い、多結晶シリコン13による第1のエツチング
マスク形成を行う(同図b)。
First, as shown in FIG. 2(-), polycrystalline silicon 13, which will serve as a first etching mask, is etched on the surface of the interlayer insulating film 12 on the semiconductor substrate 11 at a reduced pressure of 200 to 5000 A.
Formed by VD method. Next, the polycrystalline silicon 13 is anisotropically etched using the photoresist film 14 to form a first etching mask using the polycrystalline silicon 13 (FIG. 3(b)).

さらに、ホトレジスト膜を用い第1のエツチングマスク
13よシも小さなコンタクト窓を有する第2のエツチン
グマスク1ぢをホトリソグラフィ一工程により形成する
(同図C)。このような2層のエツチングマスク13.
15を有するパターンをフッ素ガスによるプラズマに酸
素ガスを添加したプラズマを用いテーパーエツチングを
行う。このエツチングにより第2のエツチングマスク1
5がプラズマによりエッチされテーパを有するコンタク
トホールの形成ができる(同図d)。次に、第1.第2
のエツチングマスク13.15を除去し、テーパーを有
するコンタクトホール16が得られる(同図e)。そし
て、この上に電極のアルミニウム膜17を形成する(同
図f)。
Furthermore, a second etching mask 1d having a contact window smaller than that of the first etching mask 13 is formed using a photoresist film by a single photolithography step (FIG. 3C). Such a two-layer etching mask 13.
Taper etching is performed to form a pattern having the pattern No. 15 using a fluorine gas plasma to which oxygen gas is added. This etching creates the second etching mask 1.
5 is etched by plasma to form a tapered contact hole (d in the same figure). Next, the first. Second
The etching masks 13 and 15 are removed to obtain a tapered contact hole 16 (see e in the figure). Then, an aluminum film 17 as an electrode is formed on this (FIG. 5f).

発明の効果 本発明の方法によれば、第1のエツチングマスクは高い
エツチング選択性を有するためその膜厚を薄くすること
ができ、ホトレジスト膜により微細なエツチングパター
ン形成が可能である。寸だエツチングマスクが2層構造
であるためエツチングによる層間絶縁膜への影響を少な
くできる。さらに第2のエツチングマスクを用いてコン
タクトホールのテーパーの角度を独立にコントロールす
ることができる。また第2のエツチングマスク下には第
1のエツチングマスクが形成されており、第2のエツチ
ングマスクであるホトレジスト膜厚を薄くできるため非
常に微細なコンタクト窓のパターニングをホトリソグラ
フィ一工程により容易に行うことができ、層間絶縁膜の
ドライエツチングによる耐圧低下及びアルミ配線の@線
、パターン加工寸法精度の向上など半導体装置の品質を
著しく高める効果がある。
Effects of the Invention According to the method of the present invention, since the first etching mask has high etching selectivity, its film thickness can be reduced, and a fine etching pattern can be formed using a photoresist film. Since the etching mask has a two-layer structure, the influence of etching on the interlayer insulating film can be reduced. Furthermore, the taper angle of the contact hole can be independently controlled using the second etching mask. Furthermore, since the first etching mask is formed under the second etching mask, the thickness of the photoresist film that is the second etching mask can be made thinner, making it easier to pattern extremely fine contact windows using a single photolithography process. This method has the effect of significantly improving the quality of semiconductor devices, such as reducing breakdown voltage due to dry etching of interlayer insulating films, improving @ lines of aluminum wiring, and improving dimensional accuracy of pattern processing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のコンタクトホール形成方法について説明
するだめの断面図、第2図(a)〜(f)は本発明の半
導体装置の製造方法を示す工程断面図である。 11・・・半導体基板、12・・・・・・層間絶縁膜、
13.、、、、 第1のエツチングマスク、15・・・
・・第2のエツチングマスク、1了・・・・・アルミニ
ウム膜。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 5 第2図 第2図
FIG. 1 is a sectional view for explaining a conventional contact hole forming method, and FIGS. 2(a) to 2(f) are process sectional views showing a method for manufacturing a semiconductor device according to the present invention. 11... Semiconductor substrate, 12... Interlayer insulating film,
13. ,,, First etching mask, 15...
...Second etching mask, 1 completion...Aluminum film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 5 Figure 2 Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)  半導体基板表面上に絶縁膜を形成し、次に前
記絶縁膜に対して、高いエツチング選択性を有するコン
タクトホール形成用の第1のエツチングマスクを形成す
る工程、前記第1のエツチングマスク クよシも小さなコンタクトホール形成用窓を開けだホト
レジスト膜による第2のエツチングマスクを形成する工
程、前記第1.第2のエツチングマスクをマスクとして
前記絶縁膜をドライエツチングする工程を有することを
特徴とする半導体装置の製造方法。
(1) A step of forming an insulating film on the surface of a semiconductor substrate, and then forming a first etching mask for forming a contact hole having high etching selectivity with respect to the insulating film, the first etching mask forming a second etching mask using a photoresist film to open a window for forming a small contact hole; A method of manufacturing a semiconductor device, comprising the step of dry etching the insulating film using a second etching mask as a mask.
(2)第1のエツチングマスクが多結晶シリコン膜であ
ることを特徴とする特許請求の範囲第1項に記載の半導
体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the first etching mask is a polycrystalline silicon film.
JP6505583A 1983-04-13 1983-04-13 Manufacture of semiconductor device Granted JPS59189626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6505583A JPS59189626A (en) 1983-04-13 1983-04-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6505583A JPS59189626A (en) 1983-04-13 1983-04-13 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59189626A true JPS59189626A (en) 1984-10-27
JPH0563935B2 JPH0563935B2 (en) 1993-09-13

Family

ID=13275880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6505583A Granted JPS59189626A (en) 1983-04-13 1983-04-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59189626A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240978A (en) * 1975-09-27 1977-03-30 Fujitsu Ltd Process for production of semiconductor device
JPS5760851A (en) * 1980-09-17 1982-04-13 Hitachi Ltd Dielectric isolation of semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240978A (en) * 1975-09-27 1977-03-30 Fujitsu Ltd Process for production of semiconductor device
JPS5760851A (en) * 1980-09-17 1982-04-13 Hitachi Ltd Dielectric isolation of semiconductor integrated circuit

Also Published As

Publication number Publication date
JPH0563935B2 (en) 1993-09-13

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