JP3532352B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an interlayer insulating film on a semiconductor device having a step.

[0002]

2. Description of the Related Art In a DRAM which requires the finest processing in a semiconductor device which is highly integrated, a stack type cell is adopted to obtain a sufficient storage capacity. A step is created between the circuit and the circuit.

FIG. 24 shows a D having a conventional stack type cell.
It is sectional drawing which shows RAM. As shown in FIG. 24A, the memory cell portion on the silicon substrate 1 is provided with the stack capacitors 2 and 3, and a step is generated at the boundary portion between the memory cell portion and the peripheral circuit portion. Therefore, when the interlayer insulating film 4 is formed on this, a step 4a is also generated in the interlayer insulating film 4. Further, when a resist 5 for forming a contact is applied on the interlayer insulating film 4, the step 4 is formed.
Due to the presence of a, the resist 5 has different film thicknesses in the memory cell portion and the peripheral circuit portion.

Thereafter, as shown in FIG. 24B, when a resist 5 pattern for contact is formed, the required exposure conditions are different between the resist patterns 5a and 5b because the resist 5 has a different film thickness. I will end up. Therefore,
It is very difficult to form the fine resist patterns 5a and 5b at the same time.

FIG. 25 is a sectional view showing a portion of a DRAM having a conventional stack type cell, which is orthogonal to FIG. As shown in FIG. 25A, as in FIG. 24A, the memory cell portion on the silicon substrate 1 is provided with the stack capacitors 2 and 3, and the boundary between the memory cell portion and the peripheral circuit portion is provided. There is a step in the part. Therefore, the steps 4a and 6a are also formed on the interlayer insulating film 4 and the aluminum wiring 6 formed thereon.
When a resist 7 for patterning the aluminum wiring 6 is applied thereon, the film thickness of the resist 7 is formed differently in the memory cell portion and the peripheral circuit portion due to the steps 4a and 6a.

Next, as shown in FIG. 25B, when the aluminum wiring 6 is etched, the aluminum wiring 6 may disappear depending on the etching conditions because the resist 7 film thickness of the memory cell portion is thin. .

[0007]

The conventional DRAM having the stack type capacitor is as described above, and since the memory cell part has the stack type capacitor, it is formed higher than the peripheral circuit part. Therefore, as shown in FIGS. 24 and 25, when the interlayer insulating film 4 is formed on the entire surface thereof, a step 4a is generated in the interlayer insulating film 4, and the film thickness of the resist 5 varies in the opening of the contact hole. Due to this, opening defects are likely to occur, and in forming the wiring, disconnection is likely to occur in the step 4a portion of the interlayer insulating film 4,
There is a problem that a good device cannot be manufactured.

The present invention has been made in order to solve the above-mentioned problems, and reduces the step in the interlayer insulating film, reduces the variation in the resist film thickness on the interlayer insulating film, and improves the subsequent process. An object of the present invention is to provide a method for manufacturing a semiconductor device, which can obtain a highly reliable device that can be performed.

[0009]

A method of manufacturing a semiconductor device according to claim 1 of the present invention comprises a step of forming an interlayer insulating film containing B or P on a semiconductor substrate having a step, and the above B or P. the B or P in the interlayer insulating film surface containing the
A step of forming a low-concentration impurity layer made of an insulating film containing a much lower concentration of B or P, a step of forming an etching mask for covering a lower step portion on the low-concentration impurity layer, and the etching mask previously for step higher region of the interlayer insulating film and the low-concentration impurity layer containing the B or P using
Note that the side etching amount was reduced due to the formation of the low-concentration impurity layer.
And a step of performing increased isotropic etching.

[0010] The method of manufacturing a semiconductor device according to claim 2 of the present invention comprises steps of forming an interlayer insulating film containing B or P on the semiconductor substrate, the surface of the interlayer insulating film containing the B or P Contains a lower concentration of B or P than B or P
A step of forming a low-concentration impurity layer formed of an insulating film, a step of forming an etching mask on the low-concentration impurity layer that covers a region to be a step lower portion in a later step, and using the etching mask. the previously given the thickness of only to the B or interlayer insulating film and the low-concentration impurity layer containing P with the formation of the low concentration impurity layer Sai Doetchin
And a step of performing isotropic etching with an increased amount of etching.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming an interlayer insulating film containing B or P after forming a transistor, and a step of forming an interlayer insulating film containing B or P on the surface of the interlayer insulating film. B or P having a lower concentration than the above B or P
Forming a low concentration impurity layer made of an insulating film containing said low density and forming a storage node contact forming resist the impurity layer, a mask the storage node contact forming resist the B or P the interlayer insulating film and the low-concentration impurity layer containing, after in advance before the region for forming the capacitor
Note that the side etching amount was reduced due to the formation of the low-concentration impurity layer.
The method further includes the step of performing the increased isotropic etching and the step of forming the capacitor after removing the storage node contact forming resist.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a silicon oxide film is formed below an interlayer insulating film containing B or P.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a nitride film is formed between an interlayer insulating film containing B or P and a silicon oxide film.

In the method of manufacturing a semiconductor device according to a sixth aspect of the present invention, the low-concentration impurity layer is formed by subjecting the interlayer insulating film containing B or P to ammonia-hydrogen peroxide treatment.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 to 7 are process sectional views showing a method of manufacturing a DRAM of the present invention. The description will be sequentially made with reference to the drawings.

First, as shown in FIG. 1, a memory cell portion and a peripheral circuit portion are separated by forming a field oxide film 8 on a silicon substrate 1 which is a semiconductor substrate. After that, the transfer gate electrode portion 10 and the impurity diffusion layer 9
The transistor of the DRAM and the bit line wiring 11 are formed. Further, after forming the interlayer insulating film 12 on the entire surface, a stack type capacitor including the storage node electrode 2 and the cell plate electrode 3 is formed in the memory cell portion. After that, BPTEOS which is the interlayer insulating film 13 is deposited on the entire surface. At this time, the step 13 is formed on the interlayer insulating film 13.
a has occurred.

Next, as shown in FIG. 2, the entire surface of the interlayer insulating film 13 is subjected to an ammonia-hydrogen peroxide treatment by immersing it in an ammonia-hydrogen peroxide mixture to reduce the B / P concentration on the surface of the interlayer insulating film 13, A low concentration impurity layer 14 is formed on the surface of the insulating film 13. FIG. 8 shows the surface concentration distribution of P in the AA ′ portion of the interlayer insulating film 13 at this time. The same applies to B. After that, the resist 15 is applied to the entire surface. Next, as shown in FIG. 3, the memory cell portion is opened by subjecting the resist 15 to photolithography.

Next, as shown in FIG. 4, wet etching which is isotropic etching is performed using the resist 15 as a mask to etch the interlayer insulating film 13. At this time, a low-concentration impurity layer 14 is formed on the surface of the interlayer insulating film 13 by performing a chemical treatment such as ammonia-hydrogen peroxide treatment. As shown in FIG. 9, by forming the low-concentration impurity layer 14, the amount of side etching to the lower portion of the resist 15 is increased by about four times. This means that the step portion of the interlayer insulating film 13 is etched, and the step between the memory cell portion and the peripheral circuit portion can be reduced.

Next, as shown in FIG. 5, after removing the resist 15, a resist pattern for a contact hole is formed (not shown), and a contact hole 16 is formed. At this time, since the step difference of the interlayer insulating film 13 is reduced, the resist film thickness can be formed constant. Therefore, the exposure conditions at the time of forming the contact hole 16 can be made constant without changing, and a fine pattern can be formed with high precision.

Next, as shown in FIG. 6, after forming an aluminum film, photoengraving and etching are carried out,
The aluminum wiring 6 is formed. Also at this time, the interlayer insulating film 13
Since the step difference is reduced, the resist film thickness can be made constant, the exposure conditions at the time of forming the aluminum wiring 6 can be made constant, and a good aluminum wiring 6 pattern can be formed.

FIG. 7 is a sectional view of a portion orthogonal to FIG. As shown in FIG. 7, since the step difference of the interlayer insulating film 13 is reduced, the resist film thickness of the memory cell portion does not become thinner than that of the peripheral circuit portion when the aluminum wiring 6 is etched, and the aluminum wiring 6 is not etched. A part of is not lost.

Embodiment 2. In the first embodiment, the method of reducing the step of the interlayer insulating film after forming the DRAM transistor and the capacitor on the silicon substrate has been described. However, after forming the DRAM transistor on the silicon substrate and before forming the capacitor, the capacitor is previously formed. The step difference may be formed in the interlayer insulating film and the capacitor may be formed to reduce the step difference. 10 to 16 show the DR of the second embodiment.
It is process sectional drawing which shows the manufacturing method of AM, and demonstrates one by one according to a figure.

First, as shown in FIG. 10, the field oxide film 8 is formed on the silicon substrate 1 to separate the memory cell portion and the peripheral circuit portion. After that, the DRA including the transfer gate electrode portion 10 and the impurity diffusion layer 9 is formed.
The M transistor and the bit line wiring 11 are formed. After that, BPTEOS, which is the interlayer insulating film 20, is formed on the entire surface.
To form. The entire surface of the interlayer insulating film 20 is subjected to an ammonia-hydrogen peroxide treatment by immersing it in ammonia-hydrogen peroxide mixture, and as shown in FIG. The low concentration impurity layer 14 is formed.

Next, as shown in FIG.
Is applied to the entire surface and the resist 15 is subjected to photoengraving to open the memory cell portion.

Next, as shown in FIG.
Is used as a mask to perform wet etching to etch the interlayer insulating film 20. This is to etch in advance the film thickness increase caused by forming the stack type capacitor in the memory cell portion. At this time, since the low-concentration impurity layer 14 is formed on the surface of the interlayer insulating film 20 by performing the ammonia-hydrogen peroxide treatment, side etching to the lower portion of the resist 15 is performed similarly to the interlayer insulating film 13 shown in FIG. The amount increases. As a result, the memory cell section and the peripheral circuit section are smoothly connected.

Next, as shown in FIG.
After the removal, the storage node electrode 2 is formed on the memory cell portion.
And a cell plate electrode 3 to form a stack type capacitor.

Next, as shown in FIG. 14, the interlayer insulating film 2
1 is deposited on the entire surface. At this time, since the step portion generated by forming the stack type capacitor is already etched in the memory cell portion, sufficient flatness can be obtained even if the interlayer insulating film 21 is formed thinly. Therefore, it becomes easier to control the film thickness of the interlayer insulating film 21 than in the case of the first embodiment.

Next, as shown in FIG. 15, a contact hole resist pattern is formed (not shown) to form a contact hole 16. After that, by forming an aluminum film and then performing photoengraving and etching,
The aluminum wiring 6 is formed. At this time, since the interlayer insulating film 21 is formed flat, the resist film thickness can be made constant. Therefore, the exposure conditions at the time of forming the contact hole 16 and the aluminum wiring 6 can be made constant, and a fine pattern can be accurately formed.

Next, FIG. 16 is a sectional view of a portion orthogonal to FIG. As shown in FIG. 16, the interlayer insulating film 2
Since No. 1 is formed flat, the resist film thickness of the memory cell portion does not become thinner than that of the peripheral circuit portion when the aluminum wiring 6 is etched, and a part of the aluminum wiring 6 may disappear. Absent.

Embodiment 3. In the first and second embodiments, the step difference is reduced by forming the resist pattern for etching the interlayer insulating film. Here, the step difference of the interlayer insulating film is formed by using the resist pattern used in the general DRAM process. The case where the reduction is performed is described. 17 to 23 are process cross-sectional views showing the method of manufacturing the DRAM according to the third embodiment.
The description will be made sequentially according to the drawing.

First, as shown in FIG. 17, a field oxide film 8 is formed on the silicon substrate 1 to separate the memory cell portion and the peripheral circuit portion. After that, the DRA including the transfer gate electrode portion 10 and the impurity diffusion layer 9 is formed.
The M transistor and the bit line wiring 11 are formed. Further, after forming a silicon oxide film which is the interlayer insulating film 22 on the entire surface, BPTEOS which is the interlayer insulating film 23 is deposited on the entire surface.

Next, as shown in FIG. 18, the entire surface of the interlayer insulating film 23 is subjected to ammonia-hydrogen peroxide treatment by immersing it in ammonia-hydrogen peroxide mixture to reduce the B / P concentration on the surface of the interlayer insulating film 23, The low-concentration impurity layer 14 is formed on the surface of the insulating film 23.
To form. After that, a resist is applied to the entire surface, and then photolithography is performed to form a resist pattern 17 for the storage node contact.

Next, as shown in FIG. 19, dry etching is performed using the resist pattern 17 as a mask to open up to the surface of the silicon substrate 1. Then, wet etching or Vapor-HF in which a resist or a silicon oxide film and BPTEOS have an etching selection ratio.
Isotropic etching is performed to etch only BPTEOS which is the interlayer insulating film 23. At this time, since the low-concentration impurity layer 14 is formed on the surface of the interlayer insulating film 23 by performing the ammonia-hydrogen peroxide treatment, the amount of side etching to the lower portion of the resist 17 increases as in the first embodiment. . As a result, the memory cell section and the peripheral circuit section are smoothly connected. Also,
Since it is not necessary to separately form a resist pattern for reducing steps, the mask process can be reduced.

Then, as shown in FIG. 20, after removing resist pattern 17, a stack type capacitor including storage node electrode 2 and cell plate electrode 3 is formed in the memory cell portion.

Next, as shown in FIG. 21, the interlayer insulating film 1
8 is deposited on the entire surface. At this time, in the memory cell portion, the stack type capacitor is formed after the interlayer insulating film 23 is removed by etching, and since the step is already reduced, it is sufficient to form the interlayer insulating film 18 thinly. Flatness can be obtained. Therefore, it becomes easy to control the film thickness of the interlayer insulating film 18.

Next, as shown in FIG. 22, a contact hole resist pattern is formed (not shown) to form a contact hole 16. After that, by forming an aluminum film and then performing photoengraving and etching,
The aluminum wiring 6 is formed. At this time, since the interlayer insulating film 18 is formed flat, the resist film thickness can be made constant. Therefore, the exposure conditions at the time of forming the contact hole 16 and the aluminum wiring 6 can be made constant, and a fine pattern can be accurately formed.

Next, FIG. 23 is a sectional view of a portion orthogonal to FIG. As shown in FIG. 23, the interlayer insulating film 1
Since 8 is formed flat, the resist film thickness of the memory cell portion does not become thinner than the peripheral circuit portion when the aluminum wiring 6 is etched, and a part of the aluminum wiring 6 may disappear. Absent.

Fourth Embodiment In the third embodiment described above, as shown in FIG. 17, the case where BPTEOS, which is the interlayer insulating film 23, is formed immediately above the silicon oxide film, which is the interlayer insulating film 22, has been described. A silicon nitride film may be sandwiched between and. In this case, it is possible to prevent the diffusion of impurities such as B and P from BPTEOS, which is the interlayer insulating film 23, to the silicon oxide film, which is the interlayer insulating film 22, while having the same effect as in the third embodiment, and to perform wet etching and Va
It is possible to prevent overetching of the interlayer insulating film 22 due to contamination of the silicon oxide film which is the interlayer insulating film 22 with impurities when isotropic etching such as por-HF is performed.

[0039]

As described above, according to the present invention, the step of forming an interlayer insulating film containing B or P on a semiconductor substrate having a step, and the step of forming an interlayer insulating film containing B or P on the surface of the interlayer insulating film described above. Insulin containing a lower concentration of B or P than B or P
A step of forming a low-concentration impurity layer made of an edge film, a step of forming an etching mask for covering a stepped portion on the low-concentration impurity layer, and an interlayer containing B or P using the etching mask. Sa with the formation of the low concentration impurity layer for the step higher region of the insulating film and the low concentration impurity layer
Since the process for performing isotropic etching with an increased amount of id etching is provided, the steps in the interlayer insulating film can be satisfactorily reduced, and the resist film thickness can be uniformly formed in the subsequent process. And, there is an effect that a method of manufacturing a semiconductor device that can perform good etching can be obtained.

Further, a step of forming an interlayer insulating film containing B or P on the semiconductor substrate, and B or P having a lower concentration than B or P on the surface of the interlayer insulating film containing B or P.
A step of forming a low-concentration impurity layer formed of an insulating film containing a, a step of forming an etching mask covering a region on the low-concentration impurity layer that will be a step lower portion in a later step, and the etching mask By using the B or P-containing interlayer insulating film and the low-concentration impurity layer , the side is formed along with the formation of the low-concentration impurity layer by a predetermined thickness in advance.
Since the step of performing isotropic etching with an increased etching amount is provided, it is possible to form a thin interlayer insulating film thereon, which facilitates control of the film thickness of the interlayer insulating film, and in a subsequent step. There is an effect that a step can be reduced, a resist film formed thereafter can be made uniform, and photolithography and etching can be favorably performed, thereby obtaining a method for manufacturing a semiconductor device.

Further, after forming the transistor, a step of forming an interlayer insulating film containing B or P, and a step of forming a lower concentration than B or P on the surface of the interlayer insulating film containing B or P.
Above and forming a B or low concentration impurity layer made of an insulating film containing P, a step of forming a storage node contact forming resist on the low concentration impurity layer, a mask the storage node contact forming resist B or interlayer insulating film and the low-concentration impurity layer containing P, the side with the formation of rough <br/> beforehand the low concentration impurity layer with respect to a region for forming the capacitor after etch
Since the step of performing isotropic etching with an increased amount of etching and the step of forming the capacitor after removing the resist for forming the storage node contact are provided, it is possible to obtain a step in the subsequent step without increasing the number of masks. It is possible to obtain a method for manufacturing a semiconductor device in which the film thickness can be reduced, the resist film thickness formed thereafter can be made uniform, and photolithography and etching can be favorably performed.

Further, since the silicon oxide film is formed under the interlayer insulating film containing B or P, the silicon oxide film acts as an etching stopper when etching the interlayer insulating film containing B or P. This has the effect of favorably etching the contained interlayer insulating film.

Further, since the nitride film is formed between the interlayer insulating film containing B or P and the silicon oxide film, B or P is used.
Impurities can be prevented from diffusing from the inter-layer insulating film containing silicon to the silicon oxide film, and overetching due to the silicon oxide film being contaminated with impurities when isotropic etching is performed can be prevented.

Since the low-concentration impurity layer is formed by subjecting the interlayer insulating film containing B or P to the ammonia-hydrogen peroxide treatment, the low-concentration impurity layer can be easily formed on the surface of the interlayer insulating film. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a process sectional view showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a process sectional view showing the manufacturing method for the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a process sectional view showing the manufacturing method for the semiconductor device according to the first embodiment of the present invention.

FIG. 7 shows the semiconductor device according to the first embodiment of the present invention.
It is sectional drawing which shows the part orthogonal to.

FIG. 8 is a diagram showing an impurity concentration distribution on the surface of an interlayer insulating film when an ammonia-hydrogen peroxide treatment is performed.

FIG. 9 is a diagram showing changes in the side etching amount in the lower portion of the etching mask when the ammonia-hydrogen peroxide treatment is performed.

FIG. 10 is a process sectional view showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a process sectional view showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a process sectional view showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a process sectional view showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a process sectional view showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a process sectional view showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a sectional view showing a portion of the semiconductor device according to the second embodiment of the present invention, the portion being orthogonal to FIG. 16;

FIG. 17 is a step sectional view showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 18 is a step sectional view showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 19 is a process sectional view showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 20 is a process sectional view showing the manufacturing method of the semiconductor device according to the third embodiment of the present invention.

FIG. 21 is a process sectional view showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 22 is a process sectional view showing the manufacturing method for the semiconductor device according to the third embodiment of the present invention.

FIG. 23 is a sectional view showing a portion of the semiconductor device according to the third embodiment of the present invention, the portion being orthogonal to FIG. 22;

FIG. 24 is a cross-sectional view showing a conventional semiconductor device.

FIG. 25 is a cross-sectional view showing a portion of a conventional semiconductor device orthogonal to FIG. 24.

[Explanation of symbols]

1 silicon substrate, 9 impurity diffusion layer, 10 gate electrode, 12, 13, 20, 21, 22, 23 interlayer insulating film, 14 low concentration impurity layer, 15 resist pattern,
17 Storage node contact resist pattern.

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Claims (6)

(57) [Claims] 1. A step of forming an interlayer insulating film containing B or P on a semiconductor substrate having a step, and a step of forming a lower concentration of B or P on the surface of the interlayer insulating film containing B or P.
A step of forming a low-concentration impurity layer made of an insulating film containing B or P, a step of forming an etching mask for covering a stepped lower portion on the low-concentration impurity layer, and a step of forming the above-mentioned B using the etching mask. the low concentration impurity relative step higher region or interlayer insulating film and the low-concentration impurity layer containing P
And a step of performing isotropic etching in which the side etching amount is increased with the formation of the physical layer . 2. A step of forming an interlayer insulating film containing B or P on a semiconductor substrate, and B or P having a lower concentration than B or P on the surface of the interlayer insulating film containing B or P.
Using the etching mask, a step of forming a low-concentration impurity layer formed of an insulating film, a step of forming an etching mask on the low-concentration impurity layer, which covers a region to be a step lower portion in a later step, the previously given the thickness of only to the B or interlayer insulating film and the low-concentration impurity layer containing P with the formation of the low concentration impurity layer Saidoe
And a step of performing isotropic etching with an increased etching amount . 3. A method of manufacturing a semiconductor device in which a capacitor and a transistor are formed on a semiconductor substrate, a step of forming an interlayer insulating film containing B or P after forming the transistor, and a step of forming the interlayer insulating film containing B or P. Containing B or P at a lower concentration than the above B or P on the surface of the interlayer insulating film
Forming a low-concentration impurity layer made of an insulating film ,
Storage node contact type in the low concentration impurity layer
Forming a formed resist, the storage node contact interlayer insulating film formed resist as a mask containing the B or P and the low concentration impurity layer, previously the low concentrated to the region for forming the capacitor after
The amount of side etching increases with the formation of the impurity layer.
A method of manufacturing a semiconductor device, comprising: a step of performing isotropic etching; and a step of forming the capacitor after removing the storage node contact forming resist. 4. A method of manufacturing a semiconductor device according to claim 3, wherein a silicon oxide film is formed below an interlayer insulating film containing B or P. 5. The method for manufacturing a semiconductor device according to claim 4, wherein a nitride film is formed between the interlayer insulating film containing B or P and the silicon oxide film. 6. The semiconductor device according to claim 1, wherein the low-concentration impurity layer is formed by subjecting an interlayer insulating film containing B or P to an ammonia-hydrogen peroxide treatment. Manufacturing method.