JPH1022380A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the step on a layer insulation film and lessen the variation of thickness of the resist film on this insulation film to obtain a high reliability device allowing following steps of process to be well executed. SOLUTION: Ammoniacal hydrolysis is applied to BPTEOS to be a layer insulation film 13, thereby forming a low-concn. impurity layer 14 on the surface of the film 13. Using a resist 15, holes are formed for memory cells. Using the resist 15 as a mask, the film 13 is isotropically wet etched. This etching increases the side etching quantity at the lower part of the resist 15 about 4 times, thereby reducing the step on the insulation film 13. Thus a method of manufacturing high-reliability semiconductor devices is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an interlayer insulating film on a semiconductor device having a step.

[0002]

2. Description of the Related Art In a DRAM that requires the finest processing in a semiconductor device which is becoming more and more highly integrated, when a stacked type cell is employed to obtain a sufficient storage capacity, a memory cell portion and its peripheral portions are used. A step is generated between the circuit section and the circuit section.

FIG. 24 shows a conventional D cell having a stacked cell.
FIG. 3 is a cross-sectional view illustrating a RAM. As shown in FIG. 24A, the memory cell portion on the silicon substrate 1 is provided with the stacked capacitors 2 and 3, and a step occurs at the boundary between the memory cell portion and the peripheral circuit portion. Therefore, if the interlayer insulating film 4 is formed thereon, a step 4a will also occur in the interlayer insulating film 4. Furthermore, when a resist 5 for forming a contact is applied on the interlayer insulating film 4, the step 4
Due to the presence of a, the resist 5 is formed differently in the memory cell portion and the peripheral circuit portion.

After that, as shown in FIG. 24B, when a resist 5 pattern for contact is formed, the required exposure conditions are different between the resist patterns 5a and 5b because the thickness of the resist 5 is different. I will. Therefore,
It is very difficult to form fine resist patterns 5a and 5b simultaneously.

FIG. 25 is a cross-sectional view showing a portion orthogonal to FIG. 24 of a DRAM having a conventional stacked cell. As shown in FIG. 25A, as in FIG. 24A, the memory cell portion on the silicon substrate 1 includes the stacked capacitors 2 and 3, and the boundary between the memory cell portion and the peripheral circuit portion. There is a step in the part. Therefore, the steps 4a and 6a are also formed on the interlayer insulating film 4 and the aluminum wiring 6 thereon.
When a resist 7 for patterning the aluminum wiring 6 is applied thereon, the thickness of the resist 7 differs between the memory cell portion and the peripheral circuit portion due to the steps 4a and 6a.

Next, as shown in FIG. 25B, when the aluminum wiring 6 is etched, the aluminum wiring 6 may disappear depending on the etching conditions because the thickness of the resist 7 in the memory cell portion is small. .

[0007]

The DRAM having the conventional stacked capacitor is as described above. Since the memory cell section has the stacked capacitor, it is formed higher than the peripheral circuit section. Therefore, as shown in FIGS. 24 and 25, when the interlayer insulating film 4 is formed on the entire surface thereof, a step 4a occurs in the interlayer insulating film 4, and the thickness of the resist 5 varies in the opening of the contact hole. Opening failure is likely to occur due to this, and it is easy to disconnect at the step 4a of the interlayer insulating film 4 in forming wiring.
There is a problem that a good device cannot be manufactured.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is intended to reduce steps in an interlayer insulating film, reduce variations in the thickness of a resist on the interlayer insulating film, and improve the subsequent process. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of obtaining a highly reliable device that can be performed.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming an interlayer insulating film containing B or P on a semiconductor substrate having a step; Forming a low-concentration impurity layer on the surface of the inter-layer insulating film containing, a step of forming an etching mask covering a low step portion on the low-concentration impurity layer, and using the etching mask to form the B or P And a step of isotropically etching the stepped portion of the low-concentration impurity layer and the interlayer insulating film containing.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an interlayer insulating film containing B or P on a semiconductor substrate; Forming a high-concentration impurity layer, forming an etching mask on the low-concentration impurity layer to cover a region that will be a low step in a later step, and containing the B or P using the etching mask. Isotropically etching the interlayer insulating film and the low-concentration impurity layer by a predetermined thickness in advance.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a transistor and then forming an interlayer insulating film containing B or P; Forming a low-concentration impurity layer; forming a storage node contact resist on the low-concentration impurity layer; using the storage node contact resist as a mask; The method includes a step of isotropically etching a region of the impurity layer where the capacitor is to be formed later, and a step of forming the capacitor after removing the storage node contact resist.

According to a fourth aspect of the present invention, in a method of manufacturing a semiconductor device, a silicon oxide film is formed below an interlayer insulating film containing B or P.

According to a fifth aspect of the present invention, in a method of manufacturing a semiconductor device, a nitride film is formed between an interlayer insulating film containing B or P and a silicon oxide film.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the low-concentration impurity layer is formed by subjecting the interlayer insulating film containing B or P to an ammonia / hydrogen treatment.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 to 7 are process sectional views showing a method for manufacturing a DRAM of the present invention. The description will be made sequentially according to the drawings.

First, as shown in FIG. 1, a memory cell section and a peripheral circuit section are separated by forming a field oxide film 8 on a silicon substrate 1 which is a semiconductor substrate. Thereafter, the transfer gate electrode portion 10, the impurity diffusion layer 9
And a bit line wiring 11 of a DRAM comprising Further, after the interlayer insulating film 12 is formed on the entire surface, a stacked capacitor including the storage node electrode 2 and the cell plate electrode 3 is formed in the memory cell portion. After that, BPTEOS, which is the interlayer insulating film 13, is deposited on the entire surface. At this time, the step 13 is formed on the interlayer insulating film 13.
a has occurred.

Next, as shown in FIG. 2, the entire surface of the interlayer insulating film 13 is subjected to an ammonia / hydrogen treatment by dipping in an ammonia / hydrogen peroxide solution to lower the B / P concentration on the surface of the interlayer insulating film 13 and A low concentration impurity layer is formed on the surface of the insulating film. FIG. 8 shows the surface concentration distribution of P in the AA ′ portion of the interlayer insulating film 13 at this time. The same applies to B. Thereafter, a resist 15 is applied on the entire surface. Next, as shown in FIG. 3, photolithography is performed on the resist 15 to open the memory cell portion.

Next, as shown in FIG. 4, wet etching as isotropic etching is performed using the resist 15 as a mask, and the interlayer insulating film 13 is etched. At this time, a low concentration impurity layer 14 is formed on the surface of the interlayer insulating film 13 by performing a chemical treatment such as an ammonia peroxide process. As shown in FIG. 9, by forming the low-concentration impurity layer 14, the amount of side etching of the lower portion of the resist 15 is increased about four times. This is because the step portion of the interlayer insulating film 13 is etched, and the step between the memory cell portion and the peripheral circuit portion can be reduced.

Next, as shown in FIG. 5, after removing the resist 15, a resist pattern for a contact hole is formed (not shown), and a contact hole 16 is formed. At this time, since the step of the interlayer insulating film 13 is reduced, the resist film thickness can be made constant. Therefore, the exposure conditions for forming the contact holes 16 can be kept constant without being different, and a fine pattern can be formed with high accuracy.

Next, as shown in FIG. 6, by forming an aluminum film and then performing photolithography and etching,
An aluminum wiring 6 is formed. Also at this time, the interlayer insulating film 13
Since the step is reduced, the resist film thickness can be formed to be constant, the exposure conditions for forming the aluminum wiring 6 can be made constant, and a good pattern of aluminum wiring 6 can be formed.

FIG. 7 is a sectional view of a portion orthogonal to FIG. As shown in FIG. 7, since the step in the interlayer insulating film 13 is reduced, the resist film thickness in the memory cell portion does not become smaller than that in the peripheral circuit portion when the aluminum wiring 6 is etched. Does not disappear.

Embodiment 2 FIG. In the first embodiment, the method of reducing the level difference of the interlayer insulating film after forming the DRAM transistor and the capacitor on the silicon substrate has been described. However, after forming the DRAM transistor on the silicon substrate and before forming the capacitor, the capacitor is formed in advance. A step may be formed in the interlayer insulating film, and the step may be reduced by forming a capacitor. Figure 10
FIG. 16 is a process cross-sectional view illustrating a method for manufacturing the DRAM of the second embodiment, and the description will be made sequentially with reference to the drawings.

First, as shown in FIG. 10, a memory cell portion and a peripheral circuit portion are separated by forming a field oxide film 8 on a silicon substrate 1. After that, the DRA including the transfer gate electrode portion 10 and the impurity diffusion layer 9 is formed.
M transistors and bit line wiring 11 are formed. Thereafter, BPTEOS, which is an interlayer insulating film 20, is formed on the entire surface.
To form The entire surface of the interlayer insulating film 20 is subjected to an ammonia-hydrogen treatment by immersion in ammonia-hydrogen peroxide, and the B / P concentration on the surface of the interlayer insulating film 20 is reduced as shown in FIG. The low concentration impurity layer 14 is formed.

Next, as shown in FIG.
Is applied to the entire surface, and photolithography is performed on the resist 15 to open the memory cell portion.

Next, as shown in FIG.
Is used as a mask, and the interlayer insulating film 20 is etched. This means that an increase in the film thickness caused by forming a stacked capacitor in the memory cell portion is etched in advance. At this time, since the low-concentration impurity layer 14 is formed on the surface of the interlayer insulating film 20 by performing the ammonia-hydrogen treatment, the side etching of the lower portion of the resist 15 is performed similarly to the interlayer insulating film 13 shown in FIG. The amount increases. As a result, the memory cell section and the peripheral circuit section are smoothly connected.

Next, as shown in FIG.
Is removed, the storage node electrode 2 is
And a cell type capacitor 3 to form a stacked capacitor.

Next, as shown in FIG.
1 is deposited on the entire surface. At this time, since the step difference caused by forming the stacked capacitor in the memory cell portion has already been etched, sufficient flatness can be obtained even if the thickness of the interlayer insulating film 21 is reduced. Therefore, the thickness control of the interlayer insulating film 21 is easier than in the case of the first embodiment.

Next, as shown in FIG. 15, a resist pattern for a contact hole is formed (not shown), and a contact hole 16 is formed. After that, by forming an aluminum film and then performing photolithography and etching,
An aluminum wiring 6 is formed. At this time, since the interlayer insulating film 21 is formed flat, the resist film thickness can be made constant. Therefore, the exposure conditions for forming the contact hole 16 and the aluminum wiring 6 can be made constant, and a fine pattern can be formed with high accuracy.

FIG. 16 is a sectional view of a portion orthogonal to FIG. As shown in FIG. 16, the interlayer insulating film 2
Since 1 is formed flat, when the aluminum wiring 6 is etched, a part of the aluminum wiring 6 may disappear without the resist film thickness of the memory cell part being thinner than the peripheral circuit part. Absent.

Embodiment 3 In the first and second embodiments, the step is reduced by forming a resist pattern for etching the interlayer insulating film. However, here, the step of the interlayer insulating film is formed using a resist pattern used in a general DRAM process. The case where the reduction is performed will be described. 17 to 23 are process cross-sectional views illustrating a method of manufacturing the DRAM of the third embodiment, which will be sequentially described with reference to the drawings.

First, as shown in FIG. 17, a memory cell portion and a peripheral circuit portion are separated by forming a field oxide film 8 on a silicon substrate 1. After that, the DRA including the transfer gate electrode portion 10 and the impurity diffusion layer 9 is formed.
M transistors and bit line wiring 11 are formed. Further, after forming a silicon oxide film as the interlayer insulating film 22 on the entire surface, BPTEOS as the interlayer insulating film 23 is deposited on the entire surface.

Next, as shown in FIG. 18, the entire surface of the interlayer insulating film 23 is subjected to ammonia-hydrogen treatment by immersion in ammonia-hydrogen peroxide to lower the B / P concentration on the surface of the interlayer insulating film 23, The low concentration impurity layer 14 is formed on the surface of the insulating film 23.
To form Thereafter, a resist is applied to the entire surface, and then photolithography is performed to form a resist pattern 17 for a storage node contact.

Next, as shown in FIG. 19, an opening is made to the surface of the silicon substrate 1 by performing dry etching using the resist pattern 17 as a mask. Thereafter, the resist or the silicon oxide film and the BPTEOS are subjected to wet etching or Vapor-HF having an etching selectivity.
By performing isotropic etching, only BPTEOS which is the interlayer insulating film 23 is etched. At this time, since the low-concentration impurity layer 14 is formed on the surface of the interlayer insulating film 23 by performing the ammonia-hydrogen treatment, the amount of side etching to the lower portion of the resist 17 increases as in the first embodiment. . As a result, the memory cell section and the peripheral circuit section are smoothly connected. Also,
Since there is no need to separately form a resist pattern for reducing a step, the number of mask steps can be reduced.

Next, as shown in FIG. 20, after removing the resist pattern 17, a stacked capacitor comprising the storage node electrode 2 and the cell plate electrode 3 is formed in the memory cell portion.

Next, as shown in FIG.
8 is deposited on the entire surface. At this time, in the memory cell portion, the stacked capacitor is formed after the interlayer insulating film 23 is removed by etching, and since the step is already reduced, it is sufficient even if the interlayer insulating film 18 is formed thin. Flatness is obtained. Therefore, it is easy to control the thickness of the interlayer insulating film 18.

Next, as shown in FIG. 22, a resist pattern for a contact hole is formed (not shown), and a contact hole 16 is formed. After that, by forming an aluminum film and then performing photolithography and etching,
An aluminum wiring 6 is formed. At this time, since the interlayer insulating film 18 is formed flat, the resist film thickness can be made constant. Therefore, the exposure conditions for forming the contact hole 16 and the aluminum wiring 6 can be made constant, and a fine pattern can be formed with high accuracy.

FIG. 23 is a cross-sectional view of a portion orthogonal to FIG. As shown in FIG.
8 is formed flat, when etching the aluminum wiring 6, the resist film thickness of the memory cell portion does not become thinner than that of the peripheral circuit portion, and a part of the aluminum wiring 6 may disappear. Absent.

Embodiment 4 FIG. In the third embodiment, as shown in FIG. 17, the case where the BPTEOS as the interlayer insulating film 23 is formed immediately above the silicon oxide film as the interlayer insulating film 22 has been described.
3, a silicon nitride film may be interposed therebetween. in this case,
The same effect as in the third embodiment can be obtained, and diffusion of impurities such as B and P from BPTEOS as the interlayer insulating film 23 to the silicon oxide film as the interlayer insulating film 22 can be prevented, and wet etching, Vapor-HF, etc. When the isotropic etching is performed, overetching of the interlayer insulating film 22 due to contamination of the silicon oxide film serving as the interlayer insulating film 22 with impurities can be prevented.

[0039]

As described above, according to the present invention, a step of forming an interlayer insulating film containing B or P on a semiconductor substrate having a step, and a step of forming a lower surface on the surface of the interlayer insulating film containing B or P, Forming a high concentration impurity layer, forming an etching mask covering a low step portion on the low concentration impurity layer, and forming the B or P using the etching mask.
And a step of isotropically etching the stepped portion of the low-concentration impurity layer containing the interlayer insulating film, so that the step of the interlayer insulating film can be reduced satisfactorily, and the resist film thickness can be made uniform in the subsequent steps. There is an effect that a method of manufacturing a semiconductor device which can be formed and can perform photolithography and etching well can be obtained.

A step of forming an interlayer insulating film containing B or P on a semiconductor substrate; a step of forming a low concentration impurity layer on the surface of the interlayer insulating film containing B or P; Forming an etching mask on the layer to cover a region which will be a step lower portion in a later step; and forming the B or P-containing interlayer insulating film and the low-concentration impurity layer into a predetermined thickness using the etching mask. A step of performing isotropic etching only by a certain amount, so that the interlayer insulating film thereon can be formed thin, so that the thickness of the interlayer insulating film can be easily controlled and a step is reduced in a later step. Thus, there is an effect that a method of manufacturing a semiconductor device in which a resist film formed thereafter can be made uniform and photolithography and etching can be favorably performed can be obtained.

A step of forming an interlayer insulating film containing B or P after forming the transistor; a step of forming a low-concentration impurity layer on the surface of the interlayer insulating film containing B or P; Forming a storage node contact resist on the impurity layer; and forming a region for forming the capacitor later in the interlayer insulating film containing B or P and the low concentration impurity layer using the storage node contact resist as a mask. Since the method includes the step of isotropic etching and the step of forming the capacitor after removing the resist for the storage node contact, a step can be reduced in a post-process without increasing the number of masks, and the formation after that Semiconductor device capable of making photolithography and etching excellent by making the resist film thickness uniform The effect of manufacturing process is obtained.

Further, since the silicon oxide film is formed under the interlayer insulating film containing B or P, the silicon oxide film acts as an etching stopper when etching the interlayer insulating film containing B or P, thereby forming B or P. There is an effect that the contained interlayer insulating film can be favorably etched.

Since a nitride film is formed between the silicon oxide film and the interlayer insulating film containing B or P,
Has the effect of preventing diffusion of impurities from the interlayer insulating film containing Si into the silicon oxide film and preventing overetching due to contamination of the silicon oxide film by the impurities during isotropic etching.

Further, since the low-concentration impurity layer is formed by subjecting the interlayer insulating film containing B or P to ammonia / hydrogen treatment, it is possible to easily form the low-concentration impurity layer on the surface of the interlayer insulating film. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device of a first embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 7 shows the semiconductor device according to the first embodiment of the present invention;
It is sectional drawing which shows the part orthogonal to FIG.

FIG. 8 is a diagram showing an impurity concentration distribution on the surface of an interlayer insulating film when an ammonia peroxide process is performed.

FIG. 9 is a diagram showing a change in the amount of side etching under the etching mask when an ammonia-hydrogen peroxide treatment is performed.

FIG. 10 is a process sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 11 is a process sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 12 is a process sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 15 is a process sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a portion of the semiconductor device according to the second embodiment of the present invention which is orthogonal to FIG. 16;

FIG. 17 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 18 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 19 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 20 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 21 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 22 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 23 is a cross-sectional view showing a portion of the semiconductor device according to the third embodiment of the present invention orthogonal to FIG. 22;

FIG. 24 is a cross-sectional view showing a conventional semiconductor device.

FIG. 25 is a cross-sectional view showing a portion of the conventional semiconductor device orthogonal to FIG.

[Explanation of symbols]

1 silicon substrate, 9 impurity diffusion layer, 10 gate electrode, 12, 13, 20, 21, 22, 23 interlayer insulating film, 14 low concentration impurity layer, 15 resist pattern,
17 Resist pattern for storage node contact.

Claims (6)

[Claims] A step of forming an interlayer insulating film containing B or P on a semiconductor substrate having a step; a step of forming a low-concentration impurity layer on the surface of the interlayer insulating film containing B or P; Forming an etching mask covering the low step portion on the low-concentration impurity layer, and isotroping the high-step portion of the B or P-containing interlayer insulating film and the low-concentration impurity layer using the etching mask. Etching the semiconductor device. A step of forming an interlayer insulating film containing B or P on a semiconductor substrate; a step of forming a low concentration impurity layer on the surface of the interlayer insulating film containing B or P; Forming an etching mask on the layer to cover a region which will be a step lower portion in a later step; and forming the B or P-containing interlayer insulating film and the low-concentration impurity layer into a predetermined thickness using the etching mask. A method of manufacturing a semiconductor device, comprising a step of performing isotropic etching by a certain amount. 3. A method of manufacturing a semiconductor device in which a capacitor and a transistor are formed on a semiconductor substrate, wherein a step of forming an interlayer insulating film containing B or P after forming the transistor; A step of forming a low-concentration impurity layer on the surface of the interlayer insulating film, a step of forming a storage node contact resist on the low-concentration impurity layer, and an interlayer containing B or P using the storage node contact resist as a mask A step of previously isotropically etching a region of the insulating film and the low concentration impurity layer where the capacitor is to be formed later; and a step of forming the capacitor after removing the storage node contact resist. Manufacturing method of a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a silicon oxide film is formed under the interlayer insulating film containing B or P. 5. The method of manufacturing a semiconductor device according to claim 4, wherein a nitride film is formed between the interlayer insulating film containing B or P and the silicon oxide film. 6. The semiconductor device according to claim 1, wherein said low-concentration impurity layer is formed by subjecting an interlayer insulating film containing B or P to an ammonia / hydrogen treatment. Manufacturing method.