JP2004071840A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device wherein a MIM capacitor can be effectively formed without deteriorating the reliability of a capacitor insulating film. <P>SOLUTION: A lower metal film 2 as a lower electrode and an upper metal film 4 as an upper electrode are deposited on a substrate 1, respectively, and then a resist 5 is patterned with lithography, which is in turn used to dry-etch the metal film 4. Thereafter, the insulating film 7 is deposited and is subjected to anisotropic dry-etching into a spacer shape such that it remains on a side wall of the upper metal film 4 as a side wall insulating film 7a, and simultaneously the capacitor insulating film 3 is dry-etched using the insulating film 7 and the upper metal film 4 as a mask. Hereby, the width of the capacitor insulating film 3 can be more increased than in the upper metal film 4 while more reducing the number of times of the formation of the resist 5 than in prior art. Thus, the manufacturing cost can be suppressed together with an improvement of the reliability of the capacitive insulating film 3. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a capacitance section formed on a semiconductor integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art In a CMOS semiconductor integrated circuit device equipped with an analog circuit, a capacitor (Metal-Insulator-Metal structure, MIM structure) in which a conductive film such as polysilicon is used as upper and lower electrodes and an insulating film is formed between them is often used. I have.
[0003]
FIG. 2 is a process sectional view showing a method for manufacturing such an MIM type capacitor.
First, a laminated film for MIM formation as shown in FIG. 2A is formed. 1 is a substrate, 2 is a lower metal film serving as a lower electrode, 3 is a capacitor insulating film, 4 is an upper metal film serving as an upper electrode, and 5 is a resist.
[0004]
Then, the upper metal film 4 and the capacitor insulating film 3 are sequentially dry-etched using the resist 5 and the resist is removed, so that the upper metal film 4 and the capacitor insulating film 3 are formed as desired as shown in FIG. Process into shape.
[0005]
Thereafter, a resist having a desired shape larger than the pattern of the upper metal film 4 and the capacitor insulating film 3 is patterned by a new lithography step (not shown), and the lower metal film 2 is dry-etched using the resist as a mask. Thereby, a pattern of the lower metal film 2 is formed.
[0006]
FIG. 3 is a process cross-sectional view illustrating another method for manufacturing an MIM-type capacitor.
A laminated film for forming the MIM as shown in FIG. 1 is a substrate, 2 is a lower metal film serving as a lower electrode, 3 is a capacitor insulating film, 4 is an upper metal film serving as an upper electrode, and 5 is a resist.
[0007]
Next, the upper metal film 4 is selectively etched using the resist 5 as a mask, and the resist is removed, thereby processing the upper metal film 4 into a desired shape as shown in FIG.
[0008]
Next, a pattern of a resist 6 that covers the upper metal film 4 as shown in FIG. 3C is formed, and the capacitive insulating film 3 is dry-etched using the resist 6 as a mask, and the resist 6 is removed. The insulating film 3 is processed into a desired shape as shown in FIG.
[0009]
Thereafter, a new lithography step (not shown) is performed to etch the lower metal film 2 into a desired shape larger than the pattern of the capacitor insulating film 3.
[0010]
[Problems to be solved by the invention]
However, each of the above-described methods for forming the MIM type capacitor has advantages and disadvantages.
[0011]
In the capacitance forming method described with reference to FIG. 2, although the resist is formed by lithography only once until the pattern formation of the capacitance insulating film 3, the pattern width of the formed capacitance insulating film 3 is equal to the pattern width of the upper metal film 4. Is the same or narrower than In particular, when the capacitor insulating film 3 is narrowed due to side etching, an interlayer insulating film having a low dielectric constant and a low withstand voltage formed around the capacitor in a process after completion of the capacitor is used as a capacitor insulating film between the metal films 4 and 2. The membrane 3 penetrates the narrowed end. In this state, when the metal films 4 and 2 are operated by applying a voltage as upper and lower electrodes, the capacitance becomes a value corresponding to the amount of side etching, so that variations occur between the same type of capacitance, and the withstand voltage decreases. is there.
[0012]
In the capacitance forming method described with reference to FIG. 3, since the capacitance insulating film 3 can be formed wider than the upper metal film 4, the above-described electrical reliability problems such as the variation in capacitance value and the decrease in withstand voltage do not occur. Since a high-cost resist pattern forming process is required twice in the stage until the pattern formation of the capacitive insulating film 3, the operation is complicated, and there is a disadvantage that the cost of the semiconductor integrated circuit device is increased.
[0013]
An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of efficiently forming an MIM-type capacitor without impairing the reliability of a capacitor insulating film.
[0014]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention is a method for manufacturing a semiconductor device in which a capacitor having a capacitor insulating film disposed between an upper electrode and a lower electrode is mounted, wherein a first conductive film is deposited on a substrate. A step of depositing a first insulating film on the first conductive film; a step of depositing a second conductive film on the first insulating film; and selectively forming the second conductive film on the first conductive film. Forming the upper electrode pattern by removing the upper electrode pattern, forming a second insulating film on a side wall of the upper electrode pattern, and using the upper electrode pattern and the second insulating film as a mask. Etching the first insulating film to form a pattern of the capacitive insulating film.
[0015]
According to the above configuration, the second insulating film is formed on the side wall of the pattern of the upper electrode, and the first insulating film is etched while being masked to be larger than the pattern of the upper electrode. Is always larger than the pattern of the upper electrode. Therefore, there is no variation in capacitance value and no reduction in breakdown voltage due to the pattern width of the capacitor insulating film becoming narrower than the pattern of the upper electrode, and electrical reliability can be ensured.
[0016]
Specifically, in the step of selectively removing the second conductive film, a resist pattern is formed on the second conductive film, and the second conductive film is etched using the resist pattern as a mask to form an upper electrode. In the step of forming a second insulating film on the side wall of the pattern, a second insulating film is deposited by covering the pattern of the upper electrode, and the second insulating film is anisotropically etched. .
[0017]
According to the above configuration, since no resist is used for forming the pattern of the second insulating film, the manufacturing cost can be reduced. In addition, since the second insulating film can be formed to have an arbitrary size within a certain range by using anisotropic etching, the pattern of the capacitive insulating film can be made to be exactly larger than the pattern of the upper electrode by a certain size. As a result, the margin between the upper electrode pattern and the capacitor insulating film pattern can be set small, which is advantageous for miniaturization of the pattern.
[0018]
As the second insulating film, any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a stacked composite film thereof can be used.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, which illustrates a method for manufacturing an MIM type capacitor incorporated in a semiconductor device.
[0020]
First, a laminated film for MIM formation as shown in FIG. 1A is formed. 1 is a semiconductor substrate, 2 is a lower metal film serving as a lower electrode, 3 is a capacitor insulating film, 4 is an upper metal film serving as an upper electrode, and 5 is a resist.
[0021]
Although not shown, the semiconductor substrate 1 has an insulating film such as SiO ₂ formed on the surface, and a transistor, a wiring, and the like are formed below the insulating film. The lower metal film 2 and the upper metal film 4 may be any conductive film, and may be Al, Cu, an Al / Cu alloy, Pt, Ti, TiN, or the like. A metal film to be formed, for example, a Ti film, a TiN film, or an Al / Cu laminated film is used. The film thickness of the lower metal film 2 and the upper metal film 4 is 50 to 400 nm. The capacitance insulating film 3 is a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), a silicon nitride oxide film (SiON), a high dielectric constant film such as tantalum oxide, or a laminated composite film of these films. . The thickness of the capacitance insulating film 3 is 30 to 150 nm. The resist 5 has a desired pattern for the upper electrode, but may be formed as the same layer as the wiring pattern inside the integrated circuit, or may be formed as a mask layer dedicated to the upper electrode.
[0022]
The upper metal film 4 is dry-etched by using the resist 5 as a mask with respect to such a laminated film so as to be processed into a desired shape as shown in FIG. 1B, and then the resist 5 is ashed and washed. Remove.
[0023]
Next, as shown in FIG. 1C, an insulating film 7 is deposited on the entire surface to a thickness of 100 to 300 nm by a plasma CVD method at about 400 ° C. or the like.
Next, as shown in FIG. 1D, the insulating film 7 is anisotropically etched and left at least on the side wall portion of the upper metal film 4, and at the same time, the sidewall insulating film 7a remaining on this side wall and the upper metal film 4 is used as a mask to etch the capacitor insulating film 3. At this time, the thickness of the side wall of the insulating film 7 is about 50 to 300 nm due to the property of the anisotropic etching. It becomes big.
[0024]
Thereafter, a resist pattern wider than the capacitor insulating film 3 is formed by a new lithography step (not shown) to cover the region of the capacitor insulating film 3, and then the lower metal film 2 is selectively etched to obtain a capacitor. A lower electrode pattern having a desired shape larger than the pattern of the insulating film 3 is formed.
[0025]
The standard capacitance value of the MIM-type capacitor mounted on the semiconductor device in this manner is several fF / μm 2, and 1 to 1 between the upper metal film (upper electrode) 4 and the lower metal film (lower electrode) 2. A voltage of about 10 V is applied during operation.
[0026]
According to the manufacturing method as described above, since the capacitance insulating film 3 is etched using the sidewall insulating film 7a formed on the side wall of the upper metal film (upper electrode) 4 as a mask, a resist pattern is formed by a lithography process. Thus, the capacitance insulating film 3 having a size larger than that of the upper metal film (upper electrode) 4 can be formed.
[0027]
Therefore, the lithography step can be reduced by one time as compared with the conventional method described above with reference to FIG. 3, and the manufacturing cost can be reduced.
Because the pattern size of the capacitor insulating film 3 is smaller than that of the upper metal film (upper electrode) 4 as in the above-described conventional method, another insulating film having poor characteristics is formed under the upper metal film (upper electrode) 4. Since the film does not enter, electrical reliability can be ensured. For this purpose, the thickness of the insulating film 7 formed in the step of FIG. 1C may be reduced to about 10 nm to 100 nm.
[0028]
Moreover, since the sidewall insulating film 7a is formed by anisotropic etching, it can be formed to have an arbitrary thickness within a certain range, whereby the pattern of the capacitor insulating film 3 can be accurately formed with respect to the pattern of the upper metal film 4. Can be increased by a certain size. Therefore, the margin between the pattern of the upper metal film 4 and the pattern of the capacitor insulating film 3 can be made very small, which is advantageous for miniaturization of the pattern.
[0029]
On the other hand, in the conventional method using a resist pattern (see FIG. 3C), a mask misalignment with respect to the pattern of the upper metal film 4 always occurs. A large dimensional margin is required for the third pattern.
[0030]
【The invention's effect】
As described above, according to the present invention, prior to processing the capacitance insulating film of the MIM type capacitor, the second insulating film is formed on the side wall of the electrode pattern on the insulating film, and these electrode patterns and the second Since the insulating film is etched using the insulating film as a mask, the size of the capacitor insulating film can be made larger than the electrode pattern without increasing the number of times of lithography. Reliability can be secured.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, which illustrates a method of forming an MIM-type capacitor.
FIG. 2 is a process cross-sectional view illustrating a conventional method of forming an MIM-type capacitor. FIG. 3 is a process cross-sectional view illustrating another conventional method of forming an MIM-type capacitor.
DESCRIPTION OF SYMBOLS 1 Substrate 2 Lower metal film 3 Capacitive insulating film 4 Upper metal film 5 Resist 7 Insulating film 7a Sidewall insulating film

Claims (3)

A method for manufacturing a semiconductor device including a capacitor having a capacitor insulating film disposed between an upper electrode and a lower electrode,
Depositing a first conductive film on the substrate;
Depositing a first insulating film on the first conductive film;
Depositing a second conductive film on the first insulating film;
Forming a pattern of the upper electrode by selectively removing the second conductive film;
Forming a second insulating film on a side wall of the pattern of the upper electrode;
Forming a pattern of the capacitive insulating film by etching the first insulating film using the pattern of the upper electrode and the second insulating film as a mask. A step of selectively removing the second conductive film, forming a resist pattern on the second conductive film, etching the second conductive film using the resist pattern as a mask,
A step of forming a second insulating film on a side wall of the pattern of the upper electrode, depositing a second insulating film covering the pattern of the upper electrode, and anisotropically etching the second insulating film; 2. The method for manufacturing a semiconductor device according to item 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is any one of a silicon oxide film, a silicon nitride film, and a silicon nitride oxide film, or a laminated composite film thereof.

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