US20040121593A1 - Method for manufacturing semiconductor device through use of mask material - Google Patents

Method for manufacturing semiconductor device through use of mask material Download PDF

Info

Publication number
US20040121593A1
US20040121593A1 US10/630,747 US63074703A US2004121593A1 US 20040121593 A1 US20040121593 A1 US 20040121593A1 US 63074703 A US63074703 A US 63074703A US 2004121593 A1 US2004121593 A1 US 2004121593A1
Authority
US
United States
Prior art keywords
mask
film
pattern
mask material
resist pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/630,747
Inventor
Takeshi Matsunuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MATSUNUMA, TAKESHI
Publication of US20040121593A1 publication Critical patent/US20040121593A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for forming a fine pattern through use of a mask material.
  • the mask material becomes unnecessary after the film to be processed has been etched, it must be removed. In a conventional method, however, it was difficult to remove only the mask material selectively without etching the film to be processed. Therefore, there was a problem that the thickness of the film to be processed 33 was changed.
  • the present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful method for manufacturing a semiconductor device.
  • a more specific object of the present invention is to remove a mask material selectively without etching a film to be processed and is to form a fine pattern easily through use of a mask material.
  • the above object of the present invention is attained by a following method for manufacturing a semiconductor device.
  • a film to be processed is formed on a substrate.
  • a mask material is formed on the film to be processed.
  • a resist pattern is formed on the mask material.
  • the mask material is patterned using the resist pattern as a mask.
  • the mask material is shrunk.
  • the film to be processed is patterned using a shrunk mask material as a mask. The shrunk mask material is removed.
  • a film to be processed is formed on a substrate.
  • a ruthenium film is formed as a mask material on the film to be processed.
  • a resist pattern is formed on the mask material.
  • the mask material is patterned using the resist pattern as a mask.
  • the film to be processed is patterned using a patterned mask material as a mask. The patterned mask material is removed.
  • FIGS. 1A to 1 F are sectional views for illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention
  • FIGS. 2A to 2 E are sectional views for illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
  • FIGS. 3A to 3 D are sectional views for illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
  • FIG. 4 is a sectional view for illustrating a case that an etching of shoulders occurs in the film to be processed.
  • FIGS. 1A to 1 F are sectional views for illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Specifically, FIGS. 1A to 1 F are diagrams for illustrating a method for forming a fine gate wiring in an ASIC and the like.
  • FIG. 1A shows, a gate oxide film of a thickness of about 5 nm is formed as a gate insulating film 12 on a silicon wafer as a substrate 11 .
  • a polysilicon film of a thickness of about 150 nm is formed as a gate wiring material 13 on the gate insulating film 12 .
  • a ruthenium (Ru) film of a thickness of about 20 nm is formed as a mask material 14 on the gate wiring material 13 .
  • a resist pattern 15 is formed on the mask material 14 .
  • the mask material 14 is subjected to anisotropic etching using the resist pattern 15 as a mask to form a mask-material pattern 14 a .
  • This anisotropic etching is performed, for example, in an ICP (inductively coupled plasma) etching apparatus, and the etching conditions are as follows.
  • High-frequency power 1500 W (upper electrode)
  • the mask-material pattern 14 a is subjected to isotropic etching to form a fine mask-material pattern 14 b having a pattern width narrower than the pattern width of the mask-material pattern 14 a . That is, the mask-material pattern 14 a is shrunk or retracted by isotropic etching.
  • This isotropic etching is performed, for example, in an ICP etching apparatus, and the etching conditions are as follows.
  • High-frequency power 1500 W (upper electrode)
  • the gate wiring material 13 is subjected to anisotropic etching using the fine mask-material pattern 14 b as a mask to form a gate wiring 13 a .
  • This anisotropic etching is performed, for example, in an ECR etching apparatus, and the etching conditions are as follows.
  • High-frequency power 400 W (upper electrode)
  • the fine mask-material pattern 14 b is removed to form a gate wiring 13 a on the gate insulating film 12 .
  • the removal of the fine mask-material pattern 14 b is performed, for example, in a down-flow-type ashing apparatus, and the ashing conditions are as follows.
  • Microwave power 1400 W
  • a ruthenium film which was a metal film, was formed as the mask material 14 .
  • the mask-material pattern 14 a was formed by anisotropic etching using the resist pattern 15 as the mask
  • the mask-material pattern 14 a was shrunk by isotropic etching
  • the gate wiring 13 a was formed by anisotropic etching using the shrunk fine mask-material pattern 14 b as the mask.
  • the polysilicon film as the gate wiring 13 has a high etching selectivity against the ruthenium film as the mask material 14 , the deterioration of the pattern, such as the etching of the mask material can be prevented. Furthermore, the removal of the ruthenium film as the mask material 14 has a high selectivity against the gate wiring material (polysilicon film) and the gate insulating film (oxide film). Therefore, the mask-material pattern 14 b can be selectively removed easily without etching the gate wiring material 13 a . Hence, change in the film thickness of the gate wiring 13 a can be prevented. Therefore, the gate wiring 13 a of a desired shape can be formed easily.
  • a fine pattern (fine gate wiring 13 a ) can be formed easily by using the fine mask-material pattern 14 b as the mask.
  • the mask material 14 is not limited to the ruthenium film, but a metal film such as a tungsten (W) film and a titanium nitride (TiN) film can also be used.
  • a metal film such as a tungsten (W) film and a titanium nitride (TiN) film
  • tungsten film is used as the mask material 14
  • TiN titanium nitride
  • the use of an aqueous solution of H 2 O 2 for shrinking and removing the mask material result in the same effect as using the ruthenium film as the mask material.
  • a titanium nitride film is used as the mask material 14
  • the use of an aqueous solution of H 2 SO 4 for shrinking and removing the mask material result in the same effect.
  • the resist pattern 15 is removed after the mask-material pattern is shrunk, the order may be reversed. That is, after the mask-material pattern has been formed by etching using the resist pattern 15 as the mask, and the resist pattern 15 has been removed, the mask-material pattern may be shrunk. In this case, since the upper surface of the mask-material pattern is also etched when the mask-material pattern is shrunk, the formed thickness of the mask material 14 is increased to, for example, about 60 nm.
  • FIGS. 2A to 2 E are sectional views for illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Specifically, FIGS. 2A to 2 E are diagrams for illustrating a method for forming a fine gate wiring in an ASIC and the like, as in FIGS. 1A to 1 F.
  • FIG. 2A shows, a gate insulating film 12 , a gate wiring material 13 , a ruthenium film (Ru film) as a mask material 14 , and a resist pattern 15 are formed on a silicon wafer 11 in the same manner as in the above-described first embodiment (refer to FIG. 1A).
  • a gate insulating film 12 As FIG. 2A shows, a gate insulating film 12 , a gate wiring material 13 , a ruthenium film (Ru film) as a mask material 14 , and a resist pattern 15 are formed on a silicon wafer 11 in the same manner as in the above-described first embodiment (refer to FIG. 1A).
  • Ru film ruthenium film
  • FIG. 2B shows, a mask-material pattern 14 a is formed in the same manner as in the first embodiment (refer to FIG. 1B).
  • the resist pattern 15 and the mask-material pattern 14 a are subjected to isotropic etching. Thereby, the resist pattern 15 and the mask-material pattern 14 a are shrunk or retracted.
  • This isotropic etching is performed, for example, in an ICP etching apparatus, and the etching conditions are as follows.
  • High-frequency power 1500 W (upper electrode)
  • the gate wiring material 13 is subjected to anisotropic etching using the shrunk resist pattern 15 a and the shrunk mask-material pattern 14 b as a mask to form a gate wiring 13 a .
  • This anisotropic etching is performed, for example, in an ECR etching apparatus, and the etching conditions are as follows.
  • High-frequency power 400 W (upper electrode)
  • the resist pattern 15 a and the mask-material pattern 14 b is removed to form a gate wiring 13 a on the gate insulating film 12 .
  • the removal of the resist pattern 15 a and the mask-material pattern 14 b is performed, for example, in a down-flow-type ashing apparatus, and the ashing conditions are as follows.
  • Microwave power 1400 W
  • the resist pattern 15 and the mask-material pattern 14 a are shrunk by isotropic etching, and the gate wiring 13 a was formed by anisotropic etching using the shrunk fine resist pattern 15 a and the shrunk mask-material pattern 14 b as the mask. Thereafter, the resist pattern 15 a and the mask-material pattern 14 b are simultaneously removed.
  • the mask-material pattern 14 b and the resist pattern 15 can be simultaneously removed under the condition that the Ru film, which is the mask-material pattern 14 b , is removed.
  • FIGS. 3A to 3 D are sectional views for illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. Specifically, FIGS. 3A to 3 D are sectional views for illustrating a method for forming a via hole connected to metal wirings in an ASIC or a memory element such as a DRAM.
  • an under-layer wiring 21 is formed on a substrate (not shown), and a silicon oxide film (such as a TEOS film, a BSG film, and a BPSG film) of a thickness of about 1.5 ⁇ m is formed as an interlayer insulating film 22 above the under-layer wiring 21 .
  • a silicon oxide film such as a TEOS film, a BSG film, and a BPSG film
  • a ruthenium (Ru) film of a thickness of about 30 nm is formed as a mask material 24 on the interlayer insulating film 22 .
  • a resist pattern 25 is formed on the mask material 24 .
  • the mask material 24 is subjected to anisotropic etching using the resist pattern 25 as a mask to form a mask-material pattern 24 a .
  • This anisotropic etching is performed, for example, in an ICP etching apparatus, and the etching conditions are as follows.
  • High-frequency power 1500 W (upper electrode)
  • the interlayer insulating film 22 is subjected to anisotropic etching using the resist pattern 25 and the mask-material pattern 24 a as a mask to form a via hole 26 reaching the under-layer wiring 21 from the surface of the interlayer insulating film 22 .
  • This anisotropic etching is performed, for example, in an ECR etching apparatus, and the etching conditions are as follows.
  • High-frequency power 1700 W (upper electrode)
  • the resist pattern 25 and the mask-material pattern 24 a are removed to form a via hole 26 connected to the under-layer wiring 21 in the interlayer insulating film 22 .
  • the removal of the resist pattern 25 and the mask-material pattern 24 a is performed, for example, in a down-flow-type ashing apparatus, and the ashing conditions are as follows.
  • Microwave power 1400 W
  • a via hole 26 connected to the under-layer wiring 21 was formed in the interlayer insulating film 22 by anisotropic etching using the resist pattern 25 and the mask-material pattern 24 a as a mask. Thereafter, the mask-material pattern 24 a was removed.
  • the removal of the ruthenium film as the mask material has a high selectivity against the interlayer insulating film, the metal material (wiring material), and the substrate material. Therefore, the mask-material pattern 24 a can be selectively removed easily without etching the interlayer insulating film 22 , the under-layer wiring 21 , and the substrate.
  • the ruthenium film is removed in a dry state using ashing, the dissolution of metal materials as in wet etching does not occur even if the metal materials, such as wirings, are exposed on the surface of the substrate. Therefore, the via hole 26 of a desired shape can be easily formed without etching the interlayer insulating film and the under-layer wiring, that is, without deteriorating the pattern.
  • the mask-material pattern 24 a and the resist pattern 25 can be simultaneously removed under the condition that the mask-material pattern 24 a is removed after the via hole 26 has been formed. Therefore, there is obtained the effect whereby no process step to remove only the resist pattern 25 after transferring the pattern onto the Ru film is required, and the number of manufacturing process steps can be reduced.
  • the present invention can also be applied to the formation of a contact hole connected to the substrate.
  • a metal film other than a ruthenium film such as a tungsten film and a titanium nitride film can be formed as the mask material.
  • An aqueous solution of H 2 O 2 can be used for removing the tungsten film; and an aqueous solution of H 2 SO 4 can be used for removing the titanium nitride film.
  • the resist pattern 25 can be removed after a mask-material pattern 24 a has been formed as in the first embodiment, and the via hole 26 can be formed using the mask-material pattern 24 a as a mask.
  • the mask material can be selectively removed without etching the film to be processed. Also according the present invention, a fine pattern can be easily formed through use of the mask material.

Abstract

A gate oxide film is formed on a substrate. A polysilicon film is formed on the gate oxide film. A ruthenium film is formed as a mask material on the polysilicon film. A resist pattern is formed on the ruthenium film. After the ruthenium film is patterned using the resist pattern as a mask, a the patterned ruthenium film is shrunk. After the polysilicon film is patterned using a shrunk the shrunken ruthenium film, the shrunk shrunken ruthenium film is removed.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for forming a fine pattern through use of a mask material. [0002]
  • 2. Description of the Background Art [0003]
  • There has been known a method for forming a fine pattern wherein a silicon oxide film, a silicon nitride film, or a polysilicon film is used as a mask material to etch a film to be processed immediately underneath the mask material. [0004]
  • However, since an etching selectivity of the film to be processed against the mask material is low, shoulders of the mask material are etched when the film to be processed is etched. As shown in FIG. 4, when the amount of the etched shoulders of the mask material is large, an etching of [0005] shoulders 33 a may also occur in the film to be processed (for example, polysilicon film) 33 disposed immediately underneath the mask material. Here, in FIG. 4, the film to be processed 33 is formed on the gate insulating film 32 formed on the substrate 31.
  • Since the mask material becomes unnecessary after the film to be processed has been etched, it must be removed. In a conventional method, however, it was difficult to remove only the mask material selectively without etching the film to be processed. Therefore, there was a problem that the thickness of the film to be processed [0006] 33 was changed.
  • Therefore, the conventional method for manufacturing semiconductor devices had a problem of the deterioration of patterns. [0007]
    • SUMMARY OF THE INVENTION
  • The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful method for manufacturing a semiconductor device. [0008]
  • A more specific object of the present invention is to remove a mask material selectively without etching a film to be processed and is to form a fine pattern easily through use of a mask material. [0009]
  • The above object of the present invention is attained by a following method for manufacturing a semiconductor device. [0010]
  • According to one aspect of the present invention, in the method for manufacturing a semiconductor device, a film to be processed is formed on a substrate. A mask material is formed on the film to be processed. A resist pattern is formed on the mask material. The mask material is patterned using the resist pattern as a mask. The mask material is shrunk. The film to be processed is patterned using a shrunk mask material as a mask. The shrunk mask material is removed. [0011]
  • According to another aspect of the present invention, in the method for manufacturing a semiconductor device, a film to be processed is formed on a substrate. A ruthenium film is formed as a mask material on the film to be processed. A resist pattern is formed on the mask material. The mask material is patterned using the resist pattern as a mask. The film to be processed is patterned using a patterned mask material as a mask. The patterned mask material is removed. [0012]
  • Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. [0013]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to [0014] 1F are sectional views for illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;
  • FIGS. 2A to [0015] 2E are sectional views for illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention;
  • FIGS. 3A to [0016] 3D are sectional views for illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention; and
  • FIG. 4 is a sectional view for illustrating a case that an etching of shoulders occurs in the film to be processed.[0017]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In the following, principles and embodiments of the present invention will be described with reference to the accompanying drawings. The members and steps that are common to some of the drawings are given the same reference numerals and redundant descriptions therefore may be omitted. [0018]
  • First Embodiment [0019]
  • FIGS. 1A to [0020] 1F are sectional views for illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Specifically, FIGS. 1A to 1F are diagrams for illustrating a method for forming a fine gate wiring in an ASIC and the like.
  • First, as FIG. 1A shows, a gate oxide film of a thickness of about 5 nm is formed as a [0021] gate insulating film 12 on a silicon wafer as a substrate 11. A polysilicon film of a thickness of about 150 nm is formed as a gate wiring material 13 on the gate insulating film 12. Next, a ruthenium (Ru) film of a thickness of about 20 nm is formed as a mask material 14 on the gate wiring material 13. Then, a resist pattern 15 is formed on the mask material 14.
  • Next, as FIG. 1B shows, the [0022] mask material 14 is subjected to anisotropic etching using the resist pattern 15 as a mask to form a mask-material pattern 14 a. This anisotropic etching is performed, for example, in an ICP (inductively coupled plasma) etching apparatus, and the etching conditions are as follows.
  • High-frequency power: 1500 W (upper electrode) [0023]
  • 200 W (lower electrode) [0024]
  • Pressure: 30 mTorr [0025]
  • Gas: O[0026] 2/Cl2=100/10 sccm
  • Next, as FIG. 1C shows, the mask-[0027] material pattern 14 a is subjected to isotropic etching to form a fine mask-material pattern 14 b having a pattern width narrower than the pattern width of the mask-material pattern 14 a. That is, the mask-material pattern 14 a is shrunk or retracted by isotropic etching. This isotropic etching is performed, for example, in an ICP etching apparatus, and the etching conditions are as follows.
  • High-frequency power: 1500 W (upper electrode) [0028]
  • 80 W (lower electrode) [0029]
  • Pressure: 20 mTorr [0030]
  • Gas: O[0031] 2/Cl2=160/20 sccm
  • Then, as FIG. 1D shows, the resist [0032] pattern 15 is removed.
  • Next, as FIG. 1E shows, the [0033] gate wiring material 13 is subjected to anisotropic etching using the fine mask-material pattern 14 b as a mask to form a gate wiring 13 a. This anisotropic etching is performed, for example, in an ECR etching apparatus, and the etching conditions are as follows.
  • High-frequency power: 400 W (upper electrode) [0034]
  • 30 W (lower electrode) [0035]
  • Pressure: 4 mTorr [0036]
  • Gas: HBr/Cl[0037] 2/O2=70/30/50 sccm
  • Finally, as FIG. 1F shows, the fine mask-[0038] material pattern 14 b is removed to form a gate wiring 13 a on the gate insulating film 12. The removal of the fine mask-material pattern 14 b is performed, for example, in a down-flow-type ashing apparatus, and the ashing conditions are as follows.
  • Microwave power: 1400 W [0039]
  • Pressure: 2 Torr [0040]
  • Gas: O[0041] 2/N2=900/100 sccm
  • Temperature: 200° C. [0042]
  • In the first embodiment, as described above, a ruthenium film, which was a metal film, was formed as the [0043] mask material 14. After the mask-material pattern 14 a was formed by anisotropic etching using the resist pattern 15 as the mask, the mask-material pattern 14 a was shrunk by isotropic etching, and the gate wiring 13 a was formed by anisotropic etching using the shrunk fine mask-material pattern 14 b as the mask.
  • According to the first embodiment, since the polysilicon film as the [0044] gate wiring 13 has a high etching selectivity against the ruthenium film as the mask material 14, the deterioration of the pattern, such as the etching of the mask material can be prevented. Furthermore, the removal of the ruthenium film as the mask material 14 has a high selectivity against the gate wiring material (polysilicon film) and the gate insulating film (oxide film). Therefore, the mask-material pattern 14 b can be selectively removed easily without etching the gate wiring material 13 a. Hence, change in the film thickness of the gate wiring 13 a can be prevented. Therefore, the gate wiring 13 a of a desired shape can be formed easily.
  • Also, since the mask can be shrunk easily, and the fine mask-[0045] material pattern 14 b can be obtained easily, a fine pattern (fine gate wiring 13 a) can be formed easily by using the fine mask-material pattern 14 b as the mask.
  • In the first embodiment, although a ruthenium film is used as the [0046] mask material 14, the mask material 14 is not limited to the ruthenium film, but a metal film such as a tungsten (W) film and a titanium nitride (TiN) film can also be used. Here, when a tungsten film is used as the mask material 14, the use of an aqueous solution of H2O2 for shrinking and removing the mask material result in the same effect as using the ruthenium film as the mask material. Also, when a titanium nitride film is used as the mask material 14, the use of an aqueous solution of H2SO4 for shrinking and removing the mask material result in the same effect.
  • Also in the first embodiment, although the resist [0047] pattern 15 is removed after the mask-material pattern is shrunk, the order may be reversed. That is, after the mask-material pattern has been formed by etching using the resist pattern 15 as the mask, and the resist pattern 15 has been removed, the mask-material pattern may be shrunk. In this case, since the upper surface of the mask-material pattern is also etched when the mask-material pattern is shrunk, the formed thickness of the mask material 14 is increased to, for example, about 60 nm.
  • Second Embodiment [0048]
  • FIGS. 2A to [0049] 2E are sectional views for illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Specifically, FIGS. 2A to 2E are diagrams for illustrating a method for forming a fine gate wiring in an ASIC and the like, as in FIGS. 1A to 1F.
  • First, as FIG. 2A shows, a [0050] gate insulating film 12, a gate wiring material 13, a ruthenium film (Ru film) as a mask material 14, and a resist pattern 15 are formed on a silicon wafer 11 in the same manner as in the above-described first embodiment (refer to FIG. 1A).
  • Next, as FIG. 2B shows, a mask-[0051] material pattern 14 a is formed in the same manner as in the first embodiment (refer to FIG. 1B).
  • Next, as FIG. 2C shows, the resist [0052] pattern 15 and the mask-material pattern 14 a are subjected to isotropic etching. Thereby, the resist pattern 15 and the mask-material pattern 14 a are shrunk or retracted. This isotropic etching is performed, for example, in an ICP etching apparatus, and the etching conditions are as follows.
  • High-frequency power: 1500 W (upper electrode) [0053]
  • 50 W (lower electrode) [0054]
  • Pressure: 50 mTorr [0055]
  • Gas: O[0056] 2/Cl2=200/20 sccm
  • Next, as FIG. 2D shows, the [0057] gate wiring material 13 is subjected to anisotropic etching using the shrunk resist pattern 15 a and the shrunk mask-material pattern 14 b as a mask to form a gate wiring 13 a. This anisotropic etching is performed, for example, in an ECR etching apparatus, and the etching conditions are as follows.
  • High-frequency power: 400 W (upper electrode) [0058]
  • 30 W (lower electrode) [0059]
  • Pressure: 4 mTorr [0060]
  • Gas: HBr/Cl[0061] 2/O2=70/30/50 sccm
  • Finally, as FIG. 2E shows, the resist [0062] pattern 15 a and the mask-material pattern 14 b is removed to form a gate wiring 13 a on the gate insulating film 12. The removal of the resist pattern 15 a and the mask-material pattern 14 b is performed, for example, in a down-flow-type ashing apparatus, and the ashing conditions are as follows.
  • Microwave power: 1400 W [0063]
  • Pressure: 2 Torr [0064]
  • Gas: O[0065] 2/N2=900/100 sccm
  • Temperature: 200° C. [0066]
  • In the second embodiment, as described above, after the mask-[0067] material pattern 14 a is formed by anisotropic etching using the resist pattern 15 as the mask, the resist pattern 15 and the mask-material pattern 14 a are shrunk by isotropic etching, and the gate wiring 13 a was formed by anisotropic etching using the shrunk fine resist pattern 15 a and the shrunk mask-material pattern 14 b as the mask. Thereafter, the resist pattern 15 a and the mask-material pattern 14 b are simultaneously removed.
  • According to the second embodiment, after the [0068] gate wiring 13 a has been formed, the mask-material pattern 14 b and the resist pattern 15 can be simultaneously removed under the condition that the Ru film, which is the mask-material pattern 14 b, is removed.
  • Therefore, in addition to the effect obtained in the first embodiment, there is obtained the effect whereby no process step to remove only the resist [0069] pattern 15 after transferring the pattern onto the Ru film is required, and the number of manufacturing process steps can be reduced.
  • Third Embodiment [0070]
  • FIGS. 3A to [0071] 3D are sectional views for illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. Specifically, FIGS. 3A to 3D are sectional views for illustrating a method for forming a via hole connected to metal wirings in an ASIC or a memory element such as a DRAM.
  • First, as FIG. 3A shows, an under-[0072] layer wiring 21 is formed on a substrate (not shown), and a silicon oxide film (such as a TEOS film, a BSG film, and a BPSG film) of a thickness of about 1.5 μm is formed as an interlayer insulating film 22 above the under-layer wiring 21. Next, a ruthenium (Ru) film of a thickness of about 30 nm is formed as a mask material 24 on the interlayer insulating film 22. Then, a resist pattern 25 is formed on the mask material 24.
  • Next, as FIG. 3B shows, the [0073] mask material 24 is subjected to anisotropic etching using the resist pattern 25 as a mask to form a mask-material pattern 24 a. This anisotropic etching is performed, for example, in an ICP etching apparatus, and the etching conditions are as follows.
  • High-frequency power: 1500 W (upper electrode) [0074]
  • 200 W (lower electrode) [0075]
  • Pressure: 30 mTorr [0076]
  • Gas: O[0077] 2/Cl2=100/10 sccm
  • Next, as FIG. 3C shows, the [0078] interlayer insulating film 22 is subjected to anisotropic etching using the resist pattern 25 and the mask-material pattern 24 a as a mask to form a via hole 26 reaching the under-layer wiring 21 from the surface of the interlayer insulating film 22. This anisotropic etching is performed, for example, in an ECR etching apparatus, and the etching conditions are as follows.
  • High-frequency power: 1700 W (upper electrode) [0079]
  • 700 W (lower electrode) [0080]
  • Pressure: 4 mTorr [0081]
  • Gas: C[0082] 4F8/Ar/CO=25/200/20 sccm
  • Finally, as FIG. 3D shows, the resist [0083] pattern 25 and the mask-material pattern 24 a are removed to form a via hole 26 connected to the under-layer wiring 21 in the interlayer insulating film 22. The removal of the resist pattern 25 and the mask-material pattern 24 a is performed, for example, in a down-flow-type ashing apparatus, and the ashing conditions are as follows.
  • Microwave power: 1400 W [0084]
  • Pressure: 2 Torr [0085]
  • Gas: O[0086] 2/N2=900/100 sccm
  • Temperature: 200° C. [0087]
  • According to the third embodiment, as described above, after a mask-[0088] material pattern 24 a had been formed by anisotropic etching using a resist pattern 25 as a mask, a via hole 26 connected to the under-layer wiring 21 was formed in the interlayer insulating film 22 by anisotropic etching using the resist pattern 25 and the mask-material pattern 24 a as a mask. Thereafter, the mask-material pattern 24 a was removed.
  • According to the third embodiment, the removal of the ruthenium film as the mask material has a high selectivity against the interlayer insulating film, the metal material (wiring material), and the substrate material. Therefore, the mask-[0089] material pattern 24 a can be selectively removed easily without etching the interlayer insulating film 22, the under-layer wiring 21, and the substrate. In particular, since the ruthenium film is removed in a dry state using ashing, the dissolution of metal materials as in wet etching does not occur even if the metal materials, such as wirings, are exposed on the surface of the substrate. Therefore, the via hole 26 of a desired shape can be easily formed without etching the interlayer insulating film and the under-layer wiring, that is, without deteriorating the pattern.
  • Also according to the third embodiment, the mask-[0090] material pattern 24 a and the resist pattern 25 can be simultaneously removed under the condition that the mask-material pattern 24 a is removed after the via hole 26 has been formed. Therefore, there is obtained the effect whereby no process step to remove only the resist pattern 25 after transferring the pattern onto the Ru film is required, and the number of manufacturing process steps can be reduced.
  • Although a method for forming a via hole connected to the under-[0091] layer wiring 21 was described in the third embodiment, the present invention can also be applied to the formation of a contact hole connected to the substrate. In this case, since wet etching can be used for removing the mask material, a metal film other than a ruthenium film, such as a tungsten film and a titanium nitride film can be formed as the mask material. An aqueous solution of H2O2 can be used for removing the tungsten film; and an aqueous solution of H2SO4 can be used for removing the titanium nitride film.
  • Although the number of manufacturing process steps increases, only the resist [0092] pattern 25 can be removed after a mask-material pattern 24 a has been formed as in the first embodiment, and the via hole 26 can be formed using the mask-material pattern 24 a as a mask.
  • This invention, when practiced illustratively in the manner described above, provides the following major effects: [0093]
  • According to the present invention, the mask material can be selectively removed without etching the film to be processed. Also according the present invention, a fine pattern can be easily formed through use of the mask material. [0094]
  • Further, the present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention. [0095]
  • The entire disclosure of Japanese Patent Application No. 2002-335764 filed on Nov. 19, 2002 containing specification, claims, drawings and summary are incorporated herein by reference in its entirety. [0096]

Claims (6)

What is claimed is:
1. A method for manufacturing a semiconductor device comprising the steps of;
forming a film to be processed on a substrate;
forming a mask material on the film to be processed;
forming a resist pattern on the mask material;
patterning the mask material using the resist pattern as a mask;
shrinking a patterned mask material;
patterning the film to be processed using a shrunk mask material as a mask; and
removing the shrunk mask material.
2. The method for manufacturing a semiconductor device according to claim 1,
wherein a metal film is formed as the mask material.
3. The method for manufacturing a semiconductor device according to claim 2,
wherein a ruthenium film is formed as the mask material, and
the shrunk mask material is removed together with the resist pattern using oxygen-containing plasma.
4. A method for manufacturing a semiconductor device comprising the steps of;
forming a film to be processed on a substrate;
forming a ruthenium film as a mask material on the film to be processed;
forming a resist pattern on the mask material;
patterning the mask material using the resist pattern as a mask;
patterning the film to be processed using a patterned mask material as a mask; and
removing the patterned mask material.
5. The method for manufacturing a semiconductor device according to claim 4,
wherein the patterned mask material is removed together with the resist pattern using oxygen-containing plasma.
6. The method for manufacturing a semiconductor device according to claim 5,
wherein the patterned mask material is removed in the state that a metal material is exposed on the substrate.
US10/630,747 2002-11-19 2003-07-31 Method for manufacturing semiconductor device through use of mask material Abandoned US20040121593A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002335764A JP2004172311A (en) 2002-11-19 2002-11-19 Manufacturing method of semiconductor device
JP2002-335764 2002-11-19

Publications (1)

Publication Number Publication Date
US20040121593A1 true US20040121593A1 (en) 2004-06-24

Family

ID=32588055

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/630,747 Abandoned US20040121593A1 (en) 2002-11-19 2003-07-31 Method for manufacturing semiconductor device through use of mask material

Country Status (5)

Country Link
US (1) US20040121593A1 (en)
JP (1) JP2004172311A (en)
KR (1) KR20040044162A (en)
CN (1) CN1503323A (en)
TW (1) TW200409197A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040203236A1 (en) * 2003-04-08 2004-10-14 Dongbu Electronics Co., Ltd. Submicron semiconductor device and a fabricating method thereof
US9075316B2 (en) 2013-11-15 2015-07-07 Globalfoundries Inc. EUV mask for use during EUV photolithography processes
US20190237331A1 (en) * 2018-01-30 2019-08-01 Tokyo Electron Limited Metal hard mask layers for processing of microelectronic workpieces
US20200051833A1 (en) * 2018-08-10 2020-02-13 Tokyo Electron Limited Ruthenium Hard Mask Process

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5432798B2 (en) * 2010-03-30 2014-03-05 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804088A (en) * 1996-07-12 1998-09-08 Texas Instruments Incorporated Intermediate layer lithography
US5976769A (en) * 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
US6008135A (en) * 1997-11-13 1999-12-28 Samsung Electronics Co., Ltd. Method for etching metal layer of a semiconductor device using hard mask
US6277760B1 (en) * 1998-06-26 2001-08-21 Lg Electronics Inc. Method for fabricating ferroelectric capacitor
US6291251B1 (en) * 1999-06-10 2001-09-18 Lg Electronics Inc. Method for fabricating ferroelectric memory
US6387774B1 (en) * 1996-12-17 2002-05-14 Samsung Electronics Co., Ltd. Methods for forming patterned layers including notched etching masks

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976769A (en) * 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
US5804088A (en) * 1996-07-12 1998-09-08 Texas Instruments Incorporated Intermediate layer lithography
US6387774B1 (en) * 1996-12-17 2002-05-14 Samsung Electronics Co., Ltd. Methods for forming patterned layers including notched etching masks
US6008135A (en) * 1997-11-13 1999-12-28 Samsung Electronics Co., Ltd. Method for etching metal layer of a semiconductor device using hard mask
US6277760B1 (en) * 1998-06-26 2001-08-21 Lg Electronics Inc. Method for fabricating ferroelectric capacitor
US6291251B1 (en) * 1999-06-10 2001-09-18 Lg Electronics Inc. Method for fabricating ferroelectric memory

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040203236A1 (en) * 2003-04-08 2004-10-14 Dongbu Electronics Co., Ltd. Submicron semiconductor device and a fabricating method thereof
US7186649B2 (en) * 2003-04-08 2007-03-06 Dongbu Electronics Co. Ltd. Submicron semiconductor device and a fabricating method thereof
US9075316B2 (en) 2013-11-15 2015-07-07 Globalfoundries Inc. EUV mask for use during EUV photolithography processes
US9217923B2 (en) 2013-11-15 2015-12-22 Globalfoundries Inc. Method of using an EUV mask during EUV photolithography processes
US20190237331A1 (en) * 2018-01-30 2019-08-01 Tokyo Electron Limited Metal hard mask layers for processing of microelectronic workpieces
US10950444B2 (en) * 2018-01-30 2021-03-16 Tokyo Electron Limited Metal hard mask layers for processing of microelectronic workpieces
US20200051833A1 (en) * 2018-08-10 2020-02-13 Tokyo Electron Limited Ruthenium Hard Mask Process
WO2020033309A1 (en) * 2018-08-10 2020-02-13 Tokyo Electron Limited Ruthenium hard mask process
US11183398B2 (en) 2018-08-10 2021-11-23 Tokyo Electron Limited Ruthenium hard mask process

Also Published As

Publication number Publication date
TW200409197A (en) 2004-06-01
KR20040044162A (en) 2004-05-27
CN1503323A (en) 2004-06-09
JP2004172311A (en) 2004-06-17

Similar Documents

Publication Publication Date Title
JP2001156170A (en) Manufacturing method for multilayer interconnection
US6589880B2 (en) Fine pattern formation method and semiconductor device or liquid crystal device manufacturing method employing this method
US6753133B2 (en) Method and manufacturing a semiconductor device having a ruthenium or a ruthenium oxide
JP3312604B2 (en) Method for manufacturing semiconductor device
KR20020037684A (en) Method of manufacturing semiconductor device
US5960293A (en) Methods including oxide masks for fabricating capacitor structures for integrated circuit devices
US20040121593A1 (en) Method for manufacturing semiconductor device through use of mask material
US6395639B1 (en) Process for improving line width variations between tightly spaced and isolated features in integrated circuits
US6861327B2 (en) Method for manufacturing gate spacer for self-aligned contact
KR100278277B1 (en) Method for improve contact resistance of silicide in semiconductor device
JP2907314B2 (en) Method for manufacturing semiconductor device
US6406999B1 (en) Semiconductor device having reduced line width variations between tightly spaced and isolated features
JP2001118927A (en) Semiconductor device and manufacturing method therefor
US6197630B1 (en) Method of fabricating a narrow bit line structure
KR100912958B1 (en) Method for fabricating fine pattern in semiconductor device
JP3780657B2 (en) Etching method
KR0139072B1 (en) Method of fabricating semiconductor device having step of forming play in contact hole
JP2715877B2 (en) Method for manufacturing semiconductor device
KR100235960B1 (en) Method of forming conducting line in semiconductor device
JP2000260871A (en) Manufacture of semiconductor device
KR100832027B1 (en) Forming method of semiconductor device pattern capable of protecting tapered profile of hardmask
KR20050068363A (en) Method for fabricating thin pattern using the hard mask
JP4196898B2 (en) Manufacturing method of semiconductor device
KR100525106B1 (en) method for forming a storage node pattern in a semiconductor device
JPH11168072A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: RENESAS TECHNOLOGY CORP., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MATSUNUMA, TAKESHI;REEL/FRAME:014349/0022

Effective date: 20030708

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION