TW202005101A - Capacitor structures and methods for fabricating the same - Google Patents

Abstract

A capacitor structure includes a first electrode plate disposed on a substrate, a first capacitor dielectric layer disposed on the first electrode plate, and a second electrode plate disposed on the first capacitor dielectric layer. A portion of the first electrode plate extends beyond an end of the second electrode plate to form a step. The capacitor structure also includes an etching stop layer, an inter-metal dielectric layer, a first via and a second via. The etching stop layer is disposed on the second electrode plate. The inter-metal dielectric layer covers the etching stop layer, the second electrode plate, the first capacitor dielectric layer and the first electrode plate. The first via penetrates through the inter-metal dielectric layer to contact the first electrode plate at the portion extending beyond the second electrode plate. The second via penetrates through the inter-metal dielectric layer to contact the second electrode plate.

Description

Capacitor structure and its manufacturing method

The embodiments of the present invention relate to a capacitor structure, and particularly to a metal-insulator-metal (MIM) capacitor structure and a manufacturing method thereof.

The capacitor structure is generally used for electronic passive components in semiconductor integrated circuits (ICs), such as radio frequency (RF) circuits and mixed signal (MS) circuits. The types of traditional capacitor structures used in integrated circuits include metal-insulator-semiconductor (MIS) capacitors, PN junction capacitors, and polysilicon-insulator-polysilicon (PIP) capacitors .

However, these conventional capacitor structures use a semiconductor layer (for example, polysilicon) as a capacitor electrode, and thus have a higher series resistance, and have a disadvantage of being unstable in a high-frequency circuit. Furthermore, during operation, the semiconductor electrode of the PN junction capacitor generates a depletion layer, which results in the limitation of its frequency characteristics. Therefore, compared to these conventional capacitor structures, metal-insulator-metal (MIM) capacitors can provide lower series resistance and lower power consumption characteristics, and are suitable for today's mixed-signal circuit and high-frequency circuit applications. In addition, metal-insulator-metal (MIM) capacitors can be formed in the metal interconnection stage of the semiconductor manufacturing process, reducing the front end of line with complementary metal oxide semiconductor (CMOS) FEOL) The difficulty and complexity of process integration.

The semiconductor integrated circuit industry has made many developments in an effort to reduce the size of components. However, in the continuously shrinking area, metal-insulator-metal (MIM) capacitors need to maintain their high capacitance values, so the manufacturing process of metal-insulator-metal (MIM) capacitors also faces many new challenges.

Some embodiments of the present invention provide a capacitor structure including a first electrode plate disposed on a substrate, a first capacitor dielectric layer disposed on the first electrode plate, and a capacitor structure disposed on the first capacitor dielectric layer Second electrode plate. A part of the first electrode plate extends beyond one end of the second electrode plate to form a step. The capacitor structure further includes an etch stop layer, an inter-metal dielectric layer, a first via hole and a second via hole. The etch stop layer is disposed on the second electrode plate, and the intermetal dielectric layer covers the etch stop layer, the second electrode plate, the first capacitor dielectric layer, and the first electrode plate. The first via hole passes through the intermetal dielectric layer to contact the first electrode plate at a portion extending beyond the second electrode plate. The second via hole passes through the intermetal dielectric layer and the etch stop layer to contact the second electrode plate.

Some embodiments of the present invention provide a capacitor structure including a first electrode plate disposed on a substrate, a first capacitor dielectric layer disposed on the first electrode plate, and a capacitor structure disposed on the first capacitor dielectric layer Second electrode plate. A part of the first electrode plate extends beyond one end of the second electrode plate to form a step. The first electrode plate includes a first anti-reflection coating, the second electrode plate includes a second anti-reflection coating, and the thickness of the second anti-reflection coating is greater than the thickness of the first anti-reflection coating. The capacitor structure further includes an inter-metal dielectric layer, a first via hole and a second via hole. The inter-metal dielectric layer covers the second electrode plate, the first capacitor dielectric layer and the first electrode plate. The first via hole passes through the intermetal dielectric layer to contact the first electrode plate at a portion extending beyond the second electrode plate. The second via hole passes through the intermetal dielectric layer to contact the second electrode plate.

Some embodiments of the present invention provide a method for manufacturing a capacitor structure. This method includes sequentially forming a first electrode plate material layer, a first dielectric layer, a second electrode plate material layer, and a first etch stop layer on a substrate An etch stop layer and a second electrode plate material layer are patterned to form a patterned first etch stop layer and a second electrode plate, respectively, and the first dielectric layer and the first electrode plate material layer are patterned to form respectively The first capacitor dielectric layer and the first electrode plate, wherein a part of the first electrode plate extends beyond one end of the second electrode plate to form a step. The method further includes forming an intermetal dielectric layer on the substrate to cover the patterned first etch stop layer, the second electrode plate, the first capacitor dielectric layer and the first electrode plate, forming a first opening through the intermetal dielectric The electrical layer until the portion where the first electrode plate extends beyond the second electrode plate is exposed, forming a second opening through the intermetal dielectric layer and patterning the first etch stop layer until the second electrode plate is exposed, and forming the first A guide hole is in the first opening and a second guide hole is in the second opening.

The capacitor structure of the present invention can be applied to various types of capacitor structures. In order to make the features and advantages of the present invention more obvious and understandable, the following examples are specifically applied to metal-insulator-metal (MIM) capacitor structures, and According to the attached drawings, detailed descriptions are as follows.

100, 100’, 200, 300, 400, 500, 600 ‧‧‧ capacitor structure

102‧‧‧ base

110, 110’‧‧‧ First metal layer

112, 112’‧‧‧ The first anti-reflective coating

114‧‧‧First dielectric layer

114’‧‧‧ First Capacitor Dielectric Layer

114L1, 114L2, 114L3, 114L4, 114L5

116‧‧‧ First electrode plate material layer

116’‧‧‧First electrode plate

116L1, 116L2, 116L3, 116L4, 116L5

120、120’‧‧‧Second metal layer

122, 122’‧‧‧Second anti-reflective coating

124‧‧‧Second dielectric layer

124’‧‧‧Second capacitor dielectric layer

126‧‧‧Second electrode plate material layer

126’‧‧‧Second Electrode Plate

130, 130’‧‧‧third metal layer

132, 132’‧‧‧third anti-reflective coating

136‧‧‧ Third electrode plate material layer

136’‧‧‧third electrode plate

140、140’‧‧‧First etching stop layer

142,142’‧‧‧Second etching stop layer

143‧‧‧Etching stop layer

144‧‧‧Interlayer dielectric layer

146‧‧‧First opening

146L1, 146L2, 146L3, 146L4, 146L5

148‧‧‧Second opening

150‧‧‧ third opening

152‧‧‧First pilot hole

152L1, 152L2, 152L3, 152L4, 152L5

154‧‧‧Second pilot hole

156‧‧‧third guide hole

158‧‧‧First endpoint

158L1, 158L2, 158L3, 158L4, 158L5

160‧‧‧The second endpoint

162‧‧‧The third endpoint

170‧‧‧The first patterning process

175‧‧‧Second patterning process

180‧‧‧The third patterning process

185‧‧‧The fourth patterning process

T1‧‧‧ First thickness

T2‧‧‧Second thickness

T3‧‧‧thickness

T4‧‧‧thickness

T5‧‧‧ fifth thickness

Through the following detailed description and examples in conjunction with the accompanying drawings, the embodiments of the present invention can be better understood. In order to make the drawings clear, different elements in the drawings may not be drawn to scale. Among them: FIGS. 1A to 1H are schematic cross-sectional views showing the manufacturing process of the capacitor structure at various stages according to some embodiments of the present invention.

1I and 2-6 are schematic cross-sectional views of capacitor structures according to some other embodiments of the present invention.

The following disclosure provides many embodiments or examples for implementing different elements of the provided capacitor structure. Specific examples of components and their configurations are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the first element is formed on the second element in the description, it may include an embodiment where the first and second elements are in direct contact, or may include additional elements formed between the first and second elements , So that they do not directly contact the embodiment. In addition, embodiments of the present invention may repeat reference numerals and/or letters in different examples. This repetition is for conciseness and clarity, not for expressing the relationship between the different embodiments discussed.

Some variations of the embodiments are described below. In the different drawings and illustrated embodiments, similar element symbols are used to indicate similar elements. It can be understood that additional steps may be provided before, during, and after the method, and some of the described steps may be replaced or deleted in other embodiments of the method.

The present invention provides an embodiment of a capacitor structure and a manufacturing method thereof, which is particularly suitable for metal-insulator-metal type (MIM) capacitor structures, but other capacitor structures can also be used, such as metal-insulator-semiconductor type (MIS) capacitors, PN Area capacitors and polysilicon-insulator-polysilicon (PIP) capacitors.

Traditionally, in the manufacturing process of a stacked capacitor structure, when forming via plates to electrode plates at various levels, since the electrode plates at various levels are located at different levels, the etching process for forming via openings may Insufficient etching and/or excessive etching. Embodiments of the present invention utilize the adjustment of the thickness of the etch stop layer on the electrode plate and/or the anti-reflective coating of the electrode plate. These thicknesses increase as the level of the electrode plate increases, so that under the same etching time, the etching depth The difference can be compensated by the difference in thickness between the etch stop layer and/or the anti-reflective coating. Therefore, the embodiments of the present invention can form a plurality of via holes with different depths to the corresponding electrode plates through one etching process, which can greatly reduce the manufacturing time and cost of the capacitor structure.

FIGS. 1A-1H are schematic cross-sectional views of the process of forming the capacitor structure 100 of FIG. 1H at various stages according to some embodiments of the present invention. Please refer to FIG. 1A to provide a substrate 102. The substrate 102 may be any substrate that can be used to form a capacitive structure thereon. In some embodiments, the substrate 102 may be a silicon substrate, a silicon germanium (SiGe) substrate, a bulk semiconductor substrate, a compound semiconductor substrate, a silicon on insulator (SOI) substrate Or similar substrate. In one embodiment, the substrate 102 is a silicon substrate, and the substrate 102 may include active devices (not shown), such as transistors, diodes, or the like. In addition, the substrate 102 may include a metal interconnection structure (not shown), such as an inter-layer dielectric (ILD), a contact plug, and an inter-metal dielectric (IMD) ), metal wires and vias. For the sake of simplicity, only a flat substrate 102 is shown here.

Next, the first electrode plate material layer 116 is formed on the substrate 102. The first electrode plate material layer 116 includes a first metal layer 110 and a first anti-reflection coating 112 on the first metal layer 110. In some embodiments, the material of the first metal layer 110 may be or include aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), rhodium (Rh), molybdenum (Mo ), nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), similar materials, the foregoing alloys, or a combination of the foregoing, and any suitable deposition method may be used to form the first metal layer 110, for example Physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating or a combination of the foregoing. In one embodiment, the first metal layer 110 includes an aluminum-copper alloy and has a thickness ranging from about 300 angstrom to about 10,000 angstrom. In some embodiments, the material of the first anti-reflective coating 112 may be a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), similar materials, or a combination of the foregoing, and any suitable deposition may be used Method to form the first anti-reflective coating 112, such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination of the foregoing. In one embodiment, the first anti-reflective coating 112 includes titanium nitride (TiN), and the first thickness T1 of the first anti-reflective coating 112 is in the range of about 100 angstroms to about 2000 angstroms.

Next, the first dielectric layer 114 is formed on the first electrode plate material layer 116. In some embodiments, the first dielectric layer 114 may be a high-k dielectric material whose dielectric constant value (k value) depends on design requirements. In some embodiments, the material of the first dielectric layer 114 may be or include silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), similar materials, the foregoing multiple layers (for example, oxide-nitride-oxide layer, ONO layer) or a combination of the foregoing, and may Use any suitable deposition method to form the first dielectric layer 114, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (plasma enhanced CVD, PECVD), atomic layer deposition (ALD), sputtering, or a combination of the foregoing.

Next, a second electrode plate material layer 126 is formed on the first dielectric layer 114. The second electrode plate material layer 126 includes a second metal layer 120 and a second anti-reflection coating 122 on the second metal layer 120. Then, a second dielectric layer 124 is formed on the second electrode plate material layer 126. In some embodiments, the materials and forming methods of the second metal layer 120, the second anti-reflective coating 122, and the second dielectric layer 124 may be the same as the aforementioned first metal layer 110, the first anti-reflective coating 112, and the first The material and forming method of the dielectric layer 114 are the same or similar. In one embodiment, the second metal layer 120 includes an aluminum-copper alloy and has a thickness ranging from about 100 angstrom to about 3000 angstrom. In one embodiment, the second anti-reflective coating 122 includes titanium nitride (TiN), and the second thickness T2 of the second anti-reflective coating 122 is in the range of about 100 angstroms to about 2000 angstroms.

Next, a third electrode plate material layer 136 is formed on the second dielectric layer 124. The third electrode plate material layer 136 includes a third metal layer 130 and a third anti-reflective coating 132 on the third metal layer 130. In some embodiments, the materials and forming methods of the third metal layer 130 and the third anti-reflective coating 132 may be the same as or similar to the foregoing materials and forming methods of the first metal layer 110 and the first anti-reflective coating 112. In one embodiment, the third electrode plate material layer 136 includes an aluminum-copper alloy and has a thickness in the range of about 100 angstroms to about 3000 angstroms. In one embodiment, the third anti-reflective coating 132 includes titanium nitride (TiN), and the third thickness T3 of the third anti-reflective coating 132 is in the range of about 100 angstroms to about 2000 angstroms.

The first anti-reflective coating 112 of the first electrode plate material layer 116 has a first thickness T1, the second anti-reflective coating 122 of the second electrode plate material layer 126 has a second thickness T2, and the third electrode plate material layer 136 The third anti-reflective coating 132 has a third thickness T3. In some embodiments, the first thickness T1, the second thickness T2, and the third thickness T3 may be the same. In other embodiments, the first thickness T1, the second thickness T2, and the third thickness T3 may be different.

With continued reference to FIG. 1, a first etch stop layer 140 is formed on the third electrode plate material layer 136. In some embodiments, the material of the first etch stop layer 140 may be or include silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), similar materials, the aforementioned multiple layers (for example, silicon oxide -A silicon nitride layer, an ON layer) or a combination of the foregoing, and any suitable deposition method may be used to form the first etch stop layer 140, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma Enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or sputtering.

Then, a first patterning process 170 is performed on the first etch stop layer 140, the third anti-reflective coating 132, and the third metal layer 130. As shown in FIG. 1B, after the first patterning process 170, a patterned first etch stop layer 140', a third anti-reflective coating 132' and a third metal layer 130' are formed, and part of the exposed Second dielectric layer 124. After the first patterning process 170, the combination of the third metal layer 130' and the third anti-reflective coating 132' serves as the third electrode plate 136'.

In some embodiments, the step of the first patterning process 170 may include forming a patterned photoresist layer (not shown) on the first etch stop layer 140 shown in FIG. 1A through a photolithography process, by The patterned photoresist layer performs an etching process on the first etch stop layer 140, the third anti-reflective coating 132, and the third metal layer 130, such as dry etching or wet etching, to remove the first etch stop layer 140, the third resist The portions of the reflective coating 132 and the third metal layer 130 that are not covered by the patterned photoresist layer, and the second dielectric layer 124 is exposed. Subsequently, the patterned photoresist layer on the first etch stop layer 140' is removed. In some embodiments, the etching process of the first patterning process 170 may be an etching process to etch all material layers. In other embodiments, the etching process of the first patterning process 170 may be multiple etching processes for individual material layers. In addition, in some embodiments, since the etching process of the first patterning process 170 uses the second dielectric layer 124 as an etch stop layer, the second dielectric layer 124 may be slightly etched.

Referring to FIG. 1C, a second etch stop layer 142 is formed on the structure shown in FIG. 1B. The second etch stop layer 142 is conformally formed on the exposed upper surface of the second dielectric layer 124, the third electrode plate 136' (including the third metal layer 130' and the third anti-reflective coating 132 ') on the sidewalls, and on the sidewalls and upper surface of the first etch stop layer 140'. The second etch stop layer 142 has a first horizontal portion on the exposed upper surface of the second dielectric layer 124, a second horizontal portion on the upper surface of the first etch stop layer 140', and a third electrode The vertical portion on the side wall of the plate 136' and the first etch stop layer 140'. In some embodiments, the thickness of the first horizontal portion of the second etch stop layer 142 is about 0.3 to about 1.0, such as 0.5, and the thickness of the vertical portion of the second etch stop layer 142 is the second The thickness of the horizontal portion is about 0.5 to about 0.9, for example 0.7. In some embodiments, the material and forming method of the second etch stop layer 142 may be the same as or similar to the material and forming method of the aforementioned first etch stop layer 140.

Then, a second patterning process 175 is performed on the second etch stop layer 142, the second dielectric layer 124, the second anti-reflective coating 122, and the second metal layer 120. As shown in FIG. 1D, after the second patterning process 175, a patterned second etch stop layer 142', a second capacitor dielectric layer 124', a second anti-reflective coating 122' and a second metal layer are formed 120', and a part of the first dielectric layer 114 is exposed. After the second patterning process 175, the combination of the second metal layer 120' and the second anti-reflective coating 122' serves as the second electrode plate 126', and part of the second capacitive dielectric layer 124' and the second electrode plate 126' extends beyond the third electrode plate 136' to form a step. In some embodiments, the second patterning process 175 may be similar to the first patterning process 170 described above in FIG. 1A.

Then, a third patterning process 180 is performed on the first dielectric layer 114, the first anti-reflective coating 112, and the first metal layer 110. As shown in FIG. 1E, after the third patterning process 180, a patterned first capacitive dielectric layer 114', a first anti-reflective coating 112' and a first metal layer 110' are formed, and the substrate 102 is exposed (Or the uppermost interlayer dielectric layer of the substrate 102). After the third patterning process 180, the combination of the first metal layer 110' and the first anti-reflective coating 112' serves as the first electrode plate 116', and part of the first capacitive dielectric layer 114' and the first electrode plate 116' extends beyond the second electrode plate 126' to form a step. The third patterning process 180 may be similar to the first patterning process 170 described above in FIG. 1A.

As shown in FIG. 1E, the combination of the first etch stop layer 140' and the second etch stop layer 142' may be referred to as an etch stop layer 143. The etch stop layer 143 has a first horizontal portion on a portion of the second electrode plate 126' extending beyond the third electrode plate 136', and a second horizontal portion on the third electrode plate 136'. The fourth thickness T4 of the first horizontal portion of the etch stop layer 143 is smaller than the fifth thickness T5 of the second horizontal portion. For example, the fifth thickness T5 is in the range of about 1.0 to 5 for the fourth thickness T4, for example, about 1.5. In the embodiment shown in FIG. 1E, no etch stop layer is formed on the first electrode plate 116'.

Referring to FIG. 1F, an interlayer dielectric layer 144 is formed on the substrate 102. The interlayer dielectric layer 144 covers the etch stop layer 143, the third electrode plate 136', the second capacitor dielectric layer 124', the second electrode plate 126', the first capacitor dielectric layer 114' and the first electrode plate 116'. In some embodiments, the material of the interlayer dielectric layer 144 may be or include silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC) , Silicon nitride carbide (SiCN), similar materials, the foregoing multiple layers or combinations of the foregoing, and any suitable deposition method can be used to form the interlayer dielectric layer 144, such as physical vapor deposition (PVD), chemical vapor deposition (CVD ), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering or a combination of the foregoing.

In some embodiments, in the subsequent etching process for forming the openings 146, 148, and 150 (shown in FIG. 1G), the etch stop layer 143 has a higher etch selectivity than the interlayer dielectric layer 144, that is, for the same Of the etchant, the etch stop layer 143 has an etch rate lower than that of the interlayer dielectric layer 144. For example, the etching selection ratio of the first etch stop layer 140 to the interlayer dielectric layer 144 is about 3 to about 10. In some embodiments, in the subsequent etching process for forming the openings 146, 148, and 150 (shown in FIG. 1G), the capacitive dielectric layers 114' and 124' have similar etch selectivity as the interlayer dielectric layer 144.

Next, a fourth patterning process 185 is performed on the interlayer dielectric layer 144. After the fourth patterning process 185, as shown in FIG. 1G, a first opening 146, a second opening 148, and a third opening 150 are formed. The first opening 146 passes through the interlayer dielectric layer 144 and the first capacitive dielectric layer 114' until the portion where the first electrode plate 116' extends beyond the second electrode plate 126' is exposed. The second opening 148 passes through the interlayer dielectric layer 144, the etch stop layer 143, and the second capacitive dielectric layer 124' until the portion where the second electrode plate 126' extends beyond the third electrode plate 136' is exposed. The third opening 150 passes through the interlayer dielectric layer 144 and the etch stop layer 143 until the third electrode plate 136' is exposed.

In some embodiments, the step of the fourth patterning process 185 may include forming a patterned photoresist layer (not shown) on the interlayer dielectric layer 144 through the photolithography process, and interposing the interlayer through the opening of the patterned photoresist layer The electrical layer 144 performs an etching process, such as dry etching or wet etching, to remove portions of the interlayer dielectric layer 144 that are not covered by the patterned photoresist layer to form the first opening 146, the second opening 148, and the third opening 150. In some embodiments, the etching process of the patterning process is anisotropic dry etching, for example, reactive ion etch (RIE), neutron beam etch (NBE), or the like Process or a combination of the foregoing, and using an etching gas including CF ₄ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, C ₄ F ₈ , C ₅ F ₈ , NF ₃ , SF ₆ or a combination of the foregoing. In some embodiments, the etching process of the patterning process is a wet etching process, for example, using dilute hydrofluoric acid (dHF). During the etching process of the patterning process, the first opening 146 passes through the first capacitive dielectric layer 114' and further extends into the first electrode plate 116'. The second opening 148 passes through the first horizontal portion of the etch stop layer 143 and the second capacitive dielectric layer 124', and further extends into the second metal plate 126'. The third opening 150 passes through the second horizontal portion of the etch stop layer 143 and further extends into the third metal plate 136'. Subsequently, the patterned photoresist layer on the interlayer dielectric layer 144 is removed, for example, through an ashing process. In some embodiments, openings 146, 148, and 150 may stop at antireflective coatings 112', 122', and 132', respectively. In other embodiments, the formed openings 146, 148, and 150 may stop at the metal layers 110', 120', and 130', respectively, and the metal layers 110', 120', and 130' are not etched through.

In the embodiment of the present invention, the first opening 146, the second opening 148, and the third opening 150 are simultaneously formed in the etching step of the fourth patterning process 185. Since the first electrode plate 116', the second electrode plate 126', and the third electrode plate 136' are at different levels (or horizontal levels), without forming the etch stop layer 143, when the first opening 146 extends to When in the first electrode plate 116', the third opening 150 and the second opening 148 may have penetrated the third electrode plate 136' and the second electrode plate 126', respectively.

In the embodiment of the present invention, the thickness of the etch stop layer 143 on the electrode plates 116', 126', and 136' changes from zero (eg, the etch stop layer 143 is not formed on the first electrode plate 116') The level increases. For example, the fifth thickness T5 of the etch stop layer 143 on the third electrode plate 136' is the fourth thickness T4 on the second electrode plate 126', for example, in the range of about 1.0 to 5, for example, about 1.5. Therefore, under the same etching time, the difference in the etching depth of the first opening 146, the second opening 148, and the third opening 150 can be compensated by the difference in the thickness of the etching stop layer 143 on the respective electrode plates. By adjusting the thicknesses of the first etch stop layer 140 and the second etch stop layer 142, the first opening 146, the second opening 148, and the third opening 150 can be simultaneously extended into the corresponding electrode plates 116', 126', and 136', The electrode plates 116', 126' and 136' are not eroded through.

Please refer to FIG. 1H, a first guide hole 152, a second guide hole 154, and a third guide hole 156 are formed in the first opening 146, the second opening 148, and the third opening 150, respectively. The first guide hole 152, the second guide hole 154, and the third guide hole 156 fill the first opening 146, the second opening 148, and the third opening 150, and respectively contact the first electrode plate 116' and the second electrode plate 126' And the third electrode plate 136'. In some embodiments, the materials of the first via hole 152, the second via hole 154, and the third via hole 156 may be or include aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), rhodium (rh), molybdenum (Mo), nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), similar materials, the foregoing alloys or combinations of the foregoing, and form the first guide The steps of the hole 152, the second via hole 154, and the third via hole 156 may include depositing a metal material layer (not shown) on the interlayer dielectric layer 144, and filling the first opening 146, the second opening 148, and the third opening 150. After that, a portion of the metal material layer above the interlayer dielectric layer 144 is removed through a planarization process such as chemical mechanical polish (CMP) to expose the upper surface of the interlayer dielectric layer 144.

With continued reference to FIG. 1H, a first terminal 158 and a second terminal are formed on the upper surface of the interlayer dielectric layer 144 and corresponding to the first via 152, the second via 154, and the third via 156 160 and the third endpoint 162. The first terminal 158, the second terminal 160, and the third terminal 162 are electrically connected to the first electrode plate 116' and the second electrode through the first guide hole 152, the second guide hole 154, and the third guide hole 156, respectively Plate 126' and third electrode plate 136'. After forming the first terminal 158, the second terminal 160, and the third terminal 162, the capacitor structure 100 is formed.

In some embodiments, the materials of the first terminal 158, the second terminal 160, and the third terminal 162 may be or include aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), rhodium (rh), molybdenum (Mo), nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), similar materials, the foregoing alloys or combinations of the foregoing, and form the first end The steps of the point 158, the second terminal 160, and the third terminal 162 may include depositing a metal material layer (not shown) on the interlayer dielectric layer 144, and patterning the metal material layer to form the corresponding first via 152 , The first end point 158, the second end point 160, and the third end point 162 of the second guide hole 154 and the third guide hole 156. In other embodiments, after forming the metal material layer for the first via hole 152, the second via hole 154, and the third via hole 156, without planarizing the metal material layer, The portion above the interlayer dielectric layer 144 is patterned to form a first terminal 158, a second terminal 160, and a third terminal 162.

In some embodiments, when the operating voltage is applied to the first terminal 158 and the second terminal 160, the first metal plate 116', the first capacitor structure 114', and the second electrode plate 126' form a first capacitor. In some embodiments, when the operating voltage is applied to the second terminal 160 and the third terminal 162, the second metal plate 126', the second capacitor structure 124', and the third electrode plate 136' form a second capacitor. In some embodiments, when the operating voltage is applied to the second terminal 160 and a common voltage is applied to the first terminal 158 and the third terminal 162, the first capacitor and the second capacitor are connected in parallel to form A third capacitor having a higher capacitance value than the first capacitor and the second capacitor.

In the embodiment of the present invention, the capacitor structure 100 includes a first electrode plate 116 ′, a first capacitor dielectric layer 114 ′, a second electrode plate 126 ′, and a second capacitor dielectric layer 124 ′ sequentially stacked on the substrate 102. And the third electrode plate 136'. A portion of the first electrode plate 116' extends beyond one end of the second electrode plate 126' to form a step, and a portion of the second electrode plate 126' extends beyond one end of the third electrode plate 136' to form Another ladder.

The first electrode plate 116' includes a first metal layer 110' and a first anti-reflection coating 112', the second electrode plate 126' includes a second metal layer 120' and a second anti-reflection coating 122', and a third electrode plate 136' includes a third metal layer 130' and a third anti-reflective coating 132'. In some embodiments, the first thickness T1 of the first anti-reflective coating 112', the second thickness T2 of the second anti-reflective coating 122', and the second thickness T3 of the third reflective coating 132' may be the same . In another embodiment, the first thickness T1 of the first anti-reflective coating 112', the second thickness T2 of the second anti-reflective coating 122', and the second thickness T3 of the third reflective coating 132' may be different of.

The capacitor structure 100 further includes an etch stop layer 143. The etch stop layer 143 has a first horizontal portion provided above the portion of the second electrode plate 126' extending beyond one end of the third electrode plate 136', and has a second horizontal portion provided above the third electrode plate 136' . The second horizontal portion of the etch stop layer 143 contains the first etch stop layer 140' and the second etch stop layer 142', and has a fifth thickness T5. The first horizontal portion of the etch stop layer 143 contains the second etch stop layer 142' and has a fourth thickness T4, where the fourth thickness T4 is smaller than the fifth thickness T5. In some embodiments, no etch stop layer is provided on the first electrode plate 116'.

The capacitor structure 100 further includes an interlayer dielectric layer 144, and a first via hole 152, a second via hole 154, and a third via contacting the first electrode plate 116', the second electrode plate 126', and the third electrode plate 136', respectively孔156. The first via hole 152 passes through the interlayer dielectric layer 144 and the first capacitive dielectric layer 114' to contact a portion of the first electrode plate 116' extending beyond the second metal plate 126'. The second via hole 154 passes through the interlayer dielectric layer 144, the etch stop layer 143, and the second capacitive dielectric layer 124' to contact a portion of the second electrode plate 126' extending beyond the third electrode plate 136'. The third via hole 156 passes through the interlayer dielectric layer 144 and the etch stop layer 143 to contact the third electrode plate 136'.

The embodiments of the present invention utilize the adjustment of the thickness of the etch stop layer on the electrode plate, and these thicknesses increase as the level of the electrode plate increases, so that under the same etching time, the difference in etching depth can pass through the etch stop layer at the level The difference in thickness is compensated. Therefore, the embodiments of the present invention can form a plurality of via holes of different depths and corresponding electrode plates through a single etching process, which can greatly reduce the manufacturing time and cost of the capacitor structure.

Although in the embodiment shown in FIG. 1H, the capacitor structure 100 has three layers of electrode plates 116', 126, and 136', however, the ideas of the embodiments of the present invention can be applied to electrode plates having different levels, for example, two layers Or more than three layers, so as to form a plurality of via holes of different depths to the corresponding electrode plates in one patterning process. For example, as shown in FIG. 1I, the capacitor structure 100' has five electrode plates 116L1 to 116L5, and the thickness of the etch stop layer 143 on the respective electrode plates 116L1 to 116L5 is from zero (for example, the etch stop layer 143 is not formed On the first electrode plate 116L1), the level of the electrode plate increases (for example, from the electrode plate 116L1 to the electrode plate 116L5). For example, starting from the second electrode plate, the thickness of the etch stop layer 143 on the electrode plate of the layer is in the range of about 1.2 to 5, for example, about 1.8 on the front electrode plate. Therefore, by adjusting the thickness of the first etch stop layer 143 on the respective electrode plates, the openings 146L1 to 146L5 can be simultaneously extended into the corresponding electrode plates 116L1 to 116L5 without eroding the electrode plates.

FIG. 2 is a schematic cross-sectional view showing a capacitor structure 200 according to other embodiments of the present invention, wherein the same components as those in the foregoing embodiments of FIGS. 1A-1H use the same reference numerals and their descriptions are omitted. The difference between the embodiment shown in FIG. 2 and the aforementioned embodiment of FIG. 1H is that the third electrode plate 136' of the capacitor structure 200 of FIG. 2 is composed of a third anti-reflection coating 132'.

In some embodiments, the material of the third anti-reflective coating 132' of the third electrode plate 136' is a conductive metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or similar metals nitride. Therefore, in the embodiment shown in FIG. 2, the third electrode plate 136 ′ may not include a metal layer (for example, the third metal layer 130 ′ in FIG. 1H ), and only include the third anti-reflection coating 132 ′ . Without the formation of the third metal layer 130', the overall thickness of the capacitor structure 200 can be reduced, which helps to reduce the difficulty and complexity of integrating the capacitor structure 200 into the metal oxide semiconductor (CMOS) front-end (FEOL) process degree.

FIG. 3 is a schematic cross-sectional view showing the capacitor structure 300 according to some other embodiments of the present invention, wherein the same reference numerals are used for the components that are the same as those in the foregoing embodiments of FIGS. 1A-1H and their descriptions are omitted. The difference between the embodiment shown in FIG. 3 and the aforementioned embodiment of FIG. 1H is that the etch stop layer 143 of the capacitor structure 300 of FIG. 3 is composed of a second etch stop layer 142 ′ and a third anti-reflective coating 132 The third thickness T3 of 'is greater than the second thickness T2 of the second anti-reflective coating 132' and the first thickness T1 of the first anti-reflective coating 112'.

In the etching process for forming the openings 146, 148, and 150, the third anti-reflective coating 132' has a higher etching selectivity relative to the interlayer dielectric layer 144, for example, the third anti-reflective coating 132' and the interlayer dielectric The etching selection ratio of the layer 144 is about 3 to about 10, so the anti-reflective coating 132' can also be used as an etch stop layer. Therefore, in the embodiment shown in FIG. 3, the first etch stop layer 140' as shown in FIG. 1H may not be formed, and the etch stop layer 143 is composed of only the second etch stop layer 142'. The third thickness T3 forming the third antireflection coating 132' is greater than the second thickness T2 of the second antireflection coating 132' and the first thickness T1 of the first antireflection coating 112'. For example, the third thickness T3 is the second thickness T2 and/or the first thickness T1 is about 1 to 2.5, such as about 1.8. Therefore, under the same etching time, the difference in the etching depth of the third opening 150 and the first opening 146 and the second opening 148 can be compensated by the increased third thickness T3 of the third anti-reflective coating 132'. Therefore, by adjusting the thickness T3 of the third anti-reflective coating 132', the first opening 146, the second opening 148, and the third opening 150 can be simultaneously extended into the corresponding electrode plates 116', 126', and 136' without The electrode plate will be eroded through.

FIG. 4 is a schematic cross-sectional view showing a capacitor structure 400 according to some other embodiments of the present invention, wherein components that are the same as those in the foregoing embodiments of FIGS. 1A-1H use the same reference numerals and their descriptions are omitted. The difference between the embodiment shown in FIG. 4 and the aforementioned embodiment of FIG. 1H is that the capacitor structure 400 of FIG. 4 does not include the stop stop layer 143 shown in FIG. 1H and the third anti-reflective coating 132 The third thickness T3 of 'is greater than the second thickness T2 of the second anti-reflective coating 132', and the second thickness T2 of the second anti-reflective coating 132' is greater than the first thickness T1 of the first anti-reflective coating 112'.

As described above, in the etching process for forming the openings 146, 148, and 150, the anti-reflective coatings 112', 122', and 132' have a higher etching selectivity relative to the interlayer dielectric layer 144, for example, anti-reflective coating The etching selection ratio of the layers 112', 122', and 132' to the interlayer dielectric layer 144 is about 3 to about 10, so the anti-reflective coatings 112', 122', and 132' can also serve as etching stop layers. Therefore, in the embodiment shown in FIG. 4, the etch stop layer 143 shown in FIG. 1H may not be formed, and the etch stop layer 143 is composed of only the second etch stop layer 142'. The third thickness T3 of the third anti-reflection layer 132' is greater than the second thickness T2 of the second anti-reflection coating 122', and the second thickness T2 of the second anti-reflection coating 122' is greater than the first anti-reflection coating 112' The first thickness T1. For example, the third thickness T3 is about 1 to 2.5, such as about 1.8, for the second thickness T2. For example, the second thickness T2 is about 1 to 2.5, such as about 1.8, for the first thickness T. Therefore, under the same etching time, the difference in the etching depth of the first opening 146, the second opening 148, and the third opening 150 can be compensated by the thickness difference of the anti-reflection coatings 112', 122', and 132'. Therefore, by adjusting the thicknesses T1, T2, and T3 of the antireflection coatings 112', 122', and 132', the first opening 146, the second opening 148, and the third opening 150 can be simultaneously extended to the corresponding electrode plates 116', 126 'And 136' without eroding through the electrode plate.

FIG. 5 is a schematic cross-sectional view showing a capacitor structure 500 according to some other embodiments of the present invention, wherein components that are the same as those in the foregoing embodiments of FIGS. 1A-1H use the same reference numerals and their descriptions are omitted. The difference between the embodiment shown in FIG. 5 and the aforementioned embodiment of FIG. 4 is that the third electrode plate 136' of the capacitor structure 500 of FIG. 5 is composed of a third anti-reflection coating 132'.

As described above, the material of the third anti-reflective coating 132' of the third electrode plate 136' is a metal nitride having conductivity. Therefore, in the embodiment shown in FIG. 5, the third electrode plate 136 ′ may not include a metal layer (for example, the third metal layer 130 ′ in FIG. 4 ), and only include the third anti-reflection coating 132 ′ . Without the formation of the third metal layer 130', the overall thickness of the capacitor structure 500 can be reduced, which helps reduce the difficulty and complexity of integrating the capacitor structure 500 into the front-end (FEOL) process of the metal oxide semiconductor (CMOS) degree.

FIG. 6 is a schematic cross-sectional view showing a capacitor structure 600 according to other embodiments of the present invention, wherein the same components as those in the foregoing embodiments of FIGS. 1A-1H use the same reference numerals and their descriptions are omitted. The difference between the embodiment shown in FIG. 6 and the foregoing embodiment of FIG. 4 is that the first electrode plate 116' of the capacitor structure 600 of FIG. 6 is composed of a first anti-reflection coating 112', and the second electrode plate 126 'Composed of the second anti-reflective coating 122', and the third electrode plate 136' is composed of the third anti-reflective coating 132'.

As mentioned above, the material of the anti-reflective coatings 112', 122, and 132' is conductive metal nitride. Therefore, the electrode plates 116', 126', and 136' may not include metal layers (for example, the metal layers 110', 120', and 130' in FIG. 4), and only include anti-reflection coatings 112', 122', and 132'. Without forming the first metal layer 110', the second metal layer 120', and the third metal layer 130', the overall thickness of the capacitor structure 600 can be reduced, which helps reduce the integration of the capacitor structure 600 into the metal oxide semiconductor ( CMOS) Front-end (FEOL) process is difficult and complicated.

In summary, the embodiments of the present invention adjust the thickness of the etch stop layer on the electrode plate and/or the anti-reflective coating of the electrode plate. These thicknesses increase as the level of the electrode plate increases, so that at the same etching time Under conditions, the difference in etch depth can be compensated by the difference in thickness between the etch stop layer and/or the anti-reflective coating. Therefore, the embodiments of the present invention can form a plurality of via holes with different depths to the corresponding electrode plates through one etching process, which can greatly reduce the manufacturing time and cost of the capacitor structure.

The above summarizes several embodiments so that those with ordinary knowledge in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention, Make various changes, substitutions and replacements.

100‧‧‧Capacitive structure

102‧‧‧ base

110’‧‧‧ First metal layer

112’‧‧‧The first anti-reflective coating

114’‧‧‧ First Capacitor Dielectric Layer

116’‧‧‧First electrode plate

120’‧‧‧Second metal layer

122’‧‧‧Second anti-reflective coating

124’‧‧‧Second capacitor dielectric layer

126’‧‧‧Second Electrode Plate

130’‧‧‧third metal layer

132’‧‧‧third anti-reflective coating

136’‧‧‧third electrode plate

140’‧‧‧ First etch stop layer

142’‧‧‧Second etching stop layer

143‧‧‧Etching stop layer

144‧‧‧Interlayer dielectric layer

146‧‧‧First opening

148‧‧‧Second opening

150‧‧‧ third opening

152‧‧‧First pilot hole

154‧‧‧Second pilot hole

156‧‧‧third guide hole

158‧‧‧First endpoint

160‧‧‧The second endpoint

162‧‧‧The third endpoint

T4‧‧‧thickness

T5‧‧‧ fifth thickness

Claims (20)

A capacitor structure includes: a first electrode plate disposed on a substrate; a first capacitor dielectric layer disposed on the first electrode plate; and a second electrode plate disposed on the first capacitor dielectric layer On which a part of the first electrode plate extends beyond one end of the second electrode plate to form a step; an etch stop layer is provided on the second electrode plate; an intermetal dielectric layer covers the An etch stop layer, the second electrode plate, the first capacitor dielectric layer and the first electrode plate; a first via hole passing through the intermetal dielectric layer to contact the first electrode plate to extend beyond the The portion of the second electrode plate; and a second via hole passing through the intermetal dielectric layer and the etch stop layer to contact the second electrode plate. The capacitor structure as described in item 1 of the patent application scope further includes: a second capacitor dielectric layer disposed on the second electrode plate; and a third electrode plate disposed on the second capacitor dielectric layer; Wherein a part of the second electrode plate extends beyond one end of the third electrode plate to form another step; wherein a first part of the etch stop layer is disposed on the second electrode plate extending beyond the third electrode plate On this portion, a second portion of the etch stop layer is provided on the third electrode plate, and the thickness of the first portion of the etch stop layer is less than the thickness of the second portion of the etch stop layer; wherein the second A via hole passes through the first portion of the etch stop layer to contact the second electrode plate; and a third via hole passes through the intermetal dielectric layer and the second portion of the etch stop layer to Contact the third electrode plate. The capacitor structure as described in item 2 of the patent application scope, wherein the first part of the etch stop layer comprises: a first etch stop layer, and the second part of the etch stop layer comprises: the first etch stop layer and A second etch stop layer on the first etch stop layer. The capacitor structure as described in item 1 of the patent application scope, wherein the material of the etch stop layer is silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing. The capacitor structure as described in item 1 of the patent application scope, wherein the first electrode plate comprises: a first metal layer and a first anti-reflection coating on the first metal layer; wherein the second electrode plate comprises : A second metal layer and a second anti-reflection coating on the second metal layer. The capacitor structure as described in item 5 of the patent application range, wherein the materials of the first reflective layer and the second reflective layer are metal nitrides. The capacitor structure as described in item 1 of the patent application range, wherein the thickness of the second anti-reflection coating is equal to or greater than the thickness of the first anti-reflection coating. The capacitor structure as described in item 1 of the patent application scope, wherein the first electrode plate comprises: a first metal layer and a first anti-reflection coating; wherein the second electrode plate is composed of a second anti-reflection coating . A capacitor structure includes: a first electrode plate disposed on a substrate, the first electrode plate including: a first anti-reflection coating; a first capacitor dielectric layer disposed on the first electrode plate; A second electrode plate is disposed on the first capacitor dielectric layer, wherein a portion of the first electrode plate extends beyond one end of the second electrode plate to form a step, and the second electrode plate includes: A second anti-reflective coating, the thickness of the second anti-reflective coating is greater than the thickness of the first anti-reflective coating; an inter-metal dielectric layer covering the second electrode plate, the first capacitor dielectric layer and The first electrode plate; a first guide hole passing through the intermetal dielectric layer to contact the portion of the first electrode plate extending beyond the second electrode plate; and a second guide hole passing through the An inter-metal dielectric layer to contact the second electrode plate. The capacitor structure as described in item 9 of the patent application scope further includes: an etch stop layer disposed on the portion of the first electrode plate extending beyond the second electrode plate and the second electrode plate, wherein the first The via hole and the second via hole further pass through the etch stop layer. The capacitor structure as described in item 9 of the patent application scope further includes: a second capacitor dielectric layer disposed on the second electrode plate; and a third electrode plate disposed on the second capacitor dielectric layer , Wherein a part of the second electrode plate extends beyond one end of the third electrode plate to form another step, and wherein the third electrode plate includes: a third anti-reflection coating, wherein the third anti-reflection The thickness of the coating is greater than the thickness of the second anti-reflective coating; and a third via hole passing through the intermetal dielectric layer to contact the third electrode plate, wherein the second via hole contacts the second electrode The plate extends beyond the portion of the third electrode plate. The capacitor structure as described in item 9 of the patent application scope, wherein the first electrode plate further comprises: a first metal layer, the first anti-reflective coating is disposed on the first metal layer; wherein the second electrode plate It further includes: a second metal layer, the second anti-reflective coating is disposed on the second metal layer. The capacitor structure as described in item 9 of the patent application scope, wherein the first electrode plate further comprises: a first metal layer, the first anti-reflective coating is disposed on the first metal layer; wherein the second electrode plate Consists of this second anti-reflective coating. The capacitor structure as described in item 9 of the patent application range, wherein the first electrode plate is composed of the first anti-reflection coating, and the second electrode plate is composed of the second anti-reflection coating. A method for manufacturing a capacitor structure includes: sequentially forming a first electrode plate material layer, a first dielectric layer, a second electrode plate material layer and a first etch stop layer on a substrate; Patterning the etch stop layer and the second electrode plate material layer to form a patterned first etch stop layer and a second electrode plate, respectively; patterning the first dielectric layer and the first electrode plate material layer, To form a first capacitor dielectric layer and a first electrode plate, wherein a part of the first electrode plate extends beyond one end of the second electrode plate to form a step; an intermetallic layer is formed on the substrate A dielectric layer to cover the patterned first etch stop layer, the second electrode plate, the first capacitor dielectric layer and the first electrode plate; forming a first opening through the intermetal dielectric layer until Exposing the portion of the first electrode plate extending beyond the second electrode plate; forming a second opening through the intermetal dielectric layer and the patterned first etch stop layer until the second electrode plate is exposed; And forming a first guide hole in the first opening and a second guide hole in the second opening. The method for manufacturing a capacitor structure as described in item 15 of the patent application range, wherein the first opening and the second opening are formed in the same etching process. The method for manufacturing a capacitor structure as described in item 15 of the patent application scope, after forming the second electrode plate material layer and before forming the first etch stop layer, further includes: on the second electrode plate material layer Sequentially forming a second dielectric layer, a third electrode plate material layer and a second etch stop layer; and patterning the second etch stop layer, the third electrode plate material layer and the second dielectric layer To form a patterned second etch stop layer, a third electrode plate and a second capacitor dielectric layer; wherein a part of the second electrode plate extends beyond one end of the third electrode plate to form another A step; wherein the step of forming the first etch stop layer further includes the first etch stop layer formed on the patterned second etch stop layer; wherein the second opening exposes the second electrode plate extending beyond the third This part of the electrode plate. The method for manufacturing a capacitor structure as described in item 17 of the patent application scope further includes: forming a third opening through the intermetal dielectric layer, the patterned first etch stop layer and the patterned second etch stop layer Until the third electrode plate is exposed, wherein the first opening, the second opening, and the third opening are formed in the same etching process; and a third via hole is formed in the third opening. The method for manufacturing a capacitor structure as recited in item 15 of the patent application range, wherein the first electrode plate material layer includes: a first metal layer and a first anti-reflection coating on the first metal layer; wherein the The second electrode plate material layer includes: a second metal layer and a second anti-reflection coating on the second metal layer, and the thickness of the second anti-reflection coating is equal to or greater than that of the first anti-reflection coating thickness of. The method for manufacturing a capacitor structure as described in item 15 of the patent application scope, wherein the first electrode plate includes: a first metal layer and a first anti-reflection coating on the first metal layer; wherein the second The electrode plate is composed of a second anti-reflective coating.

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