TWI489529B - Integrated circuit capacitor and method - Google Patents

Description

Integrated circuit capacitor and method

The present invention relates to a capacitor technology, and more particularly to a capacitor for use in an integrated circuit and a method of fabricating the same.

A capacitor is an electronic device in which a layer of insulating material is sandwiched between two electrodes. When there is a voltage difference between the two electrodes, an electric field is generated between the two electrodes so that electrical energy can be stored. When a given voltage is passed through the two electrodes, the electrical energy that can be stored in the capacitor is often referred to as its capacitance value. The electrodes are typically flat plates of different shapes, contours and sizes. The capacitance value is usually the dielectric constant of this dielectric layer Correlation, and proportional to the area of the opposing electrode, inversely proportional to the distance between the electrodes. Connecting two or more capacitors in parallel with their overall capacitance value is the sum of the individual capacitance values. Connecting two or more capacitors in series will have an overall capacitance value that is less than any of the individual capacitor values. Series capacitors are typically used in high voltage situations because high voltages are split by these capacitors. Providing many different sized capacitors outside of the integrated circuit is generally not a problem, but conventional integrated circuits can only provide relatively small capacitors due to their size limitations. See, for example, U.S. Patent No. 5,497,016.

An example of a capacitor includes a series of ridges and trenches, an interconnected region, a curved stacked plate capacitor member, and an electrical connector. The series of ridges and ditches and an interconnecting region are on a substrate. The series of ridges and ditches and the interconnecting region have a capacitor base surface having a curved cross-sectional profile over the series of ridges and ditches. This curved stack is flat A plate capacitor component comprising at least two electrically conductive electrode layers and a dielectric layer separating the electrode layers, a stack of one or more capacitors being produced at the capacitor base surface. The electrical connector electrically connects the electrode layer from the interconnect region to access the electrode layer of the capacitor member. Some examples of such capacitors may include one or more of the following technical features: The capacitor base surface is electrically conductive and constitutes an electrode layer. The interconnected area is separated from the series of ridges and ditches. The interconnected area is in at least one of the ridge or ditch. The electrical conductor passes through a vertical via hole in the interconnect region, and the vertical via hole is over the contact pad of the electrode layer, and the electrical conductor is electrically connected to the contact pad. Each of the electrical conductors is electrically connected to a contact pad of the electrode layer, and the contact pads electrically connected to the electrical conductor are arranged in a stepwise electrical connection. The ridge of the series is located above the substrate and extends away from the substrate. The ridge of the series is located in a trench of the substrate.

An example of a method of forming a capacitor can be performed by forming a series of ridges on a substrate that is separated by a trench. An interconnected region is also formed on the substrate adjacent to the series of ridges and ditches. The series of ridges and ditches and interconnected areas have a capacitor base surface. The ridge forming step is performed such that the capacitor base surface has convex and concave structures to define a curved cross-sectional profile. Forming a staggered electrically conductive electrode layer and a dielectric layer separates the electrode layer from the capacitor base surface to create a stack of at least two curved plate capacitors. The electrode layer and the electrical conductor are electrically connected to the interconnect region to access the electrode layer. Some examples of the method of forming a capacitor can include one or more of the following technical features: the ridge forming step includes forming the series of dielectric ridges in a trench on the substrate. The electrically connecting step includes: removing material from a portion of the interconnect region, the material coating a contact pad of the electrode layer; depositing a dielectric material on the portion of the interconnect region; forming a via hole through the interconnect And contacting the contact pad; and forming an electrical conductor in the via hole and electrically coupling the electrical conductor to the contact pad. The electrical connection step also includes creating a step arrangement of the contact pads to an electrical connection with the electrical conductor. The electrical connection step includes using a set of N etch masks to create contact pads of up to 2 ^N levels in the interconnect region, each mask including a mask and an etched region, N being an integer of at least 2, x Is the number of sequences of the mask starting from x=0 such that one mask x=0 and the other mask x=1 until x=n-1; using the mask to etch the interconnection area N times in a pre-selected order The contact opening is extended to each of the electrode layers; the etching step includes etching each of the masks of the sequence X through 2 ^N electrode layers. Each etch interactive screen cover hood covering the curtain 2 ^X 2 ^X region and the exposed region is etched so that x = 0 photoresist interactive screen cover ²⁰ covers the exposed contact pads and contact pads ^20, x = 1 covered with the photoresist ²¹ interactive screen cover Contact pads and bare 2 ¹ contact pads, and x=2 photoresist masks cover 2 ² contact pads and bare 2 ² contact pads. The staggered electrically conductive electrode layer and dielectric layer forming step form a stack of at least four curved plate capacitors. The dielectric ridge forming step is performed such that the ridge has a ridge height, a ridge width, and a trench width. The dielectric ridge forming step is performed such that the ratio of the average of the ridge height to the average of the ridge width is in the range of 3-20.

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments will be described in conjunction with the drawings in the sections of the following embodiments.

Certain embodiments of the invention are described in the following description of the embodiments of the invention, in which only some, but not all, embodiments are shown. However, the various embodiments of the present invention may have different types and should not be construed as limiting the present invention; rather, these embodiments are provided so that the disclosure of the present specification is full. The requirements of the patent law. Those skilled in the art will appreciate that many variations can be made in the spirit of the invention. Similar elements in different embodiments generally use similar reference numerals.

Capacitors are well known in the art as being very useful in electronic circuits, but their use in semiconductors can be very expensive and difficult to manufacture. Capacitors can be used to help reduce voltage variations and can be used to help store data in, for example, static random access memory, dynamic random access memory, flash memory, etc., either in normal operation or It is not expected to be used in the event of a power outage. While it is now possible to provide such a capacitor in the system class, it is desirable to provide a usable capacitor in the semiconductor class while accounting for system cost, voltage and reliability considerations.

Referring to FIG. 1, there is shown an integrated circuit capacitor 10 in accordance with an exemplary embodiment of the present invention. Such integrated circuit capacitor 10 is typically part of an integrated circuit. The integrated circuit capacitor 10 can provide an integrated circuit with a low cost and high density of capacitance. The integrated circuit capacitor 10 includes a substrate 12 having an upper portion of the substrate 12 having a ridge-like substrate surface 14 separated by trenches 15. The ridge 16 and the substrate surface 14 are typically constructed of the same material, which may also be constructed of different materials. In some examples, such as some of the examples in FIGS. 1-12, the ridge 16 is formed in the trench 15 of the upper half of the substrate 12 and in other examples the ridge 16 is formed in the upper half of the substrate 12. Above the ditch 15. In the example of Fig. 1, the ridge 16 and the upper half of the substrate 12 are made of the same material. For the sake of simplicity, the upper half of the substrate 12 is generally referred to herein simply as the substrate 12.

As will be described below, in other examples, the ridge 16 may be a semiconductor or conductor material and have some degree of isolation from the main portion of the integrated circuit below the upper half of the substrate 12 directly below it. In such an example, the ridge 16 and the upper half of the substrate 12 can serve as electrically conductive electrodes. Layer 20. Methods of forming ridges 16 include lithography-based etching processes and other techniques. The particular method of forming the ridge 16 separated by the trench 15 is determined by a number of different considerations, such as the materials used, the depth of the trench, the aspect ratio of the trench, and the like. One way to reduce the spacing between the trenches 15 is less than the minimum spacing of the lithography process is to use a double or quadruple patterning, sometimes referred to as multiple patterning. In this manner, typically a single reticle can be used to create a series of parallel material lines on the substrate. Different methods can then be used to convert the parallel material lines into multiple parallel material lines. Pan Xiao and Bruce W. Smith et al. disclose many different methods in their paper "Analysis of Higher-Order Pitch Division for Sub-32 nm Lithograph, Optical Microlithography XXII, Proc. of SPIE Vol. 7274, 72741Y, 2009. This multi-patterning method is also described in the U.S. Patent Application Serial No. 12/981,121, filed on Dec. 29, 2010, which is incorporated herein by reference.

As shown in FIG. 1, a stack 17 of curved plate capacitors 18 is formed over substrate 12 and dielectric ridges 16 have concave and convex portions following this curved path. The stack 17 has first and second curved plate capacitors 18, each of which includes a set of electrically conductive electrode layers 20 and having a dielectric layer 22 separating the electrode layers 20. In reality, for example four or eight curved plate capacitors 18 can be used. Further, for example, one thousand or more ridges 16 can be used. However, for the sake of simplicity, only two ridges and capacitors are shown in the figure. Stack 17 is covered by a dielectric fill layer 24.

In the examples of Figures 1-9, the ridge 16 and the upper half of the substrate 12 are dielectric materials. Since such materials have been widely used in the industry, it is preferable to use yttrium oxide as the ridge 16. Further, a low dielectric constant material such as tantalum nitride or another low dielectric constant material may also be used. In some examples, this capacitor structure uses what is referred to as a rough surface conductor such that the ridge 16 and the upper half of the substrate 12 can be constructed of a conductor and thus act as an electrically conductive electrode layer. Generally, the conductor can be a metal or a composite metal comprising aluminum, copper, tungsten, titanium, cobalt, and nickel. The conductor may also be a metal compound such as tantalum nitride, tantalum nitride, and aluminum copper or a semiconductor compound such as a heavily doped germanium (using impurities such as arsenic, phosphorus, boron, etc.); the telluride includes titanium telluride, cobalt telluride Wait. Further, typical dielectric materials are, for example, cerium oxide, cerium nitride, cerium oxynitride. However, it is preferable to have a high dielectric constant material having a dielectric constant larger than that of ruthenium oxide such as HfO _x , HfON, AlO _x , RuO _x , TiO _x . The dielectric material may also be a multilayer dielectric material such as hafnium oxide/tantalum nitride/anthracene oxide (ONO), hafnium oxide/high dielectric constant material/yttrium oxide (O/high k/O), which provides higher The dielectric constant and the leakage of the capacitor can be avoided.

2 is a three-dimensional schematic view of the structure showing dielectric ridges 16 extending outwardly from surface 14 of substrate 12 and separated by trenches 15. The ridge 16 has an upper wall surface 25 and a side wall surface 27. The ridges 16 are separated by a trench width 26 that extends in a first direction 28. The number of electrically conductive electrode layers 20 and dielectric layers 22 is primarily determined by the size of the trench width 26. The ridge 16 has a ridge width 30 that extends in the first direction 28 and a ridge height 32 that extends in the second direction 34. The ridge 16 has a ridge length 36 that extends in the third direction 38. First, the first direction 28, the second direction 34, and the third direction 38 are generally perpendicular to each other. When the integrated circuit capacitor 10 is formed in a trench, the ridge height 32 is typically equivalent to the depth of the trench. The ratio of the average ridge height 32 to the average ridge width 30 is preferably large, such as 100, to increase the capacitance value per unit area. Under current technology, the ratio of the average ridge height 32 to the average ridge width 30 is typically between 3 and 20. The trench width 26 must be twice the thickness of the stack 17 in Figure 1.

3 is a cross-sectional view showing the structure of FIG. 2 after the conformal deposited electrode layer 20 is over the upper wall surface 25 of the dielectric ridge 16 and the sidewall surface 27 and the exposed substrate surface 14. Electrode layer 20 is typically a metal or other electrically conductive material. 4 is a cross-sectional view showing the structure of FIG. 3 after the conformal deposition of the dielectric layer 22 over the electrode layer 20. According to the yield, the optimum average thickness of the electrode layer 20 is about 10 to 100 nm, and the optimum average thickness of the dielectric layer 22 is about 10 to 100 nm. According to the consideration of the leakage current of the dielectric layer 22 directly and the conduction of the electrode layer 20, the minimum thickness of each layer needs to be greater than 3 nm. The dielectric layer 22 must be thick enough to prevent the Fuller-Nordheim (FN) problem characterized by the following equation. V/t < 6 million volts/cm, where V is the operating voltage and t is the dielectric layer thickness. For example, if V = 3 volts, t > 3 V / (6 ^* 10 ^ 6 V / cm) = when the dielectric layer is yttrium oxide and the operating voltage is 3 volts, its thickness t > 5 nm.

A suitable deposition technique for the dielectric layer 22 is, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDCVD), low density plasma chemical vapor deposition (LDCVD), and the like. It is determined by the materials used. The process of depositing electrode layer 20 and dielectric layer 22 continues until a suitable number of curved plate capacitors 18 are produced. The size of the trench width 26 and the ratio of the trench width 26 to the ridge height 32 generally limits the number of electrode layers 20 and dielectric layers 22. The width of the trench 26 is typically greater than the width of the ridge 30.

Figure 5 shows a cross-sectional view of the structure of Figure 4 after deposition of four electrode layers 20 and four dielectric layers 22 to produce a stack 17 of two curved plate capacitors 18. Electrode layer 20 and dielectric layer 22 may continue with electrode layer extension 40 and dielectric layer extension 42 to an interconnect region 44 as shown. In this example, the electrode layer extension 40 and the dielectric layer extension 42 in the interconnect region 44 have the same height as the corresponding electrode layer 20 and dielectric layer 22 deposited on the upper wall surface 25 of the dielectric ridge 16. In other examples, such as when the dielectric ridge 16 is not formed within the trench, the electrode layer extends 40 in the interconnect region 44 and The dielectric layer extension 42 can have the same height as the corresponding electrode layer 20 and dielectric layer 22 deposited on the substrate surface 14. Interconnect region 44 may also be formed over one or more dielectric ridges 16 or under one or more trenches 15 rather than in separate interconnect regions; in such cases, electrode layer extension may generally not be required. 40.

In one example, the combined capacitance value of the integrated circuit capacitor having one of the parallel connected capacitors 18 is at least 10 pF. In such an example, the integrated circuit capacitor is formed on 1000 ridges 16 having two electrode layers 20 separated by a dielectric layer 22 and having an average ridge width 30 of about 200 nm and an average ridge height 32 of about 2 microns. The average ridge length 36 is about 2 microns and the average trench width 26 is about 200 nanometers. The electrode layer 20 has an average thickness of about 10 nm and the dielectric layer 22 has an average thickness of about 10 nm.

6 through 9 show a series of process profiles for producing electrical conductors 46, and Fig. 9 shows the contact of electrode layer extensions 40 in interconnect regions 44 to provide electrical access to curved plate capacitors 18 of the stacked plate capacitor members 17. path. In the examples of FIGS. 1 to 5, four electrode layers 20 and four dielectric layers 22 are shown, and in FIGS. 6-9, eight electrode layers 20 and eight dielectric layers 22 are shown to be more clearly A binary process is shown which produces electrical conductors 46 that interconnect these curved plate capacitors 18 with one another and with other components in the integrated circuit. These different electrode layer extensions 40 are identified in the figure as electrode layer extensions 40.0 to 40.7, and at the top is 40.0. The electrical conductors 46 that are in contact with the corresponding electrode layer extension 40 are labeled 0 through 7 in the figure. Dielectric layer extensions 42 are also numbered in a similar manner. When interconnect region 44 is above one or more dielectric ridges 16 or under one or more trenches 15, electrode conductor 46 will be in direct contact with electrode layer 20 without the need for electrode layer extension 40. In the above example, the integrated circuit capacitor 10 is formed in the trench of the substrate to have the advantage of lowering the overall structure height.

Figure 6 shows the position of a first photoresist mask 50 produced on an electrical conductor. The dielectric layer extends at the distal ends of 0, 2, 4, 6 and position 7. The area covered by the photoresist mask is sometimes referred to as the mask area. The region of the first photoresist mask 50 that is not covered, sometimes referred to as an etched region, is etched through the dielectric layer extension 42 and the electrical conductor 46 to create the structure of FIG. Thereafter, as shown in FIG. 7, the first photoresist mask 50 is removed and then the second photoresist mask 54 is formed over the structure in FIG. 6 to cover the positions 0, 1, 4 of the electrical conductor. , 5 and 7 at the far end. This structure then etches the exposed areas two layers to create the structure in Figure 7. Thereafter, the second photoresist mask 54 is removed and a third photoresist mask 58 is subsequently formed to cover the locations 0, 1, 2, 3 of the electrical conductor and the distal end of the location 7. The exposed regions of this structure are then etched four layers to create the structure shown in FIG.

Thereafter, the third photoresist mask 58 is removed and a selective conformal dielectric layer material can be deposited on the exposed surface, including the stepped wire pad 60, to create a dielectric barrier layer 62. The barrier layer 62 is used as an etch stop layer and may be a single layer of tantalum nitride. Dielectric fill layer 24 is then deposited over this completed structure. Appropriate via holes are then formed through the dielectric fill layer 24 and through the dielectric barrier layer 62 over which each of the electrode layers extends from 40.0 to 40.7. An electrical conductor 46 is then formed in the via hole to provide an electrical connection between the wire pad 60 of the electrode layer extension 40 and thus to the electrode layer 20 of the curved plate capacitor 18. The electrically conductive conductor 46 can be used with the same electrically conductive material as discussed. However, it is preferable to dope yttrium, tungsten and copper because the CMP characteristics of these electrically conductive materials have long been known in the industry. The electrical conductors 46 corresponding to positions 0-7 are identified as 46.0 to 46.7.

More than one interconnect region 44 can be used to access the wire pads 60 in different levels. Some or all of the wire pads 60 in different levels may be accessed by the same or different interconnect regions 44.

The process of producing the electrical conductor 46 can be referred to as a binary process because it is based on 2 ⁰ , ... 2 ^n-1 , where n is the number of etching steps. That is, a first photoresist mask 50 alternately curtain coating ²⁰ bonding wires 60 and the pad ²⁰ exposed wire pad 60; a second photoresist mask 54 alternately curtain coating ²¹ wire pad 60 and wire ²¹ exposed pad 60; The third photoresist mask 58 is alternately wrapped with the 2 ² wire pad 60 and the bare 2 ² wire pad 60; and so on. Using this binary process, n masks can provide access to 2 ⁿ wire pads 60 for 2 ⁿ electrical conductors 46. Thus, eight electrical conductors 46 can be provided with access to eight wire pads 60 using three masks. Access to 32 electrical pads 46 can be provided to 32 electrical pads 46 using five masks. The order of the etching steps is not necessarily performed in the order of n-1=0, 1, 2, . For example, the first etching step may be n-1=2, the second etching step may be n-1=0, and the third etching step may be n-1=1. This result will be the same as the structure shown in Fig. 8.

A more similar technique and method for electrically connecting the electrical conductor 46 to the wire pad 60 is disclosed in the U.S. patent entitled "Reduced Number of Mask for IC Device with Stacked Contact Levels" filed on March 16, 2011. The application is described in the application Serial No. 13/ 049, 303, filed on May 24, 2011, the entire disclosure of The invention has the same applicant.

The example of Fig. 9 has four curved plate capacitors 18 connected to the electrical conductors 46.0 and 46.1, 46.2 and 46.3, 46.4 and 46.5, 46.6 and 46.7. In order to form a capacitor having a large capacitance, capacitors denoted as C ₀₁ , C ₂₃ , C ₄₅ , and C ₆₇ in Fig. 10 may be placed in parallel. To do so, the electrical conductors 46.0, 46.2, 46.4, and 46.6 are short-circuited as the first electrode 47, and the electrical conductors 46.1, 46.3, 46.5, and 46.7 are short-circuited as the second electrode 48. In another example, as shown in Fig. 11, it is shown that each of the capacitors C ₀₁ , C ₂₃ , C ₄₅ , C _{67 is} connected in series. The overall capacitance value C _T of the example in Figure 11 will be less than any single capacitor value connected in series. It is useful when used in high voltage situations because each voltage device will only see a portion of the overall voltage. Figures 12A and 12B show capacitors C ₀₁ , C _{23 in} parallel and capacitors C ₄₅ , C ₆₇ are separated. The schematic of Fig. 12A shows the connection between the electrical conductors 46.0~46.7 and the main circuit 51. Another example is shown in Figure 13; in this example, the electrical conductors 46.2 and 46.5 are connected to ground such that the electrical conductors 46.2 and 46.5 of the electrode layer 20 and the electrode layer extension 40 are connected as capacitors C ₀₁ and C ₃₄ and capacitors. A barrier between C ₃₄ and C ₆₇ .

The integrated circuit capacitor 10 can be used in many cases. For example, a capacitor with a larger capacitance value can act as a power buffer. This design can reduce the stability of the power supply by damping the oscillation of the power supply voltage to make it smoother. The integrated circuit capacitor 10 designed to function as a power supply buffer can be approximately the same size as the main circuit 51; see Figures 14 and 15. In some cases, as shown in Fig. 15, the main circuit may be part of a main wafer 52 and the integrated circuit capacitor may be part of another integrated circuit capacitor chip 10a, both of which are packaged together in a common On the substrate 56. However, the yield problem can result in the option to use two or more smaller integrated circuit capacitors 10 instead of a larger integrated circuit capacitor, as shown in Figures 16 and 17. The integrated circuit capacitor 10 in other applications such as dynamic random access memory can then be a relatively small capacitor.

The integrated circuit capacitor 10 can be designed to be embedded in a multi-wafer as shown in Figures 14 and 16. The integrated circuit capacitor 10 can also be external to the chip such that only the capacitor is part of the wafer. Referring to Figures 15 and 17, the integrated circuit capacitor chip 10a can be placed on a multiple wafer carrier or the multiple wafer stack with the wafer 10a and other components in the main circuit can be wired by way of example. Or flipping or connecting via a via substrate via (TSV).

After testing, a particular curved plate capacitor 18 may have been found to be outside of the normal capacitance value. For example, after testing, a capacitor C _{67 of} a curved plate capacitor 18 between the electrical conductors 46.6 and 46.7 was found to have a capacitance value of 7.5 pF instead of the designed 10 pF. The electrode layer extensions 40.6 and 40.7 corresponding to the electrical conductor locations 6 and 7 are placed in a box indicating that the capacitor formed by the associated electrode layer does not conform to the specifications. The capacitor C _{67 of} the curved plate capacitor 18 can be driven into a poorly graded capacitance value of 7.5 pF. However, capacitor C _67, if considered to be defective, is labeled as a broken capacitor and will not be used. However, the secondary integrated circuit capacitor 10 having the broken capacitor can still be used as the split integrated circuit capacitor wafer 10a as shown in Figs. 15 and 17. Alternatively, the tantalum capacitor can be repaired in a manner similar to the memory error function. One such repair is accomplished by solving the connection between the tantalum capacitor and a separate capacitor using a set of spare body circuit capacitors similar to those produced by the integrated circuit capacitor chip 10b shown in Figs. 19 and 20. . The backup integrated circuit capacitor chip 10b may be the integrated circuit capacitor chip 10a disposed as shown in Fig. 17 or the integrated integrated circuit capacitor chip 10 as shown in Fig. 15. A control circuit, usually part of the main circuit 51, can be used to control this re-addressing function. Such a function can be achieved by conventionally using laser cutting or electrical fuses or embedded flash memory (non-volatile memory or resistive random access memory) code.

In a surface area no longer only one integrated circuit capacitor 10 is formed, and many different integrated circuit capacitors 10 can be created in the same surface area such that any tantalum capacitor can reduce the damage caused by flaws. Such results are shown in Figure 21. Of course, this solution still has to strike a balance between the possibility of generating more turns due to the addition of the integrated circuit capacitor 10.

In some semiconductor devices, the actual input of the voltage in the wafer is The location where the voltage is used may be a long distance. Such a distance may be such that the resistance between the location where the voltage is actually input in the wafer and the location where the voltage is used is large enough to severely affect the voltage at the actual use. Such a large separation may also be so large as to cause a transmission time delay between the actual input of the voltage in the wafer and the position at which the voltage is used. To help reduce these effects, a plurality of interconnect regions 44 may be formed in the same set of curved plate capacitors 18 surrounding the operating element in the same wafer. By doing so, it is possible to simultaneously supply voltages to different positions on the same electrode layer 20 or to different electrode layers 20. By doing so, it is possible to reduce the voltage difference between the different use positions and also to reduce the time required to apply this voltage to the entire electrode layer.

Some terms such as top, bottom, top, bottom, top, bottom, etc. are used in the above description. These terms are only used to help the understanding of the invention and are not intended to limit the scope of the invention.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents. For example, a portion of the trench width 26 shown in FIG. 1 is filled with a dielectric fill layer 24; in other examples, the entire trench width 26 is filled with an electrode layer and dielectric layers 20, 22.

All patents, patent applications, and papers referred to herein are incorporated by reference.

10‧‧‧Integrated circuit capacitors

10a‧‧‧Integrated circuit capacitor chip

10b‧‧‧Reserved integrated circuit capacitors

12‧‧‧Substrate

14‧‧‧Substrate surface

15‧‧‧ Ditch

16‧‧‧ Ridge

17‧‧‧Stacking

18‧‧‧Bent plate capacitor

20‧‧‧electrode layer

22‧‧‧Dielectric layer

24‧‧‧Filling layer

25‧‧‧Upper wall surface

27‧‧‧ sidewall surface

28‧‧‧First direction

30‧‧‧ Ridge width

32‧‧‧ Ridge height

34‧‧‧second direction

36‧‧‧ Ridge length

38‧‧‧ third direction

40‧‧‧electrode layer extension

42‧‧‧Dielectric layer extension

44‧‧‧Interconnected area

46‧‧‧Electrical conductor

50‧‧‧First photoresist mask

51‧‧‧ main circuit

52‧‧‧Main wafer

54‧‧‧Second photoresist mask

58‧‧‧ Third photoresist mask

60‧‧‧Stepped wire mat

62‧‧‧ dielectric barrier

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figure 1 shows an integrated circuit capacitor in accordance with an exemplary embodiment of the present invention.

Fig. 2 is a three-dimensional schematic view showing the dielectric ridge of the integrated circuit capacitor shown in Fig. 1 extending outward from the substrate.

Figure 3 is a cross-sectional view showing the structure of Figure 2 after the conformal deposited electrode layer is over the upper wall surface and side wall surface of the dielectric ridge and over the exposed substrate surface.

Figure 4 is a cross-sectional view showing the structure of Figure 3 after a conformal deposition of a dielectric layer over the electrode layer.

Figure 5 shows a cross-sectional view of the structure of Figure 4 after deposition of a four-layer electrode layer and four dielectric layers to produce a stack of two curved plate capacitors.

Figures 6-9 show a series of process profiles for creating an electrical conductor in an interconnected region and extending into contact with the electrode layer, as shown, for example, in the example of Figure 5, to provide electrical access to the curved plate capacitor. path.

Figure 10 shows a schematic of a parallel capacitor to provide a capacitor with a larger capacitance.

Figure 11 shows a schematic of a capacitor in series.

Figures 12 and 12A show that the two capacitors in one example are in parallel and the other two capacitors are separate.

Figure 13 shows two grounded electrical conductors as a barrier to the barrier between adjacent capacitors.

Figure 14 shows a schematic diagram of a main circuit and a single relatively large integrated circuit capacitor chip embedded in a multilayer wafer.

Figure 15 shows a schematic diagram of an off-chip design that places the main circuit and a relatively large integrated circuit capacitor chip on a common substrate.

Figure 16 shows a schematic diagram of a main circuit and a plurality of relatively small integrated circuit capacitor chips embedded in a multilayer wafer.

Figure 17 shows a simplified schematic diagram of a main circuit embedded in a primary multilayer wafer with multiple, smaller integrated circuit capacitor wafers disposed on the main multilayer wafer.

Figure 18 suggests that after testing, a separate curved plate capacitor can be tested and an abnormally curved plate capacitor can be relabeled for its true capacitance if needed.

Figures 19 and 20 suggest replacing the tantalum capacitor with a spare integrated circuit capacitor chip in addition to one or more integrated circuit capacitors after the tantalum capacitor is found.

Figure 21 suggests generating a plurality of integrated circuit capacitors in the integrated circuit capacitor wafer region to reduce the effects of the tantalum capacitor.

10‧‧‧Integrated circuit capacitors

12‧‧‧Substrate

14‧‧‧Substrate surface

15‧‧‧ Ditch

16‧‧‧ Ridge

17‧‧‧Stacking

18‧‧‧Bent plate capacitor

20‧‧‧electrode layer

22‧‧‧Dielectric layer

24‧‧‧Filling layer

30‧‧‧ Ridge width

Claims (12)

A capacitor comprising: a series of ridges and trenches and an interconnecting region on a substrate, the series of ridges and trenches and the interconnecting region having a capacitor base surface having a curved cross-sectional profile in the series a ridge and a trench; a curved stacked plate capacitor member comprising at least two electrically conductive electrode layers and a dielectric layer separating the electrode layer, a stack of one or more capacitors being produced at the capacitor base surface; and an electrical conductor The interconnect region is electrically connected to the electrode layer to access the electrode layer of the capacitor member. The capacitor of claim 1, wherein the interconnected region is separated from the series of ridges and trenches. The capacitor of claim 1, wherein the interconnected region is in at least one of the ridge or the ditch. The capacitor of claim 1, wherein the electrical conductor passes through a vertical via hole in the interconnect region, the vertical via hole is over the contact pad of the electrode layer, and the electrical conductor is in contact with the contact Padded connection. The capacitor of claim 1, wherein each of the electrical conductors is electrically connected to a contact pad of an electrode layer. The capacitor of claim 1, wherein the ridge of the series is located in a trench of the substrate. The capacitor of claim 1, wherein: the ridge has a ridge width, the trench has a trench width, the ridge width, the trench width extends in a first direction; the ridge has a ridge height in a second Extending in a direction perpendicular to the first direction; the ridge having a ridge length measured in a third direction, the third direction being perpendicular to the first and second directions; the ridge having a sidewall surface at the The second and third parties extend upward; an upper wall surface extends upwardly in the first and third directions; and the substrate includes a substrate surface extending in the first and third directions. A method of forming a capacitor comprising: forming a series of ridges on a substrate, the series of ridges being separated by trenches, and forming an interconnected region on the substrate adjacent to the series of ridges and ditches, the series The ridge and the trench and the interconnected region have a capacitor base surface; the ridge forming step is performed such that the capacitor base surface has convex and concave structures to define a curved cross-sectional profile; forming staggered electrically conductive electrode layers and interposing An electrical layer separates the electrode layer from the capacitor base surface to create a stack of at least two curved plate capacitors; and electrically interconnecting the electrode layer and the electrical conductor to access the electrode layer in the interconnect region. The method of claim 8, wherein the ridge forming step comprises forming the series of dielectric ridges in a trench on the substrate. The method of claim 8, wherein the electrical connection step comprises: Removing material from a portion of the interconnect region, the material coating a contact pad of the electrode layer; depositing a dielectric material in the portion of the interconnect region; forming a via hole through the interconnect region to the contact pad; And forming an electrical conductor in the via hole and electrically coupling the electrical conductor to the contact pad. The method of claim 8, wherein the electrically connecting step comprises: using a set of N etch masks to create contact pads of up to 2 ^N levels in the interconnect region, each mask comprising The mask and the etched area, N is an integer of at least 2, and x is the number of sequences of the mask starting from x=0 such that one mask x=0 and the other mask x=1 until x=n-1; The mask etches the interconnect region N times in a pre-selected order to create a contact opening extending to each electrode layer; the etching step includes etching each mask of the sequence X through 2 ^N electrode layers. The method of claim 8, wherein the staggered electrically conductive electrode layer and the dielectric layer forming step form a stack of at least four curved plate capacitors.