KR0126646B1 - Method for forming the contact hold of a semiconductor device - Google Patents
Method for forming the contact hold of a semiconductor deviceInfo
- Publication number
- KR0126646B1 KR0126646B1 KR1019940005627A KR19940005627A KR0126646B1 KR 0126646 B1 KR0126646 B1 KR 0126646B1 KR 1019940005627 A KR1019940005627 A KR 1019940005627A KR 19940005627 A KR19940005627 A KR 19940005627A KR 0126646 B1 KR0126646 B1 KR 0126646B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- contact hole
- etching
- silicon oxide
- contact
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000005530 etching Methods 0.000 claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 17
- 229920000642 polymer Polymers 0.000 claims abstract description 16
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
제1a도 내지 제1c도는 종래기술에 의한 반도체소자의 콘택홀 형성공정을 도시한 단면도.1A to 1C are cross-sectional views showing a contact hole forming process of a semiconductor device according to the prior art.
제2a도 내지 제2c도는 본 발명에 의한 반도체소자의 콘택홀 형성공정을 도시한 단면도.2A to 2C are cross-sectional views showing a contact hole forming process of a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : 반도체 기판 2 : 산화막1 semiconductor substrate 2 oxide film
3 : 다결정실리콘막 4 : 제 1 절연막3: polycrystalline silicon film 4: first insulating film
5 : 제 3 절연막 5' : 제 3 절연막패턴5: third insulating film 5 ': third insulating film pattern
6,17 : 콘택마스크 9 : 제 2 절연막6,17 contact mask 9: second insulating film
10 : 식각장벽층 l1 : 제 2 절연막 스페이서10: etching barrier layer l1: second insulating film spacer
13,24 : 실리콘산화막 14 : 폴리머13,24 silicon oxide film 14 polymer
15 : 평탄화층 20,40 : 콘택홀15: planarization layer 20, 40: contact hole
본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 반도체기판 상부에 워드라인을 형성하고, 그 상부에 절연막, 그 측벽에 절연막 스페이서를 형성하고, 전체구조상부에 실리콘산화막을 일정두께 증착하고, 그 상부에 평탄화층을 형성하고, 그 상부에 콘택마스크를 형성한 다음, C4F8과 CO 가스를 사용하고 고밀도의 플라즈마 반응용기를 이용하여 콘택홀 식각공정을 실시하되 형성하려는 콘택홀의 측벽에는 폴리머가 상기 반도체기판에 가까워질수록 두꺼워지도록하여 미세콘택홀을 형성할 수 있는 슬로프 식각을 실시함으로써 상기 평탄화층과 실리콘산화막을 식각하여 콘택홀을 형성한 다음, 산소플라즈마 식각공정으로 상기 콘택마스크와 폴리머를 제거함으로써, 종래에 복잡한 자기정렬적 콘택홀을 형성방법보다 더 간단하게 더 미세한 콘택홀을 형성할 수 있어 반도체소자를 고집적화시키과 콘택홀 형성공정과 공정시간을 단축시켜 생산성을향상시키고 단가를 절감시킬 수 있는 기술이다.The present invention relates to a method of forming a contact hole in a semiconductor device, comprising: forming a word line on an upper surface of a semiconductor substrate, an insulating film on an upper side thereof, an insulating film spacer on a sidewall thereof, and depositing a silicon oxide film on the entire structure to a predetermined thickness; A planarization layer is formed on the upper side, a contact mask is formed on the upper side thereof, and then a contact hole etching process is performed using C 4 F 8 and CO gas and a high density plasma reaction vessel. As the polymer gets closer to the semiconductor substrate, the contact layer is formed by etching the planarization layer and the silicon oxide layer by etching the planarization layer and the silicon oxide layer by forming a slope contact to form a fine contact hole, and then contacting the contact mask with an oxygen plasma etching process. By removing the polymer, it is simpler and finer than the conventional method of forming complex self-aligned contact holes. It is possible to form a highly integrated sikigwa taekhol shorten the contact hole formation process and the process time of the semiconductor device is a technique that can improve the productivity and reduce the unit cost.
반도체소자가 고집적화됨에 따라 0.25㎛급 이하의 콘택홀을 형성하기 위하여 일종의 자기정렬적으로 콘택홀을 형성하여야 했으나 많은 공정으로 복잡하고, 제품개발시간이 길어지고, 소자의 제품단가를 상승시키는 원인을 제공한다.As semiconductor devices have been highly integrated, it was necessary to form contact holes in a kind of self-alignment in order to form contact holes of 0.25 µm or less, but it was complicated by many processes, and the product development time was long, and the product cost of devices was increased. to provide.
이하, 첨부된 도면을 참고로 하여 종래기술을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the prior art.
제1A도 내지 제1C도는 종래기술에 의한 반도체소자의 콘택홀 형성공정을 도시한 단면도이다.1A to 1C are cross-sectional views showing a contact hole forming process of a semiconductor device according to the prior art.
제1A도는 반도체기판(1) 상부에 산화막(2), 워드라인 형성용 다결정실리콘막(3) 및 제1절연막(4)으로 형성된 워드라인을 형성한 다음, 그 상부에 제2절연막(9)과 식각장벽층(10)을 일정두께 증착하고 그 상부에 제 3 절연막(5)을 사용하여 평탄화층을 형성한 후, 그 상부에 감광막을 이용하여 콘택마스크(6)를 형성한것을 도시한 단면도이다. 여기서, 상기 제 3 절연막(5)은 비.피.에스.지 (BPSG:Boro-Phospho-Silicate-Glass, 이하에서 BPSG라 함)를 사용하여 형성한다In FIG. 1A, a word line formed of an oxide film 2, a polysilicon film 3 for forming a word line, and a first insulating film 4 is formed on a semiconductor substrate 1, and then a second insulating film 9 is formed thereon. And the etching barrier layer 10 is deposited to a predetermined thickness, and a planarization layer is formed on the upper portion using the third insulating film 5, and then the contact mask 6 is formed on the upper portion using the photoresist layer. to be. Here, the third insulating film 5 is formed using B.P.S. paper (BPSG: Boro-Phospho-Silicate-Glass, hereinafter referred to as BPSG).
제1B도는 상기 콘택마스크(6)를 사용하여 상기 제3절연막(5)을 식각하여 제 3절연막패턴(5')을 형성한 것을 도시한 단면도이다.FIG. 1B is a cross-sectional view illustrating a third insulating film pattern 5 ′ formed by etching the third insulating film 5 using the contact mask 6.
제1C도는 상기 콘택마스크(6)와 제 3 절연막패턴(5')을 사용하여 하부의 제 2절연막(9)과 식각장벽층(10)을 일정두께 식각함으로써 상기 워드라인의 측벽에 제 2절연막 스페이서(11)를 형성하는 동시에 반도체기판(l) 상부에 자기정렬적인 콘택홀(20)을 형성한 것을 도시한 단면도이다.FIG. 1C illustrates a second insulating layer formed on the sidewall of the word line by etching a lower thickness of the second insulating layer 9 and the etch barrier layer 10 using the contact mask 6 and the third insulating layer pattern 5 '. FIG. 11 is a cross-sectional view illustrating the formation of the spacer 11 and the formation of a self-aligning contact hole 20 on the semiconductor substrate 1.
상기한 종래기술에 의하면, 반도체소자의 고집적화에 부응하여 자기정렬형 콘택홀을 형성함으로써 소자에서 필요한 미세콘택홀을 형성할 수 있지만, 공정이 복잡하여 많은 시간이 소요되고 원가상승의 원인을 제공하는 문제점이 있다.According to the above-described prior art, in order to meet the high integration of the semiconductor device, a self-aligned contact hole can be formed to form a fine contact hole required in the device, but the process is complicated and takes a lot of time and provides a cause of cost increase. There is a problem.
따라서, 본 발명에서는 상기한 종래기술의 문제점이 해결된 0.25μm 이하의 미세콘택홀을 형성하기 위하여 탄소(carbon)성분이 많이 함유된 가스인 C4F8과 CO 가스를 사용하여 식각하는 방법으로써, 반도체기판 상부에 하부층을 형성하고 그 상부에 콘택마스크를 형성한 후에 상기 콘택마스크를 이용하여 상기 하부층을 상기의 두 가스를 사용하여 식각할때 상기 두개의 가스가 촉매작용을 하여 시간이 지남에 따라 하부층 내부에 폴리머(polymer)를 생성과 하부층의 식각이 동시에 발생하는 슬로프 식각(slope etch)이 됨으로써, 별도의 추가공정이 없이 간단하게 반도체소자의 콘택홀을 형성하는데 그 목적이 있다.Therefore, in the present invention, as a method of etching using C 4 F 8 and CO gas which is a gas containing a large amount of carbon in order to form a fine contact hole of 0.25 μm or less, which solves the problems of the prior art. After the lower layer is formed on the semiconductor substrate and the contact mask is formed thereon, the two gases catalyze when the lower layer is etched using the two gases using the contact mask. As a result, a slope etch occurs in which a polymer is formed inside the lower layer and the etching of the lower layer is simultaneously performed. Accordingly, an object of the present invention is to simply form a contact hole of a semiconductor device without an additional process.
이상의 목적을 달성하기 위한 본 발명의 특징은, 반도체기판 상부에 워드라인을 형성하고 상기 워드라인의 상부에 실리콘산화막을 사용하여 절연막을 형성한 다음, 상기 워드라인의 측벽에 산화막을 사용하여 스페이서를 형성하는 공정과, 상부구조전체에 절연막인 실리콘산화막을 일정두께 증착하는 공정과, 상기 실리콘산화막의 상부에 BPSG 사용하여 평탄화층을 형성하는 공정과, 상기 평탄화층의 상부에 감광막을 이용하여 콘택마스크를 형성하는 공정과, 상기 평탄화층과 실리콘산화막을 식각하되 전체구조상부로부터 C4F8과CO 가스를 사용함으로써 시간이 흐를수록 형성하려는 콘택홀의 측벽에 많은 폴리머가 발생되도록 하는 슬로프 식각을 하여 상기 콘택마스크 보다 미세한 콘택홀을 형성하는 공정과, 산소플라즈마 식각공정으로 상기 콘택마스크와 폴리머를 식각하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above object is to form a word line on the semiconductor substrate, and to form an insulating film using a silicon oxide film on top of the word line, and then to form a spacer using an oxide film on the sidewall of the word line Forming a film; depositing a silicon oxide film as an insulating film over the upper structure; forming a planarization layer using BPSG on the silicon oxide film; and using a photoresist film on the planarization layer. And etching the planarization layer and the silicon oxide layer by using a C 4 F 8 and CO gas from the entire structure to perform a slope etching to generate a large amount of polymer on the sidewall of the contact hole to be formed over time. Forming a contact hole finer than that of a contact mask; and performing the contact by an oxygen plasma etching process. It includes the process of etching the mask and the polymer.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2A도는 반도체기판(50) 상부에 다결정실리콘막(3)을 형성하고 그 상부에 실리콘산화막(24)을 형성한다음, 상기 다결정실리콘막(3)의 측벽에 층간절연을 목적으로 절연막 스페이서를 형성하고 그 상부에 절연목적으로 실리콘산화막(13)을 증착하고 그 상부에 제3절연막(15)으로 평탄화층을 형성한 후, 그 상부에 감광막을 이용하여 콘택마스크(17)를 형성한 것을 도시한 단면도이다. 여기서, 상기 제 3 절연막(15)은 BPSG를 사용하여 형성한다.2A shows a polysilicon film 3 formed on the semiconductor substrate 50 and a silicon oxide film 24 formed thereon, and then insulating film spacers are formed on the sidewalls of the polysilicon film 3 for interlayer insulation. After forming and depositing a silicon oxide film 13 for insulating purposes thereon and a planarization layer formed thereon with a third insulating film 15 thereon, and then forming a contact mask 17 using a photosensitive film thereon. One cross section. Here, the third insulating film 15 is formed using BPSG.
제2B도는 상기 제2A도의 공정후에 C4F8과 CO 가스를 이용하여 상기 제 3 절연막(15) 및 실리콘산화막(13)을 높은 밀도의 플라즈마 반응장치를 이용하여 슬로프 식각함으로써 상기 반도체기판(50) 상부에 콘택홀(40)을 형성한 것을 도시한 단면도로서, 상기 C4F8가스는 많은 탄소를 함유하는 가스로서 많은 탄소를 함유하는 폴리머(14)를 발생시키는 역할을 하며 상기 C4F8대신에 C3F8가스를 사용하기도 하고, 상기 CO가스는 수직방향으로의 식각공정이 진행되도록 하는 역할을 한다. 그리고, 상기 C4F8과 CO 가스는 1SCCM이상에서 200SCCM 이하의 플로우 비듈을 갖는다. 여기서, 상기 C4F8만 사용할 경우는 발생되는 폴리머(14)의 양이 너무 많아지게되어 식각공정이 더 이상 진행되지 않는 현상이 발생된다. 그러나, 상기 CO 가스를 함께 사용함으로써 형성되는 콘택홀(40)의 측벽에는 폴리머(14)가 발생되며, 수직방향으로는 상기 제 3 절연막(l5)과 실리콘산화막(13)의 식각이 계속되고 시간이 지나서 상기 반도체기판(50)에 가까워질수록 폴리머(14)의 증가로 인하여 상기 콘택홀(40)의 폭이 좁아짐으로써 미세콘택홀을 형성할 수 있다.FIG. 2B shows the semiconductor substrate 50 by slope etching the third insulating film 15 and the silicon oxide film 13 using a high density plasma reactor using C 4 F 8 and CO gas after the process of FIG. 2A. ) Is a cross-sectional view showing a contact hole 40 formed on the upper portion, wherein the C 4 F 8 gas is a gas containing a large amount of carbon and serves to generate a polymer 14 containing a large amount of carbon, and the C 4 F may use the C 3 F 8 gas in place of 8, and the CO gas serves to ensure that the etching process proceeds in the vertical direction. In addition, the C 4 F 8 and CO gas has a flow bead of less than 200SCCM at 1SCCM or more. In this case, when only the C 4 F 8 is used, the amount of the polymer 14 generated is too large, and thus the etching process does not proceed any more. However, the polymer 14 is generated on the sidewall of the contact hole 40 formed by using the CO gas, and the etching of the third insulating film l5 and the silicon oxide film 13 continues in the vertical direction. After this, the closer to the semiconductor substrate 50, the narrower the width of the contact hole 40 due to the increase of the polymer 14 can form a fine contact hole.
제2C도는 산소플라즈마를 이용하여 상기 콘택마스크(17)와 폴리머(14)를 제거함으로써 미세콘택홀(40)이 형성된 것을 도시한 단면도로서, 별도의 추가공정으로 상기 폴리머(14)를 제거할 필요가 없다. 여기서, 상기콘택마스크(l7)의 크기가 0.5μm일 경우에도 상기 콘택홀(40)의 크기를 0.25μm 이하로 형성할 수 있다.2C is a cross-sectional view showing that the micro contact hole 40 is formed by removing the contact mask 17 and the polymer 14 by using an oxygen plasma, and it is necessary to remove the polymer 14 by a separate additional process. There is no. Here, even when the size of the contact mask l7 is 0.5 μm, the size of the contact hole 40 may be formed to be 0.25 μm or less.
상기한 본 발명에 의하면, 종래의 리소그래피 기술을 이용하여 0.25μm 이하의 미세콘택홀을 형성할 수 있어 소자의 고집적화를 향상시키고, 공정이 간단하여 공정시간을 단축할 수 있어 소자의 생산성을 향상시키고 원가절감에 기여할 수 있다.According to the present invention, it is possible to form a fine contact hole of 0.25μm or less by using the conventional lithography technology to improve the high integration of the device, the process is simple to shorten the process time to improve the device productivity It can contribute to cost reduction.
Claims (5)
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| KR1019940005627A KR0126646B1 (en) | 1994-03-21 | 1994-03-21 | Method for forming the contact hold of a semiconductor device |
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| KR1019940005627A KR0126646B1 (en) | 1994-03-21 | 1994-03-21 | Method for forming the contact hold of a semiconductor device |
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| KR0126646B1 true KR0126646B1 (en) | 1998-04-02 |
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| KR100510067B1 (en) * | 1999-12-30 | 2005-08-26 | 주식회사 하이닉스반도체 | Self align contact etching method for forming semiconductor device |
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| KR19990075068A (en) * | 1998-03-17 | 1999-10-05 | 윤종용 | Insulation etching method and semiconductor device manufacturing method using same |
| KR20030096671A (en) * | 2002-06-17 | 2003-12-31 | 동부전자 주식회사 | Fabricating method of contact hole in semiconductor device |
| KR101115526B1 (en) * | 2010-01-25 | 2012-02-27 | 전자부품연구원 | method for manufacturing Through Silicon ViaTSV |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100510067B1 (en) * | 1999-12-30 | 2005-08-26 | 주식회사 하이닉스반도체 | Self align contact etching method for forming semiconductor device |
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