JPH0560625B2 - - Google Patents
Info
- Publication number
- JPH0560625B2 JPH0560625B2 JP23575786A JP23575786A JPH0560625B2 JP H0560625 B2 JPH0560625 B2 JP H0560625B2 JP 23575786 A JP23575786 A JP 23575786A JP 23575786 A JP23575786 A JP 23575786A JP H0560625 B2 JPH0560625 B2 JP H0560625B2
- Authority
- JP
- Japan
- Prior art keywords
- master
- busy
- slave
- access
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Multi Processors (AREA)
- Bus Control (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23575786A JPS6389956A (ja) | 1986-10-03 | 1986-10-03 | マスタ・スレーブシステムのアクセス制御方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23575786A JPS6389956A (ja) | 1986-10-03 | 1986-10-03 | マスタ・スレーブシステムのアクセス制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6389956A JPS6389956A (ja) | 1988-04-20 |
| JPH0560625B2 true JPH0560625B2 (enrdf_load_stackoverflow) | 1993-09-02 |
Family
ID=16990782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23575786A Granted JPS6389956A (ja) | 1986-10-03 | 1986-10-03 | マスタ・スレーブシステムのアクセス制御方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6389956A (enrdf_load_stackoverflow) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5140680A (en) * | 1988-04-13 | 1992-08-18 | Rockwell International Corporation | Method and apparatus for self-timed digital data transfer and bus arbitration |
| JP5111940B2 (ja) * | 2007-05-31 | 2013-01-09 | 株式会社東芝 | 情報処理装置及びアクセス制御方法 |
| JP2009264326A (ja) * | 2008-04-28 | 2009-11-12 | Toyota Motor Corp | 内燃機関の制御装置 |
| JP6629215B2 (ja) * | 2014-02-07 | 2020-01-15 | アセンシア・ディアベティス・ケア・ホールディングス・アーゲー | マルチマスターバスプロトコルのための方法および装置 |
-
1986
- 1986-10-03 JP JP23575786A patent/JPS6389956A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6389956A (ja) | 1988-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4449183A (en) | Arbitration scheme for a multiported shared functional device for use in multiprocessing systems | |
| US5119480A (en) | Bus master interface circuit with transparent preemption of a data transfer operation | |
| EP0476990A2 (en) | Dynamic bus arbitration | |
| US5293491A (en) | Data processing system and memory controller for lock semaphore operations | |
| JPH06231074A (ja) | システムバスの多重アクセス方式 | |
| US20010034805A1 (en) | Data processing device accessing a memory in response to a request made by an external bus master | |
| WO2007105376A1 (ja) | 集積回路、及び集積回路システム | |
| JPH0560625B2 (enrdf_load_stackoverflow) | ||
| US7302508B2 (en) | Apparatus and method for high speed data transfer | |
| EP0130471A2 (en) | Interface controller for connecting multiple asynchronous buses and data processing system including such controller | |
| JPS61166647A (ja) | マイクロプロセツサ装置およびアドレス可能なメモリから情報を読出すためのアクセス方法 | |
| JP3240863B2 (ja) | 調停回路 | |
| JPH0290382A (ja) | 半導体集積回路 | |
| JP2001318906A (ja) | マルチプロセッサ装置 | |
| JPH02281356A (ja) | 共有メモリ装置 | |
| US20020069311A1 (en) | Bus control device | |
| JPS63278168A (ja) | バス制御装置 | |
| JPH03201054A (ja) | 共通バス制御方法及びその制御装置並びにマスタ装置と計算機システム | |
| JP2632049B2 (ja) | マルチプロセッサシステム | |
| JP2637319B2 (ja) | 直接メモリアクセス回路 | |
| KR100191242B1 (ko) | 데이타 전송장치 | |
| JPH06149749A (ja) | 複数プロセッサ間におけるデータ転送方式 | |
| JPH0575140B2 (enrdf_load_stackoverflow) | ||
| JPH0528861B2 (enrdf_load_stackoverflow) | ||
| JPS6172350A (ja) | デ−タ転送制御方式 |