JPH0560069B2 - - Google Patents

Info

Publication number
JPH0560069B2
JPH0560069B2 JP58243050A JP24305083A JPH0560069B2 JP H0560069 B2 JPH0560069 B2 JP H0560069B2 JP 58243050 A JP58243050 A JP 58243050A JP 24305083 A JP24305083 A JP 24305083A JP H0560069 B2 JPH0560069 B2 JP H0560069B2
Authority
JP
Japan
Prior art keywords
output
input
logic
gate
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58243050A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59133471A (ja
Inventor
Meerotora Deiipatsuku
Kanto Rajani
Emu Pateru Kishoa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of JPS59133471A publication Critical patent/JPS59133471A/ja
Publication of JPH0560069B2 publication Critical patent/JPH0560069B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
JP58243050A 1982-12-22 1983-12-22 集積回路 Granted JPS59133471A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/452,169 US4527115A (en) 1982-12-22 1982-12-22 Configurable logic gate array
US452169 1982-12-22

Publications (2)

Publication Number Publication Date
JPS59133471A JPS59133471A (ja) 1984-07-31
JPH0560069B2 true JPH0560069B2 (enExample) 1993-09-01

Family

ID=23795350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58243050A Granted JPS59133471A (ja) 1982-12-22 1983-12-22 集積回路

Country Status (2)

Country Link
US (1) US4527115A (enExample)
JP (1) JPS59133471A (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07119789B2 (ja) * 1983-02-04 1995-12-20 株式会社日立製作所 半導体集積回路装置及びその診断方法
JPS59172734A (ja) * 1983-03-23 1984-09-29 Hitachi Ltd 半導体集積回路
US4607175A (en) * 1984-08-27 1986-08-19 Advanced Micro Devices, Inc. Non-inverting high speed low level gate to Schottky transistor-transistor logic translator
US4670714A (en) * 1984-12-17 1987-06-02 Advanced Micro Devices, Inc. Programmable output polarity device
US4691161A (en) * 1985-06-13 1987-09-01 Raytheon Company Configurable logic gate array
US4712213A (en) * 1985-12-11 1987-12-08 Northern Telecom Limited Flip status line
US4714876A (en) * 1986-04-14 1987-12-22 Ncr Corporation Circuit for initiating test modes
US4791603A (en) * 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
JPS63102236A (ja) * 1986-10-20 1988-05-07 Fujitsu Ltd 出力端子試験回路
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5369593A (en) * 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5353243A (en) * 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
GB8921561D0 (en) * 1989-09-23 1989-11-08 Univ Edinburgh Designs and procedures for testing integrated circuits containing sensor arrays
JPH0474977A (ja) * 1990-07-16 1992-03-10 Nec Corp 半導体集積回路
US5528600A (en) * 1991-01-28 1996-06-18 Actel Corporation Testability circuits for logic arrays
US5243274A (en) * 1992-08-07 1993-09-07 Westinghouse Electric Corp. Asic tester
DE69326248T2 (de) * 1993-11-30 2000-02-24 Stmicroelectronics S.R.L., Agrate Brianza Schaltungsarchitektur und Verfahren zur Prüfung einer programmierbaren Logikmatrix
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5959466A (en) 1997-01-31 1999-09-28 Actel Corporation Field programmable gate array with mask programmed input and output buffers
US6150837A (en) * 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6016563A (en) * 1997-12-30 2000-01-18 Fleisher; Evgeny G. Method and apparatus for testing a logic design of a programmable logic device
US6581018B1 (en) * 2000-07-26 2003-06-17 Sun Microsystems, Inc. Multiplexer select line exclusivity check method and apparatus
US7299203B1 (en) * 2001-04-19 2007-11-20 Xilinx, Inc. Method for storing and shipping programmable ASSP devices
US9500700B1 (en) * 2013-11-15 2016-11-22 Xilinx, Inc. Circuits for and methods of testing the operation of an input/output port

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961251A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961252A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
JPS5255874A (en) * 1975-10-31 1977-05-07 Toshiba Corp Integrated circuit
US4333142A (en) * 1977-07-22 1982-06-01 Chesley Gilman D Self-configurable computer and memory system
US4139818A (en) * 1977-09-30 1979-02-13 Burroughs Corporation Circuit means for collecting operational errors in IC chips and for identifying and storing the locations thereof
AU530415B2 (en) * 1978-06-02 1983-07-14 International Standard Electric Corp. Integrated circuits
US4404519A (en) * 1980-12-10 1983-09-13 International Business Machine Company Testing embedded arrays in large scale integrated circuits

Also Published As

Publication number Publication date
JPS59133471A (ja) 1984-07-31
US4527115A (en) 1985-07-02

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term