JPH0550771B2 - - Google Patents
Info
- Publication number
- JPH0550771B2 JPH0550771B2 JP60207817A JP20781785A JPH0550771B2 JP H0550771 B2 JPH0550771 B2 JP H0550771B2 JP 60207817 A JP60207817 A JP 60207817A JP 20781785 A JP20781785 A JP 20781785A JP H0550771 B2 JPH0550771 B2 JP H0550771B2
- Authority
- JP
- Japan
- Prior art keywords
- array
- stage
- multiplication
- output
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60207817A JPS6267637A (ja) | 1985-09-20 | 1985-09-20 | 配列乗算器 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60207817A JPS6267637A (ja) | 1985-09-20 | 1985-09-20 | 配列乗算器 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6267637A JPS6267637A (ja) | 1987-03-27 |
| JPH0550771B2 true JPH0550771B2 (enExample) | 1993-07-29 |
Family
ID=16545996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60207817A Granted JPS6267637A (ja) | 1985-09-20 | 1985-09-20 | 配列乗算器 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6267637A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4953119A (en) * | 1989-01-27 | 1990-08-28 | Hughes Aircraft Company | Multiplier circuit with selectively interconnected pipelined multipliers for selectively multiplication of fixed and floating point numbers |
-
1985
- 1985-09-20 JP JP60207817A patent/JPS6267637A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6267637A (ja) | 1987-03-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0448367B1 (en) | High speed digital parallel multiplier | |
| JPH0431413B2 (enExample) | ||
| JP3761977B2 (ja) | 遅延整合技術の利用によりクリティカル・パスを減少させた浮動小数点型掛け算器及びその演算方法 | |
| US6369610B1 (en) | Reconfigurable multiplier array | |
| US4901270A (en) | Four-to-two adder cell for parallel multiplication | |
| JPS60163128A (ja) | 乗算回路 | |
| JPH0831025B2 (ja) | 乗算回路 | |
| JPH05204609A (ja) | 乗算回路 | |
| KR100308726B1 (ko) | 고속 산술 장치에서 올림수 예견가산기 스테이지의 수를 감소시키는 장치 및 방법 | |
| US20040010536A1 (en) | Apparatus for multiplication of data in two's complement and unsigned magnitude formats | |
| JPH09231201A (ja) | 浮動小数点乗算累算装置 | |
| US4263660A (en) | Expandable arithmetic logic unit | |
| JPH0550771B2 (enExample) | ||
| JPH0584529B2 (enExample) | ||
| JP3515170B2 (ja) | 実数または複素数用の乗算器 | |
| JP3227538B2 (ja) | 2進整数乗算器 | |
| JP2700876B2 (ja) | 並列乗算器 | |
| JPH0370416B2 (enExample) | ||
| JPH0326857B2 (enExample) | ||
| JPH0527948A (ja) | 演算装置 | |
| JPS60112141A (ja) | 乗算回路 | |
| JP3098648B2 (ja) | 乗算器 | |
| JP2907276B2 (ja) | 演算処理装置 | |
| JP2001249798A (ja) | 規則的加算回路を使用して乗算器の性能を増大させる装置及び方法 | |
| JPH1063485A (ja) | ディジタル乗算器用加算器 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |