JPH0546101B2 - - Google Patents

Info

Publication number
JPH0546101B2
JPH0546101B2 JP21832688A JP21832688A JPH0546101B2 JP H0546101 B2 JPH0546101 B2 JP H0546101B2 JP 21832688 A JP21832688 A JP 21832688A JP 21832688 A JP21832688 A JP 21832688A JP H0546101 B2 JPH0546101 B2 JP H0546101B2
Authority
JP
Japan
Prior art keywords
resin
film
semiconductor substrate
pii
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP21832688A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6477148A (en
Inventor
Tatsumi Shirasu
Yasunobu Osa
Tokio Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21832688A priority Critical patent/JPS6477148A/ja
Publication of JPS6477148A publication Critical patent/JPS6477148A/ja
Publication of JPH0546101B2 publication Critical patent/JPH0546101B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP21832688A 1979-03-28 1988-09-02 Semiconductor storage device Granted JPS6477148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21832688A JPS6477148A (en) 1979-03-28 1988-09-02 Semiconductor storage device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3548079A JPS55128851A (en) 1979-03-28 1979-03-28 Semiconductor memory device
JP21832688A JPS6477148A (en) 1979-03-28 1988-09-02 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS6477148A JPS6477148A (en) 1989-03-23
JPH0546101B2 true JPH0546101B2 (enrdf_load_stackoverflow) 1993-07-13

Family

ID=12442917

Family Applications (2)

Application Number Title Priority Date Filing Date
JP3548079A Granted JPS55128851A (en) 1979-03-28 1979-03-28 Semiconductor memory device
JP21832688A Granted JPS6477148A (en) 1979-03-28 1988-09-02 Semiconductor storage device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP3548079A Granted JPS55128851A (en) 1979-03-28 1979-03-28 Semiconductor memory device

Country Status (1)

Country Link
JP (2) JPS55128851A (enrdf_load_stackoverflow)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55140249A (en) * 1979-04-18 1980-11-01 Fujitsu Ltd Semiconductor device
JPS5630746A (en) * 1979-08-22 1981-03-27 Fujitsu Ltd Semiconductor device
JPS577144A (en) * 1980-06-17 1982-01-14 Fujitsu Ltd Semiconductor device
JPS5776868A (en) * 1980-10-30 1982-05-14 Fujitsu Ltd Forming method for resin protected film
DE3125284A1 (de) * 1981-06-26 1983-01-13 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von bauelementen aus halbleiterscheiben
JPS584954A (ja) * 1981-06-30 1983-01-12 Hitachi Ltd 樹脂封止型半導体メモリー装置
JPS5816553A (ja) * 1981-07-22 1983-01-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPS58147048A (ja) * 1982-02-25 1983-09-01 Fujitsu Ltd 半導体装置の製造方法
US4468411A (en) * 1982-04-05 1984-08-28 Motorola, Inc. Method for providing alpha particle protection for an integrated circuit die
JPS58223352A (ja) * 1982-06-21 1983-12-24 Matsushita Electric Ind Co Ltd 半導体装置
US4653175A (en) * 1984-02-09 1987-03-31 Fairchild Semiconductor Corporation Semiconductor structure having alpha particle resistant film and method of making the same
JPS62204575A (ja) * 1986-03-05 1987-09-09 Matsushita Electric Ind Co Ltd 薄膜半導体装置およびその製造方法
CA2021682C (en) * 1989-07-21 1995-01-03 Yukio Yamaguchi Chip-carrier with alpha ray shield
US5264726A (en) * 1989-07-21 1993-11-23 Nec Corporation Chip-carrier
US7382043B2 (en) * 2002-09-25 2008-06-03 Maxwell Technologies, Inc. Method and apparatus for shielding an integrated circuit from radiation
US7191516B2 (en) 2003-07-16 2007-03-20 Maxwell Technologies, Inc. Method for shielding integrated circuit devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5166776A (ja) * 1974-12-06 1976-06-09 Hitachi Ltd Koshuhahandotaisochi oyobi sonoseizohoho
JPS5226989A (en) * 1975-08-22 1977-02-28 Chiyoda Shigyo Kk Paper bag trnsferring method for heavy packaging paper sewing machine
JPS53142375A (en) * 1977-05-18 1978-12-12 Babcock Hitachi Kk Rotary kiln

Also Published As

Publication number Publication date
JPS6477148A (en) 1989-03-23
JPS6228584B2 (enrdf_load_stackoverflow) 1987-06-22
JPS55128851A (en) 1980-10-06

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