JPH0543215B2 - - Google Patents

Info

Publication number
JPH0543215B2
JPH0543215B2 JP62251980A JP25198087A JPH0543215B2 JP H0543215 B2 JPH0543215 B2 JP H0543215B2 JP 62251980 A JP62251980 A JP 62251980A JP 25198087 A JP25198087 A JP 25198087A JP H0543215 B2 JPH0543215 B2 JP H0543215B2
Authority
JP
Japan
Prior art keywords
circuit
array
product term
line
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62251980A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0193927A (ja
Inventor
Kyoyoshi Itano
Koji Shinbayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP62251980A priority Critical patent/JPH0193927A/ja
Priority to DE3889188T priority patent/DE3889188D1/de
Priority to US07/253,515 priority patent/US4893033A/en
Priority to EP88116483A priority patent/EP0311046B1/en
Priority to KR1019880012988A priority patent/KR920000838B1/ko
Publication of JPH0193927A publication Critical patent/JPH0193927A/ja
Publication of JPH0543215B2 publication Critical patent/JPH0543215B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
JP62251980A 1987-10-06 1987-10-06 プログラム可能な論理回路 Granted JPH0193927A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62251980A JPH0193927A (ja) 1987-10-06 1987-10-06 プログラム可能な論理回路
DE3889188T DE3889188D1 (de) 1987-10-06 1988-10-05 Programmierbares logisches Feld.
US07/253,515 US4893033A (en) 1987-10-06 1988-10-05 Programmable logic array having input transition detection for generating precharge
EP88116483A EP0311046B1 (en) 1987-10-06 1988-10-05 Programmable logic array circuit
KR1019880012988A KR920000838B1 (ko) 1987-10-06 1988-10-05 프로그램이 가능한 논리 어레이 회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62251980A JPH0193927A (ja) 1987-10-06 1987-10-06 プログラム可能な論理回路

Publications (2)

Publication Number Publication Date
JPH0193927A JPH0193927A (ja) 1989-04-12
JPH0543215B2 true JPH0543215B2 (enExample) 1993-07-01

Family

ID=17230863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62251980A Granted JPH0193927A (ja) 1987-10-06 1987-10-06 プログラム可能な論理回路

Country Status (5)

Country Link
US (1) US4893033A (enExample)
EP (1) EP0311046B1 (enExample)
JP (1) JPH0193927A (enExample)
KR (1) KR920000838B1 (enExample)
DE (1) DE3889188D1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4831285A (en) * 1988-01-19 1989-05-16 National Semiconductor Corporation Self precharging static programmable logic array
JP2561167B2 (ja) * 1989-04-18 1996-12-04 三菱電機株式会社 バス回路
US5057712A (en) * 1989-09-29 1991-10-15 Advanced Micro Device, Inc. Address transition detector for programmable logic array
US5305268A (en) * 1990-12-13 1994-04-19 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with column equilibrate on change of data during a write cycle
US5160860A (en) * 1991-09-16 1992-11-03 Advanced Micro Devices, Inc. Input transition responsive CMOS self-boost circuit
US5189320A (en) * 1991-09-23 1993-02-23 Atmel Corporation Programmable logic device with multiple shared logic arrays
US5221867A (en) * 1991-10-11 1993-06-22 Intel Corporation Programmable logic array with internally generated precharge and evaluation timing
JP2944368B2 (ja) * 1993-07-07 1999-09-06 株式会社東芝 半導体集積回路及びプログラマブルロジックデバイス
DE69422794T2 (de) * 1994-02-18 2000-06-08 Stmicroelectronics S.R.L., Agrate Brianza Programmierbare logische Feldstruktur für nichtflüchtige Halbleiterspeicher, insbesondere Flash-EPROMS
GB9426335D0 (en) * 1994-12-29 1995-03-01 Sgs Thomson Microelectronics A fast nor-nor pla operating from a single phase clock
US5550490A (en) * 1995-05-25 1996-08-27 International Business Machines Corporation Single-rail self-resetting logic circuitry
US5717355A (en) * 1995-12-11 1998-02-10 International Business Machines Corporation Method and apparatus with active feedback for shifting the voltage level of a signal
US5818280A (en) * 1995-12-11 1998-10-06 International Business Machines Corporation Method and apparatus with preconditioning for shifting the voltage level of a signal
US5717344A (en) * 1996-02-20 1998-02-10 International Business Machines Corporation PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output
US5867038A (en) * 1996-12-20 1999-02-02 International Business Machines Corporation Self-timed low power ratio-logic system having an input sensing circuit
US10262732B2 (en) 2017-08-03 2019-04-16 Winbond Electronics Corp. Programmable array logic circuit and operating method thereof
JP2019121268A (ja) * 2018-01-10 2019-07-22 キヤノン株式会社 電子機器およびその制御方法ならびにプログラム

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile
DE2446655A1 (de) * 1974-09-30 1976-04-01 Siemens Ag Integrierte, programmierbare logikanordnung
US4355377A (en) * 1980-06-30 1982-10-19 Inmos Corporation Asynchronously equillibrated and pre-charged static ram
US4581548A (en) * 1983-03-15 1986-04-08 Harris Corporation Address decoder
US4577190A (en) * 1983-04-11 1986-03-18 At&T Bell Laboratories Programmed logic array with auxiliary pull-up means to increase precharging speed
US4740721A (en) * 1985-10-21 1988-04-26 Western Digital Corporation Programmable logic array with single clock dynamic logic
JPS62190926A (ja) * 1986-02-18 1987-08-21 Matsushita Electric Ind Co Ltd ダイナミツクｐｌａ回路
CA1257343A (en) * 1986-07-02 1989-07-11 Robert C. Rose Self-timed programmable logic array with pre-charge circuit
US4697105A (en) * 1986-07-23 1987-09-29 American Telephone And Telegraph Company, At&T Bell Laboratories CMOS programmable logic array
IT1195119B (it) * 1986-08-04 1988-10-12 Cselt Centro Studi Lab Telecom Perfezionamenti alle schiere logi che programmabili dinamiche a struttura nor nor realizzate in tecnolo gia c mos
JP2554475B2 (ja) * 1986-09-11 1996-11-13 株式会社リコー プログラマブル・ロジツク・デバイス
US4760290A (en) * 1987-05-21 1988-07-26 Vlsi Technology, Inc. Synchronous logic array circuit with dummy signal lines for controlling "AND" array output
US4831285A (en) * 1988-01-19 1989-05-16 National Semiconductor Corporation Self precharging static programmable logic array

Also Published As

Publication number Publication date
EP0311046A2 (en) 1989-04-12
DE3889188D1 (de) 1994-05-26
KR890007505A (ko) 1989-06-20
JPH0193927A (ja) 1989-04-12
EP0311046B1 (en) 1994-04-20
EP0311046A3 (en) 1989-08-30
KR920000838B1 (ko) 1992-01-30
US4893033A (en) 1990-01-09

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