JPH054281Y2 - - Google Patents

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Publication number
JPH054281Y2
JPH054281Y2 JP1987148200U JP14820087U JPH054281Y2 JP H054281 Y2 JPH054281 Y2 JP H054281Y2 JP 1987148200 U JP1987148200 U JP 1987148200U JP 14820087 U JP14820087 U JP 14820087U JP H054281 Y2 JPH054281 Y2 JP H054281Y2
Authority
JP
Japan
Prior art keywords
wires
transistor
wire
microwave
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987148200U
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English (en)
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JPS6454333U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Priority to JP1987148200U priority Critical patent/JPH054281Y2/ja
Publication of JPS6454333U publication Critical patent/JPS6454333U/ja
Application granted granted Critical
Publication of JPH054281Y2 publication Critical patent/JPH054281Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49425—Wedge bonds
    • H01L2224/49426—Wedge bonds on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Wire Bonding (AREA)
  • Microwave Amplifiers (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は高周波で高利得、広帯域の出力を必要
とするマイクロ波ICの改良に関する。
〔従来の技術〕
半導体チツプ例えばGaAsの電界効果トランジ
スタチツプを搭載したハイブリツドICにおいて、
特に高周波で高利得、広帯域の出力を要求される
マイクロ波ICは、トランジスタの内部インピー
ダンス、入力回路のインピーダンス、その他ワイ
ヤーなどの寄生素子量を考慮に入れて設計され
る。このうち高周波特性に最も影響を与えるのは
入力回路とトランジスタのマツチングであり、入
力基板上の信号ラインとトランジスタをワイヤー
で接続した場合、高周波ではワイヤーのインダク
タンスの寄生素子量が問題となる。
第３図は従来におけるマイクロ波ICの入力基
板上の信号ラインとトランジスタの接続構造を示
しており、パツケージ３の一部３ａにGaAs電界
効果トランジスタ１を搭載し、このトランジスタ
１のゲート電極１ａを入力側の基板４の信号ライ
ンパターン４ａに、またドレイン電極１ｂを出力
側の基板５の信号ラインパターン５ａに夫々ワイ
ヤ７によつて接続している。なお、１ｃはソース
電極である。
〔考案が解決しようとする問題点〕
上述した従来のマイクロ波ICは、特にトラン
ジスタ１のゲート電極１ａと入力側の基板４の信
号ラインパターン４ａとをワイヤ７で接続する際
に、ゲート電極１ａの寸法と使用するワイヤー７
の径寸法の制限より、その接続はワイヤー１本で
接続されている。このため、特に高周波において
ワイヤ７のインダクタンスによるリアクタンス量
が大きくなり、入力回路とトランジスタの負荷回
路のマツチングがずれて、出力としての利得が低
下したり周波数帯域が延びなくなり、要求される
電気特性が得られない問題があつた。
本考案は、ワイヤのリアクタンス量を低減して
利得の向上や周波数帯域の向上を図つたマイクロ
波ICを提供することを目的としている。
〔問題点を解決するための手段〕
本考案のマイクロ波ICは、マイクロ波ICにお
る半導体素子チツプの電極と回路基板の信号ライ
ンパターンとを複数本のワイヤで並列接続し、か
つこれらワイヤは半導体素子チツプの電極に接続
される端部で重ねた状態で接続し、ワイヤのイン
ダクタンスによるリアクタンス量の低減を図つて
いる。
〔実施例〕
次に、本考案を図面を参照して説明する。
第１図は本考案を30GHz帯の２段アンプに適用
した実施例の概略斜視図であり、第２図はその一
部の拡大図である。
第１図において、パツケージ３上には入力基板
４、中間基板５及び出力基板６を適宜間隔おいて
配設し、かつこれらの間に位置するパツケージ３
ａ上には夫々GaAs電界効果トランジスタ１，２
を搭載している。第２図に一方のトランジスタ１
を拡大図示するように、トランジスタ１のゲート
電極１ａを前記入力基板４の信号ラインパターン
４ａにワイヤ７で接続し、ドレイン電極１ｂを出
力側の前記中間基板５の信号ラインパターン５ａ
にワイヤ７′で接続している。そして、ゲート電
極１ａに接続するワイヤ７は、ゲート電極１ａ上
で２本のワイヤ７，７の各一端を重ね打ちし、各
他端は夫々個別に信号ラインパターン４ａに接続
し、その平面形状をＶ字形に構成している。この
場合、ワイヤ７，７はゲート電極１ａ上では重ね
打ちしているため、ゲート電極１ａの寸法が小さ
いのにもかかわらず２本のワイヤ接続が可能とな
る。
なお、これはトランジスタ２においても同様で
ある。
この構成によれば、トランジスタのゲート電極
をＶ字形にワイヤ接続しているため、ワイヤで生
ずるリアクタンス量を従来より約30〜40％低減す
ることができる。このため、入力回路の入力イン
ピーダンスとトランジスタの負荷インピーダンス
のマツチングの向上が図れ、高周波出力として利
得の向上、周波数帯域を広げることができる。
例えば第１図の30GHzの２段アンプにおいて、
周波数帯域27.4GHz〜29.5GHzで利得7dB以上、振
幅特性で帯域内偏差1.5dBの要求性能を満足する
ことができる。
なお、本考案は電界効果トランジスタ以外の半
導体素子チツプを搭載する場合にも同様に適用す
ることができる。
〔考案の効果〕
以上説明したように本考案は、半導体素子チツ
プの電極と回路基板の信号ラインパターンとを複
数本のワイヤで並列接続し、かつこれらワイヤは
半導体素子チツプの電極に接続される端部で重ね
た状態で接続しているので、ワイヤのリアクタン
ス量を大幅に低減でき、入力回路の入力インピー
ダンスとトランジスタの負荷インピーダンスのマ
ツチングをとり、高周波出力として利得の向上を
図るとともに、周波数帯域を拡大を図ることがで
き、要求される電気特性を満足させることが可能
となる。
【図面の簡単な説明】
第１図は本考案を適用したマイロ波ICの概略
斜視図、第２図はそのトランジスタ部分の拡大斜
視図、第３図は従来のマイクロ波ICのトランジ
スタ部分の拡大斜視図である。 １，２……電界効果トランジスタ、１ａ……ゲ
ート電極、１ｂ……ドレイン電極、１ｃ……ソー
ス電極、３……パツケージ、４……入力基板、５
……中間基板、６……出力基板、７，７′……ワ
イヤ。

Claims (1)

    【実用新案登録請求の範囲】
  1. パツケージ上に搭載した半導体素子チツプと回
    路基板とをワイヤで接続したマイクロ波ICにお
    いて、前記半導体素子チツプの電極と回路基板の
    信号ラインパターンとを複数本のワイヤで並列接
    続し、かつこれらワイヤは半導体素子チツプの電
    極に接続される端部で重ねた状態で接続したこと
    を特徴とするマイクロ波IC。
JP1987148200U 1987-09-30 1987-09-30 Expired - Lifetime JPH054281Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987148200U JPH054281Y2 (ja) 1987-09-30 1987-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987148200U JPH054281Y2 (ja) 1987-09-30 1987-09-30

Publications (2)

Publication Number Publication Date
JPS6454333U JPS6454333U (ja) 1989-04-04
JPH054281Y2 true JPH054281Y2 (ja) 1993-02-02

Family

ID=31419305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987148200U Expired - Lifetime JPH054281Y2 (ja) 1987-09-30 1987-09-30

Country Status (1)

Country Link
JP (1) JPH054281Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010161348A (ja) * 2008-12-10 2010-07-22 Toshiba Corp 高周波半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010161348A (ja) * 2008-12-10 2010-07-22 Toshiba Corp 高周波半導体装置
JP2015015496A (ja) * 2008-12-10 2015-01-22 株式会社東芝 高周波半導体装置

Also Published As

Publication number Publication date
JPS6454333U (ja) 1989-04-04

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