JPH05343919A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the required layout area and to make the operation stable for an oscillation circuit built in a microcomputer or the like. CONSTITUTION:In a microcomputer MC where an oscillation circuit OSC is built in, a crystal oscillator XO is mounted externally and external terminals XTAL and EXTAL are provided, the output of an inverter INV1 is coupled with the terminal EXTAL and acts like a static electricity protection element. Moreover, both transistors(TRs) PM1, NM1 being components of the INV1 are arranged closely and symmetrically to a bonding pad PEXTAL corresponding to the terminal EXTAL. Moreover, a feedback resistor Rf provided between an input terminal and an output terminal of the INV1 and TRs PM2, PM3 and NM2, NM3 being components of the inverter INV2 transmitting its output signal to a post-stage circuit are arranged closely and symmetrically to the TRs PM1, NM1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective when used in a microcomputer having an oscillation circuit.

[0002]

2. Description of the Related Art There is a microcomputer including an oscillation circuit for forming a clock signal and having a pair of external terminals to which a crystal oscillator for setting the oscillation frequency of the oscillation circuit is externally attached.

For a microcomputer including an oscillation circuit and specifications regarding the oscillation circuit, see, for example, "H8" issued by Hitachi, Ltd. in August 1990.
/ 510 HD6415108 Hardware Manual, pp. 127-129.

[0004]

In the conventional microcomputer described above, the built-in oscillating circuit is, for example, as shown in FIG. 8, an inverter serving as a drive element for an externally attached crystal oscillator XO. INV1
And a feedback resistor Rf provided between the input terminal and the output terminal of the inverter INV1. As shown in FIG. 9, the inverter INV1 includes a P-channel MOSFET (metal oxide semiconductor type field effect transistor. In this specification, MOSFET is a generic term for an insulated gate field effect transistor) PM1 and N-channel MOSFET NM1. CMOS (complementary M
OS) logic circuit having its input terminal and external terminal XT
Between AL and its output terminal and external terminal EXTAL
And a pair of diodes D1 and D2 or D
Electrostatic protection circuits ESD1 and ESD2 composed of 3 and D4 and a protection resistor Rs1 or Rs2 are provided, respectively.
Relatively large capacitors CL1 and CL2 for stabilizing the oscillation operation of the crystal oscillator XO are coupled between the external terminals XTAL and EXTAL and the ground potential of the circuit, respectively.

However, it has been made clear by the inventors of the present application that the conventional oscillator circuit OSC described above has the following problems as the degree of integration and speed of the microcomputer increases. That is, the crystal oscillator XO
As described above, the output terminal of the inverter INV1 that serves as a drive element of the inverter INV1 is coupled to the external terminal EXTAL via the protection resistor Rs3 included in the electrostatic protection circuit ESD2, which reduces the substantial drive capability of the inverter INV1. To do. In order to deal with this, the drive capacity of the inverter INV1 must be increased more than necessary, but this increases the current consumption of the inverter INV1 and increases the required layout area. Further, in the conventional oscillation circuit OSC, in addition to the inverter INV1 serving as a drive element, an inverter INV2 for transmitting an output signal of the inverter INV1 as a clock signal φ0 to an internal circuit of the microcomputer and electrostatic protection circuits ESD1 and ESD2 are provided. Therefore, a total of 4 dedicated cells are required.

Further, the inverter INV1 requires a relatively large drive capacity for driving a relatively large external capacitance CL2, and its output terminal and external terminal EX.
The wiring layer for coupling with the TAL also needs to have a relatively large line width in order to suppress the resistance value. However, the P-channel MOSFETs PM1 and NM1 forming the inverter INV1 are externally connected to each other as shown in FIG. Terminal EXT
A P-channel MOSFET PM7 and an N-channel MOSFET at least forming the electrostatic protection circuit ESD2 when viewed from the bonding pad PEXTAL corresponding to AL
Since it is arranged far from NM7, the total wiring length of the oscillation circuit including the wiring between the inverter INV1 and the external terminal EXTAL becomes long. This means that the oscillator circuit OSC
The required layout area is further increased, and the oscillation operation of the oscillation circuit OSC becomes unstable due to coupling noise between wirings, power supply noise, and the like.

An object of the present invention is to reduce the required layout area of an oscillation circuit incorporated in a microcomputer or the like and stabilize its operation.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in a microcomputer or the like having a pair of external terminals for incorporating a crystal oscillator in which an oscillator circuit is built-in, a first CMOS logic circuit provided as a drive element for the crystal oscillator is provided with a static circuit for a corresponding external terminal. Also serves as an electrical protection element. In addition, the output terminal of the first CMOS logic circuit is directly coupled to the corresponding external terminal, and the P-channel and N-channel MOSFETs forming the first CMOS logic circuit are placed close to the bonding pad corresponding to the external terminal. And a second CMOS for symmetrically arranging a feedback resistor provided between an input terminal and an output terminal of the first CMOS logic circuit and for transmitting an output signal of the first CMOS logic circuit to a subsequent circuit of the microcomputer. P-channel and N-channel MOSFE configuring a logic circuit
The Ts are respectively arranged close to and symmetrical to the P-channel and N-channel MOSFETs that form the first CMOS logic circuit.

[0010]

According to the above means, the protective resistance provided between the output terminal of the first CMOS logic circuit and the corresponding external terminal is eliminated, and the driving capability of the first CMOS logic circuit is correspondingly reduced. You can In addition, the wiring between the output terminal of the first CMOS logic circuit and the corresponding external terminal can be shortened and the wiring resistance thereof can be reduced to further reduce the driving capability of the first CMOS logic circuit. The total wiring length of the oscillation circuit can be shortened, and the coupling noise and power supply noise between these wirings can be suppressed. As a result, the required layout area of the oscillator circuit can be reduced and its operation can be stabilized.

[0011]

1 is a partial block diagram of an embodiment of a microcomputer MC to which the present invention is applied. An outline of the configuration and operation of the microcomputer MC of this embodiment will be described first with reference to FIG. The circuit elements forming each block in FIG. 1 are formed on one semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. Further, the microcomputer MC includes many functional blocks not shown in the figure, but the description of these functional blocks is omitted because it is not directly related to the present invention.

In FIG. 1, a microcomputer MC of this embodiment has an oscillation circuit OSC for forming a clock signal φ0 built therein and a crystal oscillator XO (oscillator) for setting the oscillation frequency of the oscillation circuit OSC. ) Is externally attached to a pair of external terminals XTAL (first external terminal) and EXTAL (second external terminal). Crystal oscillator X
Although not particularly limited, O is composed of a so-called AT cut parallel resonance type crystal oscillator and has an inherent resonance frequency.
Further, capacitors CL1 and CL2 for stabilizing the oscillation operation of the crystal oscillator XO are externally attached between the external terminals XTAL and EXTAL and the ground potential of the circuit, respectively.
These capacitors have a relatively large electrostatic capacitance of, for example, 10 to 20 pF (picofarad).

The clock signal φ0 output from the oscillator circuit OSC is not particularly limited, but is supplied to the frequency dividing circuit FD1 and output from the frequency dividing circuit FD1.
Is supplied to the frequency dividing circuit FD2. The clock signal φ2 output from the frequency dividing circuit FD2 is supplied as an operation clock to a subsequent circuit (not shown) of the microcomputer MC. The frequency dividing circuits FD1 and FD2 each have a basic circuit of a counter circuit of a predetermined bit, and have a clock signal φ0.
And φ1 are divided into ½ and ⅛, respectively, to form clock signals φ1 and φ2, respectively.

FIG. 2 shows the microcomputer M of FIG.
A functional diagram of an embodiment of the oscillator circuit OSC included in C is shown, and a circuit diagram of the embodiment is shown in FIG.
Based on these figures, the specific configuration and operation of the oscillator circuit OSC included in the microcomputer MC of this embodiment and its characteristics will be described. In the following circuit diagram, the MOSFET whose channel (back gate) part has an arrow is a P-channel type (first conductivity type), and the MOSFET without an arrow is an N-channel type (second conductivity type).
(Conductivity type) MOSFET is shown separately.

In FIG. 2, the oscillator circuit OSC includes an inverter INV1 (first CMOS logic circuit) which acts as a drive element for the crystal oscillator XO, although not particularly limited thereto. As shown in FIG. 3, the inverter INV1 is a so-called output inversion type CM including a P-channel MOSFET PM1 and an N-channel MOSFET NM1.
The OS logic circuit has a relatively large driving capability by making the size of these MOSFETs relatively large. The input terminal of the inverter INV1 has an electrostatic protection circuit E
It is coupled to the external terminal XTAL via SD1, and its output terminal is directly coupled to the external terminal EXTAL.

Here, the electrostatic protection circuit ESD1 has a predetermined protection resistor Rs1 provided between the input terminal of the inverter INV1 and the external terminal XTAL, and between the external terminal XTAL and the power supply voltage and ground potential of the circuit. It includes diodes D1 and D2 respectively provided. Of these, the protection resistor Rs1 is made of a diffusion resistor as described later, and has a relatively small resistance value of, for example, about 100 Ω (ohm). Further, as shown in FIG. 3, the diodes D1 and D2 are P-channel MOSFETs in a diode form by having their gates and sources commonly coupled.
The TPM4 and the N-channel MOSFET NM4 are configured to absorb the high-voltage static electricity applied to the external terminal XTAL to prevent the gate breakdown of the P-channel MOSFETs PM1 and NM1 that form the inverter INV1. The power supply voltage of the circuit is not particularly limited,
It is a positive power supply voltage such as + 5V.

The output terminal of the inverter INV1, that is, the external terminal EXTAL is further coupled to the input terminal of the inverter INV2 (second CMOS logic circuit) via a predetermined protection resistor Rs2. The output signal of the inverter INV2 is supplied to the subsequent circuit, that is, the frequency dividing circuit FD1 as the clock signal φ0 as described above. A predetermined feedback resistor Rf is provided between the input terminal of the inverter INV1 and the input terminal of the inverter INV2. The inverter INV2 is composed of a P-channel MOSFET PM2 and an N-channel MOSFET NM2, as shown in FIG. Further, as will be described later, the protection resistor Rs2 is a relatively small diffusion resistor of, for example, about 100Ω and is a P-channel MOSFET.
It works to prevent the gate breakdown of the PM2 and the N-channel MOSFET NM2 and to absorb the noise inputted through the external terminal EXTAL. Further, the feedback resistor Rf is composed of a pair of P-channel MOSFET PM3 and N-channel MOSFET NM3 which are connected in parallel and whose gates are constantly turned on by receiving the power supply voltage or ground potential of the circuit. It has a relatively large resistance value of about 1 MΩ (mega ohm). As a result, the feedback resistance R
The required layout area as f can be reduced, and
It is possible to suppress the coupling noise via the related wiring and the like.

From these things, the inverter INV1
Inverts and amplifies a minute piezoelectric signal obtained at the external terminal XTAL by the resonance of the crystal oscillator XO, and the external terminal EXT
AL, that is, acts as a drive element that feeds back to the other electrode of the crystal oscillator XO, and the feedback resistor Rf acts to determine the operating point of the inverter INV1 by feeding back the output signal of the inverter INV1 to its input terminal. .. In this embodiment, the output terminal of the inverter INV1 is directly connected to the corresponding external terminal EX as described above.
Bound to TAL. Therefore, the inverter INV1
Acts as an electrostatic protection element with the P-channel MOSFET PM1 and the N-channel MOSFET NM1, absorbs the high-voltage static electricity applied to the external terminal EXTAL, and forms the P-channel MOSFET PM2 and the N-channel MOSFET NM constituting the inverter INV2.
2. Prevent gate breakdown. In addition, the inverter INV1
Requires a large driving capability capable of driving a relatively large capacitance CL2 coupled to the external terminal EXTAL.
By directly coupling the output terminal to the external terminal EXTAL without passing through the protective resistance, the driving capability can be reduced accordingly. As a result, the dedicated electrostatic protection circuit provided between the input terminal of the inverter INV1 and the external terminal EXTAL in the conventional oscillation circuit OSC is not required, and the size of the inverter INV1 which is a drive element is reduced. Therefore, the required layout area of the oscillator circuit OSC is reduced.

FIG. 4 shows a layout of an embodiment of the oscillator circuit OSC of FIG. The specific layout and features of the oscillator circuit OSC of this embodiment will be described with reference to FIG. The N-channel MOSFET that constitutes each circuit element of the oscillation circuit OSC has an N-type diffusion layer formed directly on the P-type semiconductor substrate as a source and a drain, and the P-channel MOSFET is an N-type on the P-type semiconductor substrate. The P-type diffusion layer formed in the well region is used as its source and drain. In the layouts below, the thin well line represents the N-type well region, the thin solid line represents the diffusion layer and the gate layer, and the thick solid line represents the aluminum wiring layer. Further, in the following description, the upper and lower sides and left and right sides of the semiconductor substrate surface are represented by the positional relationship in the layout diagram.

In FIG. 4, a bonding pad PXTAL corresponding to the external terminal XTAL and an external terminal EXTAL are formed on the P-type semiconductor substrate on which the oscillator circuit OSC is formed.
Corresponding to the bonding pad PEXTAL. Of these, an N-type well region NWELL2 is formed on the right side of the bonding pad PXTAL.
A P-type diffusion layer PD4 serving as a source and a drain of a P-channel MOSFET PM4 forming the electrostatic protection circuit ESD1 is formed in the mold well region in the vicinity of the bonding pad PXTAL. P-channel MOSFET
Between the source and the drain of PM4, that is, on the channel thereof, a gate layer FG4P serving as the gate is formed of polysilicon or the like with a predetermined insulating film interposed therebetween. P
The source and gate of the channel MOSFET PM4 are
Power supply voltage VC of the circuit via the aluminum wiring layer AL8
C is connected to the drain of the aluminum wiring layer A
It is coupled to the bonding pad PXTAL via L4.

On the other hand, on the left side of the bonding pad PXTAL, close to the bonding pad PXTAL and P
Type diffusion layer PD4, that is, P-channel MOSFET PM
4, an N-type diffusion layer ND4 serving as a source and a drain of the N-channel MOSFET NM4 forming the electrostatic protection circuit ESD1 is formed. N channel M
On the channel of the OSFET NM4, a gate layer FG4N which becomes the gate thereof is formed of polysilicon or the like. The source and gate of the N-channel MOSFET NM4 are coupled to the ground potential VSS of the circuit through the aluminum wiring layer AL7, and the drain thereof is coupled to the bonding pad PXTAL through the aluminum wiring layer AL3. Further, the left side of the N-type diffusion layer ND4 serving as the drain of the N-channel MOSFET NM4 is further extended to the upper left side to form a diffusion resistance, and the electrostatic protection circuit ESD1
Protection resistance Rs1.

Next, an N type well region NWELL1 is formed on the left side of the bonding pad PEXTAL, and the bonding pad PEXT is formed in this N type well region.
A P-type diffusion layer PD1 serving as a source and a drain of the P-channel MOSFET PM1 forming the inverter INV1 is formed near the AL. P channel MOSF
The gate layer FG1P is formed of polysilicon or the like on the channel of the ETPM1. P channel MOSF
The source of ETPM1 is coupled to the power supply voltage VCC of the circuit through the aluminum wiring layer AL5, and the drain thereof is coupled to the bonding pad PEXTAL through the aluminum wiring layer AL1.

On the other hand, on the right side of the bonding pad PEXTAL, the P-type diffusion layer PD1 that is close to the bonding pad PEXTAL, that is, the P-channel MOSFET is provided.
An N-type diffusion layer ND1 serving as a source and a drain of the N-channel MOSFET NM1 forming the inverter INV1 is formed at a position symmetrical to PM1. On the channel of the N-channel MOSFET NM1, a gate layer FG1N to be its gate is formed of polysilicon or the like. The source of the N-channel MOSFET NM1 is coupled to the ground potential VSS of the circuit through the aluminum wiring layer AL6, and the drain thereof is the aluminum wiring layer AL2.
To the bonding pad PEXTAL via. Further, the right side of the N-type diffusion layer ND1 serving as the drain of the N-channel MOSFET NM1 is further extended to the upper right to form a diffusion resistance, which serves as a protection resistance Rs2 for the inverter INV2.

Above the P-type diffusion layer PD1 in the N-type well region NWELL1, in proximity to the P-type diffusion layer PD1, a P-channel M forming a feedback resistance Rf.
A P-type diffusion layer PD3 serving as the source and drain of the OSFET PM3 is formed. Further, above the N-type diffusion layer ND1 and in the vicinity of the N-type diffusion layer ND1 and at a position symmetrical to the P-type diffusion layer PD3, the source and drain of the N-channel MOSFET NM3 also forming the feedback resistance Rf are formed. The N-type diffusion layer ND3 is formed.
On the channels of the P-channel MOSFETs PM3 and NM3, gate layers FG3P and FG3N which become the gates of these MOSFETs are formed of polysilicon or the like. In addition, as is apparent from FIG. 4, the P channel M
OSFET PM3 and N-channel MOSFET NM3
Is formed so that its gate length is relatively large and its gate width is relatively small, so that it has a relatively large resistance value of 1 MΩ.

The source of the P-channel MOSFET PM3 forming the feedback resistor Rf and the drain of the N-channel MOSFET NM3 are formed on the gate layer FG1P of the P-channel MOSFET PM1 forming the inverter INV1 and the gate layer FG1N of the N-channel MOSFET NM1 via the aluminum wiring layer AL9. It is further coupled to the other of the protection resistors Rs1. The drain of the P-channel MOSFET PM3 and the source of the N-channel MOSFET NM3 are
The protection resistor Rs is provided through the aluminum wiring layer AL10.
It is coupled to the other of the two, and further coupled to the gate layer FG2 of the P-channel MOSFET PM2 and the N-channel MOSFET NM2 which form the inverter INV2. P
The gate layer FG3P of the channel MOSFET PM3 is
The N-channel MOSFET NM3 is coupled to the ground potential VSS of the circuit through an aluminum wiring layer (not shown).
Gate layer FG3N is coupled to the power supply voltage VCC of the circuit via another aluminum wiring layer (not shown). As a result, the P-channel MOSFET PM3 and the N-channel MOSFET NM3 are constantly turned on and act as a feedback resistor Rf having a resistance value corresponding to the source / drain resistance thereof.

Next, the P-channel MOSFET PM2 forming the inverter INV2 is connected to the N-type well region NWE.
A P-type diffusion layer PD3, that is, a P-channel MO in LL1.
P-type diffusion layer PD2 arranged close to SFETPM3
As its source and drain. Also, an N-channel MOSFET NM which also constitutes the inverter INV2
2 is an N-type diffusion layer ND3, that is, an N-channel MOSF
The N-type diffusion layer ND2 arranged near the ETNM3 and at a position symmetrical to the P-type diffusion layer PD2, that is, the P-channel MOSFET PM2 is used as the source and drain thereof.
The source of the P-channel MOSFET PM2 is coupled to the circuit power supply voltage VCC through the aluminum wiring layer AL11, and the source of the N-channel MOSFET NM2 is
Ground potential V of the circuit via the aluminum wiring layer AL12
It is connected to SS. In addition, P-channel MOSFETP
The drains of the M2 and the N-channel MOSFET NM2 are coupled to a subsequent circuit (not shown) via the aluminum wiring layer AL13, and the gate layer FG2 serving as the gates of these MOSFETs has the P-channel via the aluminum wiring layer AL10 as described above. MOSFET PM3
Of the N channel MOSFET NM3.

As described above, the oscillator circuit OS of this embodiment
In C, the P channel M that constitutes the inverter INV1
OSFET PM1 and N-channel MOSFET NM1
Of the P channel M, which is arranged symmetrically and close to the bonding pad PEXTAL corresponding to the external terminal EXTAL and which constitutes the feedback resistor Rf.
OSFET PM3 and N-channel MOSFET NM3
And the P channel M that constitutes the inverter INV2
OSFET PM2 and N-channel MOSFET NM2
Are arranged close to the corresponding P-channel MOSFET PM1 and N-channel MOSFET NM1, respectively, and symmetrically arranged. However, the inverter INV1
Of the output terminal and the external terminal EXTAL, that is, the bonding pad PEXTAL is shortened, the wiring resistance is correspondingly reduced, and the oscillation circuit OS
The total wiring length in C is reduced, and coupling noise and power supply noise between these wirings are suppressed. As a result, the inverter INV1 and thus the oscillation circuit OS
The required layout area of C is further reduced, and the oscillation circuit O
The operation as the SC is stabilized.

By applying the present invention to a semiconductor device such as a microcomputer incorporating an oscillation circuit as shown in the above embodiment, the following operational effects can be obtained. That is, (1) In a microcomputer or the like having a pair of external terminals to which a crystal oscillator is externally mounted and which has an oscillation circuit,
First provided as a driving element for a crystal oscillator in an oscillation circuit
Of the first CMOS logic circuit by directly connecting the output terminal of the first CMOS logic circuit to the corresponding external terminal by also using the CMOS logic circuit as a static electricity protection element for the corresponding external terminal. It is possible to eliminate the protection resistance provided between the corresponding external terminal and the driving capability of the first CMOS logic circuit, which is the driving element, by that much.

(2) In the above item (1), the first CM
By arranging the P-channel and N-channel MOSFETs forming the OS logic circuit in close proximity to the corresponding bonding pad and symmetrically, the wiring length between the output terminal and the corresponding bonding pad is shortened, and the wiring resistance is reduced. Can be reduced to further reduce the driving capability of the first CMOS logic circuit. (3) In the above (1) and (2), the first CM
A feedback resistor provided between the input terminal and the output terminal of the OS logic circuit and a P channel and an N channel forming a second CMOS logic circuit for transmitting the output signal of the first CMOS logic circuit to the internal circuit of the microcomputer. A MOSFET is a P-channel and N-channel MOSFE which constitutes a first CMOS logic circuit.
By arranging them close to T and symmetrically with respect to each other, it is possible to obtain an effect that the total wiring length as the oscillation circuit can be shortened and the coupling noise and the power supply noise between these wirings can be suppressed. (4) According to the above items (1) to (3), the required layout area of the oscillation circuit can be reduced and the operation thereof can be stabilized.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the microcomputer MC can include one or three or more frequency dividing circuits, and the frequency dividing ratio and connection form of each frequency dividing circuit are not limited by this embodiment. The crystal oscillator XO coupled to the external terminals XTAL and EXTAL does not particularly need to be the AT cut parallel resonance type, and an oscillator other than a crystal can be used. Specific capacitance values of the capacitors CL1 and CL2 provided between the external terminals XTAL and EXTAL and the ground potential of the circuit can be arbitrarily set.

In FIG. 2, the structure of the electrostatic protection circuit ESD1 is not restricted by this embodiment. Further, as illustrated in FIG. 5, by replacing the inverter INV1 with a 2-input NOR gate NOG1, the operation of the oscillation circuit OSC can be controlled according to the internal control signal OC. In this case, the NOR gate NOG1 is composed of P-channel MOSFETs PM5 and PM6 and N-channel MOSFETs NM5 and NM6, as shown in FIG. However, they may be arranged at symmetrical positions. The CMOS logic circuit serving as the drive element of the crystal oscillator XO can be replaced with a NAND gate, and the inverter INV2 can be replaced with various CMOS logic circuits. As the protection resistors Rs1 and Rs2, for example, polysilicon resistors or the like can be used instead of the diffusion resistors. Furthermore, the specific circuit configuration and layout of the oscillator circuit OSC, and the polarity and absolute value of the power supply voltage are
Various embodiments can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is a field of application which is the background of the invention has been described.
The present invention is not limited to this, and can be applied to, for example, a microprocessor or a gate array integrated circuit. The present invention can be widely applied to semiconductor devices having at least an oscillation circuit and an external terminal for externally attaching a crystal oscillator.

[0033]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a microcomputer or the like having a pair of external terminals for externally mounting a crystal oscillator that has a built-in oscillation circuit, the first CMOS logic circuit provided as a drive element of the crystal oscillator is provided with a corresponding external terminal Also serves as an electrical protection element. Also, the first CMO
The output terminal of the S logic circuit is directly coupled to the corresponding external terminal, and the P-channel and N-channel MOSFETs forming the first CMOS logic circuit are arranged in close proximity and symmetrically to the bonding pad corresponding to the external terminal. To do. Further, a feedback resistor provided between the input terminal and the output terminal of the first CMOS logic circuit and a P channel forming a second CMOS logic circuit for transmitting an output signal of the first CMOS logic circuit to a subsequent circuit of the microcomputer. And N-channel MOSFET,
P channel and N constituting the first CMOS logic circuit
The channel MOSFETs are arranged close to each other and symmetrically arranged with respect to each other. As a result, the protective resistance provided between the output terminal of the first CMOS logic circuit and the corresponding external terminal can be eliminated, and the drive capability of the first CMOS logic circuit can be reduced accordingly. In addition, the first CMOS
The wiring length between the output terminal and the external terminal of the logic circuit can be shortened and the wiring resistance thereof can be reduced to further reduce the driving ability of the first CMOS logic circuit, and the total wiring length of the oscillation circuit can be shortened. However, coupling noise and power supply noise between these wirings can be suppressed. As a result, the required layout area of the oscillator circuit can be reduced and its operation can be stabilized.

[Brief description of drawings]

FIG. 1 is a partial block diagram showing an embodiment of a microcomputer to which the present invention is applied.

FIG. 2 is a functional diagram showing a first embodiment of an oscillator circuit included in the microcomputer of FIG.

FIG. 3 is a circuit diagram showing an embodiment of the oscillator circuit of FIG.

FIG. 4 is a layout diagram showing an embodiment of the oscillation circuit of FIG.

5 is a functional diagram showing a second embodiment of an oscillator circuit included in the microcomputer of FIG.

6 is a circuit diagram showing an embodiment of the oscillation circuit of FIG.

FIG. 7 is a layout showing an embodiment of the oscillator circuit of FIG.

FIG. 8 is a functional diagram showing an example of an oscillator circuit included in a microcomputer developed by the inventors of the present application prior to the present invention.

9 is a circuit diagram showing an example of the oscillator circuit of FIG.

10 is a layout diagram showing an example of the oscillator circuit of FIG. 9. FIG.

[Explanation of symbols]

MC ... Microcomputer, OSC ... Oscillation circuit, FD1 to FD2 ... Frequency divider circuit, XO ... Crystal oscillator, CL1 to CL2 ... External capacitance. INV1-I
NV2 ... Inverter, ESD1 to ESD2 ... Electrostatic protection circuit, D1 to D4 ... Diode, Rf, Rs
1 to Rs3 ... Resistance. PM1 to PM7 ... P-channel MOSFET, NM1 to NM7 ... N-channel MOSFET. NWELL1 to NWELL5 ... N type well region, PD1 to PD7, PD56 ... P type diffusion layer, ND1 to ND7, ND56 ... N type diffusion layer, FG
1P to FG7P, FG1N to FG7N, FG1 to FG2
... Gate layer, AL1 to AL23 ... Aluminum wiring layer. NOG1 ... NOR gate.

Claims (5)

[Claims] 1. A first and second external terminal to which a predetermined oscillator is externally attached, and its input terminal and output terminal are the first
And a driving circuit which is respectively coupled to the second external terminal and which functions as a driving element for the oscillator and an electrostatic protection element for the second external terminal. 2. The drive circuit comprises an output inverting type first C
A MOS logic circuit, the input terminal of which is coupled to the first input terminal through a predetermined electrostatic protection circuit, and the output terminal of which is directly coupled to the second external terminal. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 3. The first and second conductivity type MOSFETs constituting the drive circuit are arranged in proximity to and symmetrically with a bonding pad corresponding to the second external terminal. The semiconductor device according to claim 2. 4. The output signal of the drive circuit is a second CM.
The signal is transmitted to the subsequent stage circuit via the OS logic circuit, and is connected to the input terminal of the second CMOS logic circuit and the second circuit.
A predetermined protection resistor is provided between the external terminal of the second CMOS logic circuit and the first CM.
4. The semiconductor device according to claim 2, wherein a predetermined feedback resistance is provided between the output terminal of the OS logic circuit and the output terminal. 5. The feedback resistance is realized by source / drain resistances of first and second conductivity type MOSFETs connected in parallel, and the feedback resistance and the second CMOS logic circuit constitute a second CMOS logic circuit. The first and second conductivity type MOSFETs are the first and second conductivity type MOSFETs that form the first CMOS logic circuit.
5. The semiconductor device according to claim 2, wherein the semiconductor device is arranged close to each other and symmetrically arranged.