JPH067440B2 - Thin film shift register circuit - Google Patents

Description

The present invention relates to a thin film shift register circuit, and more particularly to a thin film shift register circuit in an active matrix substrate with a built-in peripheral drive circuit.

Currently, as an active matrix substrate, a gate line provided on a single crystal silicon substrate, a data line, a MOS transistor and a MOS provided at an intersection of the gate line and the data line.
A peripheral drive circuit using a transistor, or a gate line, a data line provided on an insulating substrate, and a thin film transistor provided at an intersection of the gate line and the data line have been actively manufactured and manufactured on a trial basis.

By the way, in an active matrix substrate using thin film transistors provided on an insulating substrate, in order to reduce the size, increase the performance, and reduce the cost of the active matrix type crystal display device using the active matrix substrate, the thin film transistors on the active matrix substrate are used. Built-in peripheral drive circuits are required.

In a conventional shift register using a MOS transistor provided on a single crystal silicon substrate, since there is a junction capacitance between the source or drain portion and the substrate and wiring capacitance is easily added, it is not necessary to provide a malfunction prevention capacitance. There wasn't. An example thereof is shown in FIG. In the figure, 1
Reference numerals 00 and 101 denote clock lines to which clock signals having opposite phases are applied. 102 is a data input terminal, 103 is a power supply line, 110 to 113, 120 to 123, 130
To 133 etc. are MOS transistors, 114, 124 and 134 etc. are MOS capacitors using MOS transistors,
115, 125, 135 and the like are MOS transistors and MOS capacitors 111 and 114, 121 and 12, respectively.
Gates such as 4,131 and 134, 116,126,1
36 and the like are output terminals of the shift register, and the figure is an example of a single-channel dynamic shift register. FIG. 2 is an example of the voltage waveform of each part. Reference numerals 200 and 201 are clock signals applied to the clock lines 100 and 101, 202 is a data signal applied to the data input terminal 102, 203 is a signal waveform observed at the gate 115 of the MOS transistor 111 and the MOS capacitor 114, and 204 is a shift. Signal waveform observed at register output terminal 116,
205 is a MOS transistor 121 and a MOS capacitor 12
4 is a signal waveform observed at the gate 125, 206 is a signal waveform observed at the shift register output terminal 126, 20
Reference numeral 7 is a signal waveform observed at the gate 135 of the MOS transistor 131 and the MOS capacitor 134. The figure shows an example of driving a P-channel dynamic shift register. In FIG. 1, one bit of a shift register is formed by the MOS transistors 110 to 113 and the MOS capacitor 114. Here, the MOS transistor 11
Consider a situation in which wiring capacitance is not added to the common gate 115 such as 1 and the MOS capacitor 114, and there is no junction capacitance between the source or drain portion such as 111 and 114 and the substrate. M
The OS transistor 111 and the MOS capacitor 114 have an overlapping capacitance of the source or drain portion and the gate portion. Considering the operation at time t ₄ in FIG. 2,
The potential of the clock line 100 rises from low to high,
The MOS transistor 110 becomes non-conductive. Further, the potential of the clock line 101 becomes low, and the potential of 115 drops to the low potential because of the overlapping capacitance. Then M
Since the OS transistor 111 is conductive, the potential of the output terminal 116 is lowered, and the MOS transistor 120 is conductive, the MOS transistor 121 and the MOS capacitor 1
The potential of the common gate 125 of 24 drops. Therefore t ₄
During the period from t ₅ to t ₅ , the potential of the output terminal 116 becomes low.
Then, during the period from t _{5 to} t _6, etc., the output terminal 126, M
The potential of the common gate 135 of the OS transistor 131 and the MOS capacitor 134 drops. Although the shift register of FIG. 1 malfunctions due to the above mechanism, in reality, the common gate 11 of the MOS transistor and the MOS capacitor is used.
5,125,135 and the like and a power supply (the potential supplied to the power supply line 103) wiring capacitance is added between, for MOS transistors and the source or drain portion and the junction capacitance between the source of the MOS capacitor is present, _{t 4} to MOS during t ₅ etc.
The potential drop of the common gate 115 of the transistor and the MOS capacitor is suppressed. The potential drop of 115 and the like is Vd, the voltage amplitude of the clock is V, the overlapping capacitance of 115 and 111 and 114 and the like is Cg, the junction capacitance between the source or drain part and the power supply of 111 and 114 and the 115 and the power supply When the sum of wiring capacitances added between is Cs, the potential drop Vd of 115 or the like is expressed by Vd = Cg.V / (Cg + Cs). Therefore, the malfunction as described above does not occur. Therefore, in the conventional shift register using the MOS transistor, the Pn junction region and the wiring region play the role of the malfunction preventing capacitance, and it is not necessary to provide a special capacitance. However, in a thin film integrated circuit, the substrate is generally insulated, and there is no capacitance due to the Pn junction region,
No capacitance is added to the wiring area.

An object of the present invention is to provide a capacitor in a thin film shift register circuit, prevent malfunction of the thin film shift register by the capacitor, and improve the performance. To be built into.

The gist of the present invention is that an insulating thin film such as an interlayer insulating film is used as a dielectric and a malfunction preventing capacitance is specially provided.

Hereinafter, the present invention will be described in detail based on examples.

3 and 4 show an embodiment of the present invention. In FIG. 3, reference numerals 300 and 301 denote clock lines, to which clock signals having opposite phases are applied. 302 is a data input terminal,
303 is a power supply line, 310 to 313, 320 to 32
3, 330 to 333, etc. are thin film transistors, 314,
324 and 334 are MOSs using thin film transistors
Capacitors 315, 325, 335, etc. are common gates of the thin film transistors and MOS capacitors 311 and 334, 31
6, 326 and 336 are output terminals of the shift register,
317, 327, 337 and the like are malfunction preventing capacitors provided by using an insulating film or the like, 318, 328, 338 and the like are power sources of the potential supplied to the power line 303, and are thin film transistors 310 to 313, MOS capacitors 314, Further, the malfunction prevention capacitor 317 forms one bit of the shift register. The operation example of the shift register of FIG. 3 is the same as that of FIG. 1, as shown in FIG.

FIG. 4 is an example of the structure of the present invention, and is a cross-sectional view of the channel portion such as the thin film transistor 311 taken along the channel width direction. 401 is an insulating substrate, 402 is a channel portion of a thin film transistor cut in the channel width direction, 4
Reference numeral 03 is a gate oxide film, 404 is a gate electrode, 405 is an interlayer insulating film, and 406 is a power supply line. Gate electrode 404,
The interlayer insulating film 405 and the power supply line 406 form a malfunction preventing capacitance.

FIG. 5 shows another embodiment of the present invention. The same symbols as those in FIG. 3 represent the same components as those in FIG. 510,51
2, 520, 522, 530, 532 and the like are malfunction preventing capacitors provided by using an insulating thin film, 511, 513, 52.
1, 523, 531, 533 and the like are power supplies of the potential supplied to the power supply line 303. In FIG. 5, one bit of the shift register is formed by the thin film transistors 310 to 313, the MOS capacitor 314, and the malfunction preventing capacitors 510 and 512. In the thin film shift register circuit,
Defects are most likely to occur in the malfunction preventing capacitance section because dust and the like cause a short circuit in the insulating thin film section. Then, a plurality of malfunction preventing capacitors may be provided in parallel so that only the short-circuited capacitors can be separated, and the yield is improved. Therefore, in FIG. 5, two malfunction preventing capacitors are provided in parallel in one bit. The operation example of the shift register of FIG. 5 is also as shown in FIG.

As described above, by using the present invention, a high-performance thin film shift register without malfunction can be realized, and a high-performance and high-yield peripheral drive circuit-embedded active matrix substrate can be realized.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an example of a conventional shift register circuit including MOS transistors provided on a single crystal silicon substrate. FIG. 2 is a diagram showing an applied waveform to each part of the shift register shown in FIG. 3 and 4 are views for explaining an embodiment of the present invention. FIG. 5 is a diagram for explaining another embodiment of the present invention.

Claims (2)

[Claims] 1. A thin film shift register circuit comprising thin film transistors formed on an insulating substrate or an insulating thin film, wherein each 1 bit of the thin film shift register has an output side terminal of the thin film transistor connected to a data input signal line. A thin film shift register circuit characterized in that a malfunction preventing capacitance is formed in parallel with the thin film shift register circuit. 2. The thin film shift register circuit according to claim 1, wherein a plurality of the malfunction preventing capacitors are formed in parallel with the output terminal line.