KR20010059851A - Semiconductor device with structure of decoupling capacitor - Google Patents
Semiconductor device with structure of decoupling capacitor Download PDFInfo
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- KR20010059851A KR20010059851A KR1019990067388A KR19990067388A KR20010059851A KR 20010059851 A KR20010059851 A KR 20010059851A KR 1019990067388 A KR1019990067388 A KR 1019990067388A KR 19990067388 A KR19990067388 A KR 19990067388A KR 20010059851 A KR20010059851 A KR 20010059851A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
- H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Abstract
Description
본 발명은 반도체 소자에 관한 것으로, 특히 레이아웃(layout)의 면적을 줄일 수 있고 반도체소자의 성능을 향상시킬 수 있는 디커플링(decoupling) 커패시터 구조를 갖는 반도체소자에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a decoupling capacitor structure that can reduce the area of the layout and improve the performance of the semiconductor device.
최근 전자기기 시스템의 고기능, 고속 동작에 대응하기 위해, 반도체 집적회로가 복잡해지고 또한 회로의 동작속도도 빨라지고 있다. 반도체 소자를 구성하는 회로가 복잡해짐에 따라 기생 커패시턴스, 인덕턴스, 저항등이 증가하고 있고, 그로 인하여 반도체 소자의 내부회로에 안정된 전원전압을 공급하기 위한 전원전압 배선의 노이즈 대책이 중요한 문제로 대두된다.In order to cope with the high-performance and high-speed operation of electronic system systems, semiconductor integrated circuits have become complicated and the operation speed of circuits has also increased. Parasitic capacitance, inductance, resistance, etc. are increasing as the circuits of semiconductor devices become more complicated. Therefore, noise countermeasures of power supply wiring for supplying stable power supply voltage to the internal circuits of semiconductor devices become an important problem. .
종래에 알려져 있는 전원전압 배선의 노이즈 대책중의 하나는 전원전압 배선과 내부회로 특히 드라이버 회로 사이에 디커플링 커패시터라고 불리는 커패시터를 설치하여, 커패시터를 일시적인 전류의 소스로 이용하는 것이다. 즉 드라이버 회로의 클럭이 어떤 한 상태로부터 다른 상태로 변화할 때 필요로 하는 순간적인 거대 전류를 디커플링 커패시터에서 드라이버 회로에 공급함으로써, 파워 서플라이로부터 내부회로로의 급격한 전류의 흐름을 방지하여, 전원전압 배선에 의해 유기되는 노이즈 및 전압강하를 방지한다.One of the known noise countermeasures of power supply voltage wiring is to install a capacitor called a decoupling capacitor between the power supply voltage wiring and an internal circuit, in particular a driver circuit, to use the capacitor as a source of temporary current. In other words, by supplying the instantaneous huge current required when the clock of the driver circuit changes from one state to another from the decoupling capacitor to the driver circuit, it prevents the rapid flow of current from the power supply to the internal circuit, thereby reducing the power supply voltage. Prevents noise and voltage drop induced by wiring.
도1은 일반적인 디커플링 커패시터의 구조를 도시한 것이다.1 shows the structure of a typical decoupling capacitor.
상기 디커플링 커패시터는 p형 반도체기판(100) 또는 p형 웰(100)내에 형성된 제1 및 제2 n형 불순물 확산층들(102a),(102b)과, 상기 제1 n형 불순물 확산층(102a)과 제2 n형 불순물 확산층(102b)사이의 상기 p형 웰(100) 표면에 형성되는 채널영역(112)과, 상기 채널영역(112)위의 상기 p형 웰(100)상면에 형성된 게이트산화막(114)과, 상기 게이트산화막(114)위에 형성된 게이트 전극(116)으로 구성된 n채널 모스(MOS)트랜지스터(200)로 구성되고, 상기 게이트 전극(116)에는 정전원전압(Vdd)이 공급되고, 상기 제1, 제2 n형 불순물 확산층(102a),(102b)에는 부전원전압(예를 들어, 그라운드 전압 : Vss)이 인가된다. 여기서, 게이트전극 (116)에는 정전원전압(Vdd)이 인가되므로, 게이트전극(116) 아래의 p형 웰(100)내에는 n채널(112)이 형성된다. 따라서 게이트 전극(116)과 n채널(112)이 각각 커패시터의 양쪽 전극으로 작용하고 게이트산화막(114)이 커패시터의 유전체로서 작용하여 디커플링 커패시터를 구성한다.The decoupling capacitor may include first and second n-type impurity diffusion layers 102a and 102b formed in the p-type semiconductor substrate 100 or the p-type well 100, and the first n-type impurity diffusion layer 102a. A channel region 112 formed on a surface of the p-type well 100 between the second n-type impurity diffusion layer 102b and a gate oxide film formed on an upper surface of the p-type well 100 on the channel region 112 ( 114 and an n-channel MOS transistor 200 formed of a gate electrode 116 formed on the gate oxide film 114, and an electrostatic source voltage Vdd is supplied to the gate electrode 116. A negative power supply voltage (eg, ground voltage: Vss) is applied to the first and second n-type impurity diffusion layers 102a and 102b. Here, since the electrostatic source voltage Vdd is applied to the gate electrode 116, the n-channel 112 is formed in the p-type well 100 under the gate electrode 116. Therefore, the gate electrode 116 and the n-channel 112 act as both electrodes of the capacitor, respectively, and the gate oxide film 114 acts as the dielectric of the capacitor to form a decoupling capacitor.
도 2는 종래의 반도체소자의 레이아웃을 보인 것이다. 종래의 반도체 소자는 p형 반도체기판(100)과, 입출력 버퍼와, 상기 입출력 버퍼로부터의 출력신호를 반도체 집적회로의 내부로 전달하는 신호전달 배선(106)들이 밀집되어 있는 신호전달 배선밀집부로 구성되어 있다.2 shows a layout of a conventional semiconductor device. The conventional semiconductor device includes a p-type semiconductor substrate 100, an input / output buffer, and a signal transfer wiring assembly unit in which signal transmission wirings 106 for transmitting an output signal from the input / output buffer are integrated into the semiconductor integrated circuit. It is.
또한, 상기 입축력 버퍼는 다음과 같이 구성된 씨모스(CMOS: Complementary Metal Oxide Semiconductor)이다. 정전원전압(Vdd) 배선(110)과, 상기 정전원전압 배선(110)에 연결되고, n형 웰(101)상에 형성된 p채널 MOS트랜지스터(111)와, 그 p채널 MOS트랜지스터(111)와 직렬로 연결되고 상기 p형 반도체기판(100)상에 형성된 n채널 MOS트랜지스터(103)와, 그 n채널 MOS트랜지스터(103)의 소스에 연결된 부전원전압(Vss) 배선(104)으로 구성되어 있다.In addition, the accumulation force buffer is a CMOS (Complementary Metal Oxide Semiconductor) (CMOS) configured as follows. A p-channel MOS transistor 111 connected to the electrostatic source voltage Vdd wiring 110, the electrostatic power supply voltage wiring 110, and formed on the n-type well 101, and the p-channel MOS transistor 111. And an n-channel MOS transistor 103 formed in series on the p-type semiconductor substrate 100 and a negative power supply voltage (Vss) wiring 104 connected to a source of the n-channel MOS transistor 103. have.
또한, 상기 p채널 MOS트랜지스터(111)는 게이트전극(111a)과, 그 게이트전극 (111a)의 양측 n형 웰(101)내에 형성된 소스(111b) 및 드레인(111c)으로 구성되어 있다.The p-channel MOS transistor 111 is composed of a gate electrode 111a and a source 111b and a drain 111c formed in both n-type wells 101 of the gate electrode 111a.
또한, 상기 n채널 MOS트랜지스터(103)는 게이트전극(103a)과, 그 게이트전극 (103a)의 양측 반도체기판(100)내에 형성된 소스(103b) 및 드레인(103c)으로 구성되어 있다.The n-channel MOS transistor 103 is composed of a gate electrode 103a, a source 103b and a drain 103c formed in the semiconductor substrate 100 on both sides of the gate electrode 103a.
또한, 상기 p채널 MOS트랜지스터의 게이트전극(111a)과, n채널 MOS트랜지스터(103)의 게이트전극(103a)은 공통 입력 라인(102)에 의해 연결되어 있다.The gate electrode 111a of the p-channel MOS transistor and the gate electrode 103a of the n-channel MOS transistor 103 are connected by a common input line 102.
또한, 상기 p채널 MOS트랜지스터(111)의 드레인(111c)과, 상기 n채널 MOS트랜지스터(103)의 드레인(103c)이 공통 출력라인(105)에 의해 연결되어 있다.The drain 111c of the p-channel MOS transistor 111 and the drain 103c of the n-channel MOS transistor 103 are connected by a common output line 105.
상기 입력버퍼회로의 공통 출력라인(105)은 신호전달배선(106)에 연결되어 있다. 여기서 신호전달배선(106)이란, 일반적으로 입출력패드 또는 버퍼와, 구동회로, 클럭신호 발생회로, 디코더 등과 같은 내부회로를 연결하는 금속배선을 의미한다.The common output line 105 of the input buffer circuit is connected to the signal transfer wiring 106. Here, the signal transfer wiring 106 generally refers to a metal wiring that connects an input / output pad or buffer and an internal circuit such as a driving circuit, a clock signal generation circuit, a decoder, and the like.
그런데, 종래의 반도체소자에 있어서, 상기 신호전달배선(106)은 일반적으로 반도체칩의 주변부에 밀집되어 형성되어 있다. 상기 신호전달배선(106)의 주변에는 트랜지스터를 제조할 수 없는 영역이므로, 단지 신호전달배선(106)을 형성하는 데만 이용된다. 또한 상기 신호전달배선(106)은 플로팅상태의 반도체기판(100) 상부에 형성된다.By the way, in the conventional semiconductor device, the signal transmission wiring 106 is generally formed in the periphery of the semiconductor chip. Since the transistor cannot be manufactured in the vicinity of the signal transmission wiring 106, it is only used to form the signal transmission wiring 106. In addition, the signal transfer wiring 106 is formed on the semiconductor substrate 100 in a floating state.
상기와 같이, 전원전압 배선의 노이즈를 감소시키기 위하여 구비되는 MOS트랜지스터(200)를 이용한 디커플링 커패시터는, 집적회로의 구성요소들과는 별도로 제작해야 되기 때문에, 반도체기판(100)의 레이아웃 면적을 많이 점유한다. 따라서 반도체소자의 크기의 소형화를 저해하며, 결과적으로 반도체 칩의 제조원가를 높이는 단점이 있었다.As described above, the decoupling capacitor using the MOS transistor 200 provided to reduce the noise of the power supply voltage wiring occupies much of the layout area of the semiconductor substrate 100 because it must be manufactured separately from the components of the integrated circuit. . Therefore, the size of the semiconductor device is reduced, and as a result, the manufacturing cost of the semiconductor chip is increased.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 반도체 소자의 레이아웃의 면적을 줄이고, 반도체소자의 성능을 향상시킬 수 있는 디커플링 커패시터 구조를 갖는 반도체소자를 제공하는 것을 목적으로 한다.The present invention has been made to solve the above problems, an object of the present invention is to provide a semiconductor device having a decoupling capacitor structure that can reduce the area of the layout of the semiconductor device, and improve the performance of the semiconductor device.
본 발명의 또 다른 목적은 반도체 집적회로를 구성하는 트랜지스터들을 형성할 수 없는 영역을 이용하여 전원전압 배선의 노이즈를 절감시키기 위한 디커플링 커패시터를 형성할 수 있는 디커플링 커패시터 구조를 갖는 반도체소자를 제공하는 것이다.It is still another object of the present invention to provide a semiconductor device having a decoupling capacitor structure capable of forming a decoupling capacitor for reducing noise in power supply voltage wiring by using an area where transistors constituting a semiconductor integrated circuit cannot be formed. .
본 발명의 또 다른 목적은, 반도체 집적회로들간을 연결하는 신호전달 배선이 밀집되어 있는 반도체기판 주변부에서, 상기 신호 전달 배선 아래의 반도체 기판내에 n형 웰을 형성함으로써, 신호 전달 배선과 반도체 기판내의 n형 웰을 각각 디커플링 커패시터의 두 전극으로 하고 그들 사이의 층간절연막을 유전체로 이용하는 디커플링 커패시터 구조를 갖는 반도체소자를 제공하는 것이다.It is still another object of the present invention to form an n-type well in a semiconductor substrate below the signal transmission wiring at a peripheral portion of the semiconductor substrate where signal transmission wiring that connects the semiconductor integrated circuits is concentrated. A semiconductor device having a decoupling capacitor structure using n-type wells as two electrodes of a decoupling capacitor and using an interlayer insulating film therebetween as a dielectric is provided.
도1은 종래의 반도체 소자에 구비되는 디커플링 커패시터의 구조를 도시한 단면도.1 is a cross-sectional view showing the structure of a decoupling capacitor provided in a conventional semiconductor device.
도2는 종래의 반도체 소자의 레이아웃을 보인 도.2 is a view showing a layout of a conventional semiconductor device.
도3은 본 발명에 따른 디커플링 커패시터 구조를 갖는 반도체 소자의 레이아웃을 보인 도.Figure 3 shows a layout of a semiconductor device having a decoupling capacitor structure in accordance with the present invention.
*도면부호에 대한 간단한 설명** Brief description of the drawings
100 : 반도체 기판 102a, 102b : 소스, 드레인100: semiconductor substrate 102a, 102b: source, drain
112 : 채널 114 : 게이트 산화막112: channel 114: gate oxide film
116 : 게이트 전극 200 : p채널 트랜지스터116: gate electrode 200: p-channel transistor
30 : p형 반도체 기판 30a, 30b : n형 웰30: p-type semiconductor substrate 30a, 30b: n-type well
31 : 정전원전압 배선 32 : 부전원전압 배선31: electrostatic source voltage wiring 32: negative power supply voltage wiring
33 : 신호 입력 라인 35 : 신호 출력 라인33: signal input line 35: signal output line
36 : 신호 전달 배선 39 : 내부회로36: signal transmission wiring 39: internal circuit
상기 발명의 목적을 달성하기 위하여 본 발명은 제1도전형 반도체 기판과, 상기 제1도전형 반도체 기판상에 형성된 입출력 버퍼회로와, 상기 입출력 버퍼회로의 출력라인에 연결된 신호 전달 배선과, 상기 신호전달 배선 하방측 상기 반도체 기판내에 형성된 제2 도전형의 웰로 구성되고, 상기 제2도전형의 웰은 전원전압 배선에 연결되어 있는 것을 특징으로 하는 전원전압 배선의 노이즈 저감 구조를 제공한다.In order to achieve the object of the present invention, the present invention provides a first conductive semiconductor substrate, an input / output buffer circuit formed on the first conductive semiconductor substrate, signal transmission wiring connected to an output line of the input / output buffer circuit, and the signal. And a second conductive well formed in the semiconductor substrate below the transfer wiring, and the well of the second conductive type is connected to the power supply voltage wiring.
이하, 본 발명의 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도3은 본 발명에 따른, 전원전압 배선의 노이즈 저감 구조를 갖는 반도체 소자의 레이아웃이다.3 is a layout of a semiconductor device having a noise reduction structure of power supply voltage wiring according to the present invention.
즉, 본 발명에 따른 반도체 소자는, p형 반도체기판(30)과, 입출력 버퍼와, 그 입출력 버퍼로부터의 출력신호를 반도체소자의 내부회로(39)로 전달하는 신호전달 배선(36)들이 밀집되어 있는 신호전달 배선밀집부와, 상기 신호전달 배선(36)들 하방의 반도체기판(30)내에 형성된 n형웰(30b)을 포함하고, 상기 n형웰(30b)에는 정전압(Vdd)이 인가되도록 구성되어 있다.That is, in the semiconductor device according to the present invention, the p-type semiconductor substrate 30, the input / output buffer, and the signal transmission wirings 36 for transmitting the output signal from the input / output buffer to the internal circuit 39 of the semiconductor device are densely packed. And a n-type well 30b formed in the semiconductor substrate 30 under the signal-transfer wirings 36, and a constant voltage Vdd is applied to the n-type well 30b. It is.
또한, 상기 입출력 버퍼는 다음과 같이 구성된 CMOS이다. 정전원전압(Vdd) 배선(31)과, 그 정전원전압 배선(31)에 연결되고, n형 웰(30a)상에 형성된 p채널 MOS트랜지스터(301)와, 그 p채널 MOS트랜지스터(301)와 직렬로 연결되어 있고 상기 p형 반도체기판(30)상에 형성된 n채널 MOS트랜지스터(302)와, 그 n채널 MOS트랜지스터(302)의 소스에 연결된 부전원전압(Vss) 배선(32)으로 구성되어 있다.The input / output buffer is a CMOS configured as follows. The p-channel MOS transistor 301 connected to the electrostatic source voltage Vdd wiring 31, the electrostatic source voltage wiring 31, and formed on the n-type well 30a, and the p-channel MOS transistor 301. And an n-channel MOS transistor 302 connected in series with and connected to the source of the n-channel MOS transistor 302 and connected in series with the p-type semiconductor substrate 30. It is.
또한, 상기 p채널 MOS트랜지스터(301)는 게이트전극(301a)과, 그 게이트전극 (301a)의 양측 n형 웰(30a)내에 형성된 소스(301b) 및 드레인(301c)으로 구성되어 있다.The p-channel MOS transistor 301 is composed of a gate electrode 301a, a source 301b and a drain 301c formed in both n-type wells 30a of the gate electrode 301a.
또한, 상기 n채널 MOS트랜지스터(302)는 게이트전극(302a)과, 그 게이트전극 (302a)의 양측 반도체기판(30)내에 형성된 소스(302b) 및 드레인(302c)으로 구성되어 있다.The n-channel MOS transistor 302 is composed of a gate electrode 302a, and a source 302b and a drain 302c formed in the semiconductor substrate 30 on both sides of the gate electrode 302a.
또한, 상기 p채널 MOS트랜지스터의 게이트전극(301a)과, n채널 MOS트랜지스터의 게이트전극(302a)은 공통 입력 라인(34)에 의해 연결되어 있다.The gate electrode 301a of the p-channel MOS transistor and the gate electrode 302a of the n-channel MOS transistor are connected by a common input line 34.
또한, 상기 p채널 MOS트랜지스터의 드레인(301c)과, 상기 n채널 MOS트랜지스터의 드레인(302c)이 공통 출력 라인(35)에 의해 연결되어 있다.The drain 301c of the p-channel MOS transistor and the drain 302c of the n-channel MOS transistor are connected by a common output line 35.
상기 입력버퍼회로의 출력라인(35)은 신호전달배선(36)에 연결되어 있다.The output line 35 of the input buffer circuit is connected to the signal transfer wiring 36.
여기서 신호전달배선(36)이란, 일반적으로 입출력패드 또는 버퍼와, 구동회로, 클럭신호 발생회로, 디코더 등과 같은 내부회로(39)를 연결하는 금속배선을 가르킨다.In this case, the signal transfer wiring 36 generally refers to a metal wiring that connects an input / output pad or buffer with an internal circuit 39 such as a driving circuit, a clock signal generation circuit, a decoder, and the like.
그런데 도3에 도시한 바와 같이, 본 발명에 따른 반도체 소자에 있어서는, 상기 신호전달 배선(36)들이 밀집되어 있는 부분의 그 하방측의 p형 반도체 기판(30)의 표면에 n형 웰(30b)을 형성하고, 상기 n형 웰(30b)의 상부에까지 상기 입출력 버퍼회로(30)의 정전원전압 배선(31)을 연장형성하여, 상기 n형 웰(30b)과 상기 정전원전압배선(31)을 콘택홀(33)에 의해 연결하였다.3, in the semiconductor device according to the present invention, the n-type well 30b is disposed on the surface of the p-type semiconductor substrate 30 on the lower side of the portion where the signal transfer wirings 36 are concentrated. ) And extend the electrostatic source voltage wiring 31 of the input / output buffer circuit 30 to the top of the n-type well 30b to form the n-type well 30b and the electrostatic source voltage wiring 31. ) Is connected by a contact hole 33.
본 발명은 상기와 같이 반도체소자를 구성함으로써, 상기 n형 웰(30b)과 상기신호전달배선(36)을 디커플링 커패시터의 양측전극으로 하고, 그들 사이에 형성된 층간 절연막(미도시)을 유전체로 하여 디커플링 커패시터를 구성하게 된다. 따라서, 전원전압배선의 노이즈를 저감하기 위한 MOS형 디커플링 커패시터를 별도로 제조하여 반도체기판(30) 상에 장착하지 않고, 신호전달 배선을 이용하여 디커플링 커패시터를 형성할 수 있기 때문에, 공정이 용이하고 또한 반도체기판(30)의 점유면적을 줄일 수 있게 된다. 즉, 본 발명의 반도체소자에 있어서는, 단순히 종래 구조의 반도체소자의 신호배선 하방측의 반도체기판(30)내에, 반도체 집적회로를 제조하기 위한 n형 웰 형성공정과 동일한 공정단계에서 n형 웰(30b)을 형성하는 것만으로, 전원전압 배선의 노이즈를 저감할 수 있는 디커플링 커패시터를 제조한다.In the present invention, the n-type well 30b and the signal transfer wiring 36 are both electrodes of the decoupling capacitor, and the interlayer insulating film (not shown) formed therebetween is used as a dielectric material. It will form a decoupling capacitor. Therefore, since the MOS type decoupling capacitor for reducing the noise of the power supply voltage wiring is separately manufactured and mounted on the semiconductor substrate 30, the decoupling capacitor can be formed using the signal transfer wiring, so that the process is easy and Occupancy area of the semiconductor substrate 30 can be reduced. That is, in the semiconductor device of the present invention, the n-type well (in the same process step as the n-type well forming process for manufacturing a semiconductor integrated circuit in the semiconductor substrate 30 on the lower side of the signal wiring of the semiconductor device of the conventional structure) Only by forming 30b), the decoupling capacitor which can reduce the noise of a power supply voltage wiring is manufactured.
상기와 같이 본 발명에 따른 반도체 소자는, 입출력 버퍼회로와 내부회로 사이에 전원전압 배선 노이즈를 절감하기 위한 MOS트랜지스터형의 디커플링 커패시터를 별도로 형성하지 않고, 신호배선이 형성되어 있는 영역을 디커플링 커패시터로 이용함으로써, 종래에 비하여 반도체기판의 점유면적을 줄일 수 있는 효과가 있다.As described above, the semiconductor device according to the present invention does not form a separate MOS transistor type decoupling capacitor for reducing power supply voltage wiring noise between the input / output buffer circuit and the internal circuit, and uses the decoupling capacitor as an area for the signal wiring. By using the same, the area occupied by the semiconductor substrate can be reduced as compared with the conventional art.
또한, 종래 반도체 소자의 집적회로를 제조하는 공정에 새로운 공정 단계를 추가하지 않고 디커플링 커패시터를 형성할 수 있기 때문에 제조비용이 증가하지 않는 효과가 있다.In addition, since the decoupling capacitor can be formed without adding a new process step to the process of manufacturing an integrated circuit of a conventional semiconductor device, there is an effect that the manufacturing cost does not increase.
또한, 본 발명에서는 종래의 노이즈 저감 구조인 MOS형 디커플링 커패시터를 형성할 필요가 없기 때문에, 그 MOS형 디커플링 커패시터가 차지하던 면적에 다른반도체소자를 형성할 수 있어 반도체기판의 이용효율을 높이는 효과가 있다.In addition, since the MOS type decoupling capacitor, which is a conventional noise reduction structure, does not need to be formed in the present invention, another semiconductor element can be formed in the area occupied by the MOS type decoupling capacitor, thereby increasing the utilization efficiency of the semiconductor substrate. have.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100721191B1 (en) * | 2001-06-30 | 2007-05-23 | 주식회사 하이닉스반도체 | Method for forming decoupling capacitor of semiconductor device |
| KR100788222B1 (en) * | 2005-08-31 | 2007-12-26 | 엔이씨 일렉트로닉스 가부시키가이샤 | Integrated circuit incorporating decoupling capacitor under power and ground lines |
| US7456063B2 (en) | 2005-12-08 | 2008-11-25 | Electronics And Telecommunications Research Institute | Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method |
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| ATE154726T1 (en) * | 1992-02-27 | 1997-07-15 | Philips Electronics Nv | INTEGRATED CMOS CIRCUIT |
| KR100261210B1 (en) * | 1992-06-20 | 2000-07-01 | 윤종용 | Method for manufacturing decoupling capacitor |
| JPH11177022A (en) * | 1997-12-08 | 1999-07-02 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH11186497A (en) * | 1997-12-17 | 1999-07-09 | Toshiba Corp | Semiconductor integrated circuit device |
| KR20000003885A (en) * | 1998-06-29 | 2000-01-25 | 윤종용 | Semiconductor devices having decoupling capacitor |
| KR20000041463A (en) * | 1998-12-22 | 2000-07-15 | 김영환 | Decoupling capacitor for power of memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100721191B1 (en) * | 2001-06-30 | 2007-05-23 | 주식회사 하이닉스반도체 | Method for forming decoupling capacitor of semiconductor device |
| KR100788222B1 (en) * | 2005-08-31 | 2007-12-26 | 엔이씨 일렉트로닉스 가부시키가이샤 | Integrated circuit incorporating decoupling capacitor under power and ground lines |
| US7456063B2 (en) | 2005-12-08 | 2008-11-25 | Electronics And Telecommunications Research Institute | Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method |
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