JPH1098112A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce unwanted radiated electromagnetic waves by providing an electromagnetic wave reducing means, for flowing a current reverse to a current flowing a current path in parallel to current paths in a semiconductor element near which this reducing means is disposed. SOLUTION: When an input signal voltage turns from L to H or vice versa, a pMOS101 and nMOS102 turn on transiently simultaneously to flow a through- current 107, causing an electromagnetic wave 108 to be radiated. A current 110 also flows at the same intensity as that of the through-current 107 flowing in a semiconductor element and in the reverse direction thereto in a conductor 109 disposed near this element, so as to flow the current 110 in reverse to the current 107, resulting in radiation of electromagnetic wave 111 which has the same intensity as that of the current 107 but reverse in phase thereto. Hence the electromagnetic waves 108 and 111 are mutually cancelled as being radiated nearby. This reduces the electromagnetic waves radiated from a semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for reducing electromagnetic waves radiated from a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A semiconductor integrated circuit with reduced electromagnetic wave radiation is disclosed, for example, in Japanese Patent Application Laid-Open No. 4-113653.

[0003] This prior art discloses an output transistor circuit of a semiconductor integrated circuit arranged on a semiconductor substrate, an output signal wiring portion of the output transistor circuit, a power supply wiring portion connected to the output transistor circuit, and a GND wiring. In the semiconductor device including the part, on the side of the output signal wiring part,
The power supply wiring section and the GND wiring section are extended and arranged in parallel. When signals are switched, electromagnetic waves cancel each other out of the power supply wiring and the output signal wiring, and the output signal wiring and the GND wiring. , Electromagnetic waves from the wiring section are reduced.

[0004]

However, the above prior art does not consider reduction of electromagnetic waves generated by a through current flowing inside a semiconductor element mounted on a semiconductor integrated circuit.

[0005] This problem will be described in detail with reference to FIG.

A typical element CMOS (Complementary MOS) used for a semiconductor integrated circuit is as follows.
A p-channel MOS transistor that is turned on when the input signal voltage is at “L” (“0”) level (hereinafter referred to as pMOS)
And an n-channel MOS transistor (hereinafter referred to as nMOS) which is turned on when the input signal voltage is at the “H” (“1”) level.

FIG. 8 shows the most basic CMOS inverter. In brief, the operation is as follows. When the input signal voltage applied to the input signal terminal 1001 is at “H” level, the pMOS 1002 is turned off, the nMOS 1003 is turned on, and the output signal terminal 1004 is connected to the ground (hereinafter referred to as GND) 1006. It is electrically connected and the output signal voltage is "
On the contrary, when the input signal voltage applied to the input signal terminal 1001 is at "L" level, the pMOS 100
2 is turned on, the nMOS 1003 is turned off, the output signal terminal 1004 is electrically connected to a power supply (hereinafter, referred to as Vcc) 1005, and the output signal voltage becomes "H" level.

As described above, in the CMOS inverter, since one of the MOS transistors is constantly turned off, no current flows from Vcc 1005 to GND 1006 through both MOS transistors. Input signal terminal 10
It is merely that one of the MOS transistors is turned on in accordance with the level of the voltage 01, and the voltage of the output signal terminal 1004 is switched.

A feature that no current flows from Vcc to GND is that other CMOs such as NAND circuits and NOR circuits
The same applies to the S element. Therefore, the CMOS device has a great advantage that power consumption is extremely small, and is widely used in semiconductor integrated circuits.

However, in the conventional circuit shown in FIG. 8, the voltage level of the input signal terminal 1001 is actually "
From "H" level to "L" level, from "L" level to "
When switching to H level, pMOS
1002 and nMOS 1003 are simultaneously turned on, and Vc
A current called through current 1007 flows from c1005 to GND 1006 via pMOS 1002 and nMOS 1003.

This through current 1007 is a short-circuit current, and therefore contains a large current and a large amount of harmonic components.
When the through current 1007 flows, there is a problem that unnecessary and large electromagnetic waves 1008 are radiated. The electromagnetic wave due to this through current is supplied to the power supply wiring, GN
It is generated from the D wiring and the semiconductor circuit element, respectively.

[0012] Recently, the clock frequency at which the semiconductor integrated circuit operates is steadily increasing.
I. In the United States, regulations have been established to limit the intensity of unnecessary electromagnetic waves radiated from devices such as the FCC, and it is important to reduce unnecessary electromagnetic waves radiated from an electromagnetic wave source in order to satisfy these regulations.

An object of the present invention is to provide means for reducing unnecessary electromagnetic waves radiated from a semiconductor integrated circuit by a through current.

Another object of the present invention is to provide means for reducing unnecessary electromagnetic waves radiated from a semiconductor integrated circuit application device such as an information processing device.

[0015]

To achieve the above object, the present invention provides a semiconductor integrated circuit comprising a semiconductor element and a semiconductor chip on which the semiconductor element is mounted.
An electromagnetic wave reduction means is provided near the semiconductor element and flows a current parallel to a current path flowing inside the semiconductor element and in a direction opposite to the current flowing through the current path.

The electromagnetic wave reducing means is preferably arranged at a distance where the electromagnetic waves generated by the through current flowing inside the semiconductor chip and the current flowing inside the electromagnetic wave reducing means interfere with each other. Further, it is desirable that no other signal wiring be arranged between the electromagnetic wave reducing means and the semiconductor chip.

In order to achieve the object with a simple configuration, the electromagnetic wave reducing means is configured by either the power supply wiring or the ground wiring in which the current flowing in parallel with the current path is in the opposite direction.

The wiring for reducing the electromagnetic wave is arranged on the same surface as the surface on which the semiconductor element is installed, so that the pattern processing is performed only on one side of the semiconductor chip.

On the other hand, it is preferable that the wiring for reducing the electromagnetic wave is arranged on a different surface of the semiconductor chip from the surface on which the semiconductor element is provided, to secure a mounting area.

Further, by arranging the power supply wiring and the ground wiring so as to be close to each other and to allow currents to flow in opposite directions, all electromagnetic waves generated from the semiconductor element and the power and ground wirings can be reduced. So more desirable.

Further, the present invention is also achieved by providing an electromagnetic wave reducing means for flowing a current in a direction opposite to a through current flowing in the inside of the semiconductor element, which comprises a semiconductor element and a semiconductor chip on which the semiconductor element is mounted. A power supply wiring and a ground wiring connected to the semiconductor element; a first connection part to the power supply wiring provided in the semiconductor element; and a second connection to the ground wiring provided to the semiconductor element. The power supply wiring or the ground wiring is disposed in the vicinity of the semiconductor element and in parallel with a line segment formed by the first and second connection parts. It can also be said.

Further, in order to solve the same problem, according to the present invention, at least two semiconductor elements for switching an output signal in response to the same input signal are supplied with a current flowing through each semiconductor element in the opposite direction when the signal is switched. It is also disclosed that it is arranged at a position in the vicinity of the relationship that flows through.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a diagram showing the concept of a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes a pMOS;
Is an nMOS, 103 is an input signal terminal, 104 is Vcc,
105 is GND, and 106 is an output signal terminal. 107
Is a through current flowing through the semiconductor element, and 108 is a through current 10
7, a conductor disposed so as to allow current to flow in the vicinity of the semiconductor element and in a direction opposite to the through current 107 flowing through the semiconductor element;
A current flowing through 9, 111 indicates an electromagnetic wave radiated by the current 110. A portion (112) surrounded by a dotted line is a semiconductor element, 113 is a connection portion with a power supply wiring, and 114 is a connection portion with a ground wiring.

The outline of the operation of the semiconductor integrated circuit of this embodiment will be described below with reference to FIG.

In FIG. 1, pMOS 101 and nMOS 10
2 are combined to form a CMOS inverter. The input signal voltage applied to the input signal terminal 103 is "
If it is at the L level, the pMOS 101 is turned on and nM
The OS 102 is turned off and the output signal terminal 106 is connected to Vcc1.
04, and the voltage level of the output signal terminal 106 becomes “H” level. In this state, nMOS1
02 is off, so GND from Vcc104
No current flows to 105 and no electromagnetic wave 108 is emitted.

Conversely, when the input signal voltage applied to the input signal terminal 103 is at "H" level, the pMOS 10
1 is off, the nMOS 102 is on, and the output signal terminal 1
Reference numeral 06 is electrically connected to the GND 105, and the voltage level of the output signal terminal 106 is at "L" level. In this state, since the pMOS 101 is off, no current flows from the Vcc 104 to the GND 105 as in the case described above, and the electromagnetic wave 108 is not emitted.

However, when the input signal voltage applied to the input signal terminal 103 changes from "L" level to "H" level and conversely from "H" level to "L" level, p
The MOS 101 and the nMOS 102 are simultaneously turned on for a moment, and a through current 107 flows. An electromagnetic wave 108 is radiated by the through current 107.

At the same time, a current 110 in the same amount and opposite direction as the through current 107 also flows through the conductor 109 arranged near the semiconductor element and in a direction opposite to the through current 107 flowing through the semiconductor element. This current 110 radiates an electromagnetic wave 111. The electromagnetic wave 108 and the electromagnetic wave 111 are electromagnetic waves having the same intensity and opposite phases, and cancel each other by radiating the electromagnetic wave 108 and the electromagnetic wave 111 from the vicinity.

As described above, in this embodiment, the electromagnetic waves radiated from the semiconductor integrated circuit having these semiconductor elements can be reduced.

Although there is a certain effect even if another wiring is inserted between the conductor 109 and the semiconductor element, it is desirable not to dispose another wiring in terms of bringing the wiring closer and reducing electromagnetic waves.

The present embodiment is not limited to the inverter, but
The present invention can be applied to other logic circuits such as an ND circuit, an OR circuit, a NAND circuit, and a NOR circuit.

(Embodiment 2) FIG. 2 is a diagram schematically showing a wiring structure of a semiconductor integrated circuit according to an embodiment in which a semiconductor element different from that of FIG. 1 is used.

In FIG. 2, reference numeral 201 denotes an input signal terminal;
02 is an npn-type bipolar transistor (hereinafter referred to as a bipolar transistor), 203 is a resistor for determining the base current amount of the bipolar transistor 202, 20
4 is a resistor that determines the amount of collector current of the bipolar transistor 202, 205 is Vcc, 206 is GND, 2
07 is a current flowing through the semiconductor element, 208 is an electromagnetic wave radiated by the current 207, 209 is a conductor arranged in the vicinity of the semiconductor element and in a direction opposite to the current 207 flowing through the semiconductor element, 210 is a conductor 209 Current, 211 is an electromagnetic wave radiated by the current 210,
Reference numeral 212 denotes an output signal terminal. Part enclosed by dotted line
Reference numeral (213) denotes a semiconductor element, 214 denotes a connection part to a power supply wiring, and 215 denotes a connection part to a ground wiring.

The outline of the operation of the semiconductor integrated circuit of this embodiment will be described below with reference to FIG.

In FIG. 2, the bipolar transistor 20
2 and a resistor 203 and a resistor 204 are combined to constitute an inverter using a bipolar transistor. When the input signal voltage applied to the input signal terminal 201 is “
If L level, the bipolar transistor 2
02 is turned off, the voltage of Vcc 205 is applied to the output signal terminal 212, and the voltage level of the output signal terminal 212 becomes "
H "level.

Conversely, when the input signal voltage applied to the input signal terminal 201 is at "H" level,
The transistor 202 is turned on, the output signal terminal 212 is electrically connected to the GND 206, and the output signal terminal 212
Becomes the "L" level. At this time, since the bipolar transistor 202 is turned on, V
A current 207 flows from the cc 205 via the resistor 204 and the bipolar transistor 202. This current 207
As a result, an electromagnetic wave 208 is emitted.

At the same time, a current 210 in the same amount and opposite direction as the current 207 also flows through the conductor 209 arranged near the semiconductor element and in a direction opposite to the current 207 flowing through the semiconductor element. This current 210 radiates an electromagnetic wave 211. The electromagnetic wave 208 and the electromagnetic wave 211 are electromagnetic waves having opposite phases, and the electromagnetic wave 208 and the electromagnetic wave 211 cancel each other by being radiated from the vicinity.

As described above, in this embodiment, the electromagnetic waves radiated from the semiconductor integrated circuit having these semiconductor elements can be reduced.

The embodiments shown in the first embodiment and the second embodiment are not limited to the CMOS device and the bipolar device, but may be a Bi-type device.
The present invention is also applicable to other semiconductor devices such as CMOS.

(Embodiment 3) FIG. 3 is a diagram schematically showing a semiconductor integrated circuit according to an embodiment of the present invention. The upper part of FIG. 3 shows the semiconductor integrated circuit according to the present embodiment as viewed from above. The lower part of FIG. 3 shows a section taken along the line AA ′ of the semiconductor integrated circuit according to the present embodiment.

In FIG. 3, 301 is Vcc, 302 is GND, 303 is an n + poly Si gate, 304 is a gate oxide film, 305 is an insulating film, 306 is a field oxide film,
307 is n +, 308 is n +, 309 is p-well, 31
0 is p +, 311 is p +, 312 is n + poly Si gate, 313 is a gate oxide film, and 314 is an n substrate.

315 is an nMOS, 316 is a pMOS, 3
17 is a gate terminal of the nMOS 315, and 318 is an nMOS
315 is a source terminal, 319 is a drain terminal of the nMOS 315, 320 is a gate terminal of the pMOS 316, 321
Is the source terminal of the pMOS 316 and 322 is the pMOS 31
6, an input signal terminal for applying a signal to the gate terminal 317 of the nMOS 315 and a gate terminal 320 of the pMOS 316;
This is an output signal terminal of a CMOS inverter composed of the MOS 316.

325 is an nMOS 315 and a pMOS 316
Current flowing through the CMOS device composed of
Is an electromagnetic wave radiated by the through current 325, and 327 is n
CMOS composed of MOS 315 and pMOS 316
32, a conductor arranged so that current flows in the vicinity of the device and in the direction opposite to the through current 325 flowing through the CMOS device;
8 is a through current flowing through the conductor 327, and 329 is a through current 3.
2 shows the electromagnetic waves emitted by 28.

The outline of the operation of the semiconductor integrated circuit of this embodiment will be described below with reference to FIG.

In FIG. 3, n + poly S
i-gate 303, gate oxide film 304, n + 307 and 3
08, a p-well 309, a gate terminal 317, a source terminal 318, and a drain terminal 319 form an nMOS 315. Similarly, n + poly-Si gate 312, gate oxide film 313, p + 310 and 311 and gate terminal 32
0, pMO from source terminal 321 and drain terminal 322
S316 is formed. These nMOS 315 and p
The MOS 316 is combined to form a CM on the n-substrate 314.
It constitutes an OS inverter.

When the signal voltage applied to the input signal terminal 323 is at "L" level, the voltage is applied to the gate terminal 3
20, an n + poly-Si gate 3 which is a good electrical conductor
12 is applied. This voltage induces a positive hole under the gate oxide film 313 which is an insulator, and
The portion immediately below the gate oxide film 314 changes to a p-channel, forming an inversion layer. Therefore, p +
310 and p + 311 are electrically connected, and the pMOS 316
Turns on.

Also in the nMOS 315, the “L” level signal voltage applied to the input signal terminal 323 is applied via the gate terminal 317 to the n + poly-Si gate 303, which is a good electrical conductor. This voltage induces a positive hole under the gate oxide film 304 which is an insulator.
Since the portion of the p well 309 immediately below the gate oxide film 304 is not inverted to the n channel, n + 307 and n + 3
08 does not conduct electrically, and the nMOS 315 is turned off.

Therefore, the output signal terminal 324 is connected to Vcc
The voltage of 301 is applied via the pMOS 316, and the output signal becomes “H” level.

On the other hand, when the signal voltage applied to the input signal terminal 323 is at the “H” level, the voltage is applied to the n + poly-Si gate 303, which is an electric conductor, via the gate terminal 317. This voltage induces negative electrons below the gate oxide film 304 as an insulator, and the portion of the p-well 309 immediately below the gate oxide film 304 changes to an n-channel, forming an inversion layer. Therefore, the n + 307 and p + 308 are electrically conducted by the inversion layer, and the nMOS
315 is turned on.

Also in the pMOS 316, the “H” level signal voltage applied to the input signal terminal 323 is applied via the gate terminal 320 to the n + poly-Si gate 312 which is a good electrical conductor. This voltage induces negative electrons below the gate oxide film 313 which is an insulator.
Since the portion of the substrate 314 immediately below the gate oxide film 313 is not inverted to the p-channel, p + 310 and p + 311
Does not conduct, and the pMOS 316 is turned off.

Therefore, the output signal terminal 324 is connected to GND.
The voltage of 302 is applied via the nMOS 315, and the output signal becomes “L” level.

Here, the signal voltage applied to the input signal terminal 323 changes from "L" to "H" or from "H" to "H".
L ", the nMOS 315 and the pMOS 31
6 are turned on simultaneously for a moment, and pMOS
316, a through current 325 flows through the nMOS 315. This through current 325 radiates an electromagnetic wave 326. At the same time, a conductor 327 arranged near the CMOS device composed of the nMOS 315 and the pMOS 316 and arranged so that a current flows in the direction opposite to the through current 325 flowing in the CMOS device flows through the same amount and in the opposite direction as the through current 325. A current 328 flows. An electromagnetic wave 329 is emitted by this through current 328.

The electromagnetic wave 326 and the electromagnetic wave 329 are electromagnetic waves having the same intensity and opposite phases. The electromagnetic waves 326 and the electromagnetic waves 329 cancel each other by being radiated from the vicinity.

As described above, in this embodiment, the electromagnetic waves radiated from the semiconductor integrated circuit having these semiconductor elements can be reduced. Further, the present embodiment is a CMO
The present invention can be applied to not only the S element but also other semiconductor elements such as a bipolar element and a Bi-CMOS element. In addition, the present embodiment is not limited to an inverter, and can be applied to other logic circuits such as an AND circuit.

(Embodiment 4) FIG. 4 is a diagram schematically showing a semiconductor integrated circuit according to an embodiment of the present invention. The upper part of FIG. 4 is a view of the semiconductor integrated circuit according to the present embodiment as viewed from above. The lower part of FIG. 4 shows a cross section of the semiconductor integrated circuit in this embodiment.

In FIG. 3, 401 is Vcc, 402 is GND, 403 is an n + poly Si gate, 404 is a gate oxide film, 405 is an insulating film, 406 is a field oxide film,
407 is n +, 408 is n +, 409 is p-well, 41
0 is p +, 411 is p +, 412 is an n + poly Si gate, 413 is a gate oxide film, 414 is an n substrate, 415 is an nMOS, 416 is a pMOS, and 417 is an nMOS 415
418 is a source terminal of the nMOS 415,
419 is a drain terminal of the nMOS 415, and 420 is pM
A gate terminal of the OS 416; a source terminal 421 of the pMOS 416; a drain terminal 422 of the pMOS 416;
23 is a gate terminal 417 of the nMOS 415 and the pMOS 4
An input signal terminal 424 for applying a signal to the 16 gate terminals 420 is an output signal terminal of a CMOS inverter composed of an nMOS 415 and a pMOS 416.
CMOS composed of MOS 415 and pMOS 416
The through current 426 flowing through the element is an electromagnetic wave radiated by the through current 425, and 427 is an nMOS 415 and a pMOS
416 and n substrate 4
42, a conductor arranged on the back side of 14 so that a current flows in a direction opposite to a through current 425 flowing through the CMOS element;
8 is a through current flowing through the conductor 427, and 429 is a through current 4
FIG.

The outline of the operation of the semiconductor integrated circuit of this embodiment will be described below with reference to FIG.

In FIG. 4, n + poly S
i-gate 403, gate oxide film 404, n + 407 and 4
08, a p well 409, a gate terminal 417, a source terminal 418, and a drain terminal 419 form an nMOS 415. Similarly, n + poly Si gate 412, gate oxide film 413, p + 410 and 411, gate terminal 42
0, pMO from source terminal 421, drain terminal 422
S416 is formed. These nMOS 415 and p
The MOS 416 is combined to form a CM on the n-substrate 414.
It constitutes an OS inverter.

When the signal voltage applied to input signal terminal 423 is at "L" level, the voltage is applied to gate terminal 4
20, an n + poly-Si gate 4 which is a good electrical conductor
12 is applied. This voltage induces a positive hole under the gate oxide film 413 which is an insulator,
The portion immediately below the gate oxide film 413 changes to a p-channel, forming an inversion layer. Therefore, p +
410 and p + 411 conduct electrically, and the pMOS 416
Turns on.

Also in the nMOS 415, the “L” level signal voltage applied to the input signal terminal 423 is applied via the gate terminal 417 to the n + poly-Si gate 403 which is an electric conductor. This voltage induces a positive hole under the gate oxide film 404 which is an insulator.
Since the portion of the p well 409 immediately below the gate oxide film 404 is not inverted to the n channel, n + 407 and n + 4
08 does not conduct electrically, and the nMOS 415 is turned off.

Therefore, the output signal terminal 424 is connected to Vcc
The voltage of 401 is applied via the pMOS 416, and the output signal becomes “H” level.

Conversely, when the signal voltage applied to the input signal terminal 423 is at the “H” level, the voltage is applied to the n + poly-Si gate 403 as a good conductor via the gate terminal 417. This voltage induces negative electrons below the gate oxide film 404, which is an insulator, and the portion of the p-well 409 immediately below the gate oxide film 404 changes to an n-channel to form an inversion layer. Therefore, the n + 407 and p + 408 are electrically conducted by this inversion layer, and the nMOS
415 is turned on.

Also in the pMOS 416, the “H” level signal voltage applied to the input signal terminal 423 is applied via the gate terminal 420 to the n + poly-Si gate 412 which is an electric conductor. This voltage induces negative electrons below the gate oxide film 413 which is an insulator.
Since the portion of the substrate 414 immediately below the gate oxide film 413 is not inverted to the p-channel, p + 410 and p + 411
Does not conduct, and the pMOS 416 is turned off.

Therefore, the output signal terminal 424 is connected to GND
The voltage of 402 is applied via the nMOS 415, and the output signal becomes “L” level.

Here, the signal voltage applied to the input signal terminal 423 changes from “L” to “H” or from “H” to “H”.
L ”, the nMOS 415 and the pMOS 41
6 are turned on simultaneously for a moment, and pMOS
416, a through current 425 flows through the nMOS 415. Electromagnetic wave 426 is emitted by this through current 425. At the same time, the through current 425 is also applied to the conductor 327 arranged near the CMOS device composed of the nMOS 415 and the pMOS 416 and on the back side of the n substrate 414 so that the current flows in the direction opposite to the through current 425 flowing through the CMOS device. A through current 428 flows in the same amount and in the opposite direction. An electromagnetic wave 429 is emitted by this through current 428.

The electromagnetic wave 426 and the electromagnetic wave 429 are electromagnetic waves having the same intensity and opposite phases. The electromagnetic waves 426 and 429 cancel each other out when they are radiated from the vicinity.

As described above, in this embodiment, the electromagnetic waves radiated from the semiconductor integrated circuit having these semiconductor elements can be reduced. Further, the present embodiment is a CMO
The present invention can be applied to not only the S element but also other semiconductor elements such as a bipolar element and a Bi-CMOS element. In addition, the present embodiment is not limited to an inverter, and can be applied to other logic circuits such as an AND circuit.

(Embodiment 5) FIG. 5 is a circuit diagram schematically showing a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 5, 501 and 503 are pMO
S, 502 and 504 are nMOS, and 505 is an input signal terminal. 506 is an output signal terminal connected to the output of the CMOS inverter composed of pMOS 501 and nMOS 502, 507 is the output signal terminal connected to the output of the CMOS inverter composed of pMOS 503 and nMOS 504, 508 is Vcc, and 509 is GND. is there.
Reference numeral 510 denotes a pMOS 501 and an nMOS 5 from Vcc 508.
02, a through current flowing through the GND 509 through the GND 511, an electromagnetic wave radiated by the through current 510, and 512 a Vc
The through current 513 flows from c508 through the pMOS 503 and the nMOS 504 to the GND 509, and the through current 513 is the through current 51.
2 shows an electromagnetic wave radiated by 2.

The outline of the operation of the semiconductor integrated circuit of this embodiment will be described below with reference to FIG.

In FIG. 5, pMOS 501 and nMOS 50
2 are combined to form a CMOS inverter. Further, a pMOS 503 and an nMOS 504 constitute a CMOS inverter which is arranged near the present CMOS inverter and arranged so that a flowing current flows in the opposite direction.

When the input signal voltage applied to input signal terminal 505 is at "L" level, pMOS 501 is turned on, nMOS 502 is turned off, output signal terminal 506 is electrically connected to Vcc 508, and output signal terminal 506 is output.
Becomes the "H" level. In this state, n
Since the MOS 502 is off, the through current 510 does not flow from Vcc 508 to GND 509 and the electromagnetic wave 511 does not flow.
Is not emitted. Similarly, the pMOS 503 is turned on, the nMOS 504 is turned off, the output signal terminal 507 is electrically connected to the Vcc 508, and the output signal terminal 507 is turned on.
Becomes the "H" level. Since nMOS 504 is off, Vcc 508 to GND 509
No through current 512 flows and no electromagnetic wave 513 is radiated.

Conversely, when the input signal voltage applied to the input signal terminal 505 is at the “H” level, the pMOS 50
1 is off, nMOS 502 is on and output signal terminal 5
Reference numeral 06 is electrically connected to the GND 509, and the voltage level of the output signal terminal 506 becomes "L" level. In this state, since the pMOS 501 is off, no current flows from the Vcc 508 to the GND 509 and the electromagnetic wave 511 is not radiated as in the case described above.

Similarly, pMOS 503 is off, nMOS
504 is turned on and the output signal terminal 507 is connected to GND 509.
And the voltage level of the output signal terminal 507 becomes “L” level. Since the pMOS 503 is off, the through current 5 from Vcc 508 to GND 509
12 does not flow and the electromagnetic wave 513 is not emitted.

However, when the input signal voltage applied to the input signal terminal 505 changes from “L” level to “H” level, and conversely, from “H” level to “L” level, p
The MOS 501 and the nMOS 502 are simultaneously turned on for a moment, and a through current 510 flows. Electromagnetic wave 511 is emitted by this through current 510.

At the same time, the pMOS 501 and the nMOS 5
02, and arranged so that the direction of the through current flowing therethrough is opposite to that of the CMOS inverter composed of
CMO composed of pMOS 503 and nMOS 504
Also in the S inverter, the pMOS 503 and the nMOS 5
04 turns on simultaneously for a moment, and a through current 512 flows. An electromagnetic wave 513 is emitted by this through current 512.

The electromagnetic wave 511 and the electromagnetic wave 513 are electromagnetic waves having opposite phases. The electromagnetic wave 511 and the electromagnetic wave 513 cancel each other by being radiated from the vicinity.

As described above, in the present embodiment, the electromagnetic waves radiated from the semiconductor integrated circuit having the plurality of semiconductor elements can be reduced. Further, the present embodiment is not limited to the CMOS device, but may be a bipolar device, a Bi-CMO
The present invention is also applicable to other semiconductor elements such as S elements. In addition, the present embodiment is not limited to an inverter, and can be applied to other logic circuits such as an AND circuit.

(Embodiment 6) FIG. 7 is a circuit diagram schematically showing a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 7, reference numeral 801 denotes a pMOS;
Is a pMOS near the pMOS 801 and the through current is pMOS
NMOS arranged so as to be in the direction opposite to the direction of the through current flowing through 801, Vcc 803, GND 804,
805 is an input signal terminal of a CMOS inverter composed of pMOS 801 and nMOS 802, and 806 is pMO
An output signal terminal of a CMOS inverter composed of S801 and nMOS 802; 807, a through current flowing through pMOS 801; 808, an electromagnetic wave radiated by through current 807; 809, a through current flowing through nMOS 802;
Reference numeral 10 denotes an electromagnetic wave radiated by the through current 809.

The outline of the operation of the semiconductor integrated circuit of this embodiment will be described below with reference to FIG.

In FIG. 7, pMOS 801 and nMOS 80
2 are combined to form a CMOS inverter. The input signal voltage applied to the input signal terminal 805 is "
If it is at the L level, the pMOS 801 is turned on and nM
The OS 802 is turned off and the output signal terminal 806 is connected to Vcc8
03, and the voltage level of the output signal terminal 806 becomes “H” level. In this state, the nMOS8
02 is off, so GND from Vcc 803
No current flows to 804, and no electromagnetic wave is emitted.

Conversely, when the input signal voltage applied to the input signal terminal 805 is at “H” level, the pMOS 80
1 is off, nMOS 802 is on and output signal terminal 8
Reference numeral 06 is electrically connected to the GND 804, and the voltage level of the output signal terminal 806 becomes "L" level. In this state, since the pMOS 801 is off, no current flows from the Vcc 803 to the GND 804 and no electromagnetic wave is radiated as in the case described above.

However, when the input signal voltage applied to the input signal terminal 805 changes from “L” level to “H” level and conversely from “H” level to “L” level, p
The MOS 801 and the nMOS 802 are simultaneously turned on for a moment, and a through current 807 flows through the pMOS 801. An electromagnetic wave 808 is radiated by the through current 807.

At the same time, the through current flowing near pMOS 801 and flowing through pMOS 801
NMOS 802 arranged in a direction opposite to the direction of
Also, the through current 8 in the same direction as the through current 807 and in the opposite direction
09 flows. This through current 809 causes electromagnetic waves 810
Is emitted.

The electromagnetic wave 808 and the electromagnetic wave 810 are electromagnetic waves having the same intensity and opposite phases. The electromagnetic waves 808 and 810 cancel each other out when they are radiated from the vicinity.

As described above, in this embodiment, the electromagnetic waves radiated from the semiconductor integrated circuit having these semiconductor elements can be reduced.

This embodiment can be applied not only to CMOS devices but also to other semiconductor devices such as bipolar devices and Bi-CMOS. In addition, the present embodiment is not limited to an inverter, and can be applied to other logic circuits such as an AND circuit.

(Embodiment 7) FIG. 6 is a diagram showing an embodiment of a semiconductor integrated circuit which further embodies the semiconductor integrated circuit of FIG.

In FIG. 6, reference numeral 601 denotes a pMOS;
Is an nMOS, and 603 is a pMOS 601 and an nMOS 60
2, an input signal terminal of a CMOS inverter composed of
An output signal terminal 604 is connected to the output of the above-described CMOS inverter.

605 is a pMOS, 606 is an nMOS, 6
07 is an input signal terminal of a CMOS inverter composed of a pMOS 605 and an nMOS 606, and 608 is an output signal terminal connected to the output of the CMOS inverter.

609 is connected to an external power supply means,
PMOS 601 and nMOS 60 inside a semiconductor integrated circuit
2, composed of pMOS 605 and nMOS 606
Terminal for supplying power to two CMOS inverters,
Reference numeral 610 denotes a terminal for connecting the two CMOS inverters to a ground outside the semiconductor integrated circuit.

611 is Vcc, 612 is GND, 613
Is a semiconductor chip on which the above two CMOS inverters are formed. Reference numeral 614 denotes a main power supply line for supplying power from the Vcc 611 to the inside of the semiconductor integrated circuit via the terminal 609. Reference numerals 620 and 621 denote main power supply lines 614 and the two CMOS inverters, respectively.
(Semiconductor element) to supply power to the semiconductor element.

The conductor 6 formed on the semiconductor chip 613
Reference numeral 15 denotes a main ground line connecting the inside of the semiconductor integrated circuit and an external ground via the terminal 610. 622,6
23 is a main ground line 615 and the two CMs described above.
This is a ground wiring for connecting to an OS inverter (semiconductor element). The main ground line is formed on the semiconductor chip 613 such that the direction of the current flowing in the vicinity of the main power supply line is opposite to that of the main power supply line.

Further, the power supply wirings 620 and 621 and the ground wirings 622 and 623 connected to the respective semiconductor elements are formed on the semiconductor chip 613 so that the current directions are opposite to each other.

The ground wiring is, as shown in FIG.
It is arranged close to the CMOS inverter so that a current in the opposite direction to the through current flowing in the CMOS inverter flows.

Reference numeral 616 denotes a C composed of a pMOS 601 and an nMOS 602 via a main power supply line 614.
The through current flowing into the MOS inverter, 617 is an electromagnetic wave radiated by the through current 616, and 618 is a pMOS
Reference numeral 619 denotes an electromagnetic wave radiated by the through current 618 from the CMOS inverter including the 601 and the nMOS 602 to the GND 612 via the conductor 615.

The outline of the operation of the semiconductor integrated circuit of this embodiment will be described below with reference to FIG.

When the input signal applied to the input signal terminal 603 changes from “L” level to “H” level or from “H” level to “L” level, the pMOS 601
And the nMOS 602 performs a switching operation to change the output signal applied to the output signal terminal 604. During this switching operation, the pMOS 601 and the nMOS 602 are simultaneously turned on for a moment, and the through current 616 is supplied to the main power supply line 614.
Flows. An electromagnetic wave 617 is radiated by the through current 616. At the same time, the main ground line 615
A through current 618 also flows through the device, and an electromagnetic wave 619 is radiated by the through current 618.

The electromagnetic wave 617 and the electromagnetic wave 619 are electromagnetic waves having opposite phases. The electromagnetic wave 617 and the electromagnetic wave 619 cancel each other by being radiated from the vicinity.

According to the present embodiment, as shown in FIG.
Since both the electromagnetic radiation caused by the through current flowing inside the semiconductor element and the electromagnetic radiation flowing through other wirings can be suppressed, the electromagnetic radiation emitted from the semiconductor integrated circuit can be suppressed to an extremely low level.

In the above description, the pMOS 601 and the nMOS 60
2 has been described, the same applies to a CMOS inverter composed of pMOS 605 and nMOS 606.

This embodiment can be applied not only to CMOS devices but also to other semiconductor devices such as bipolar devices and Bi-CMOS. In addition, the present embodiment is not limited to an inverter, and can be applied to other logic circuits such as an AND circuit.

[0106]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, according to the semiconductor integrated circuit of the present invention, an effect is obtained that unnecessary electromagnetic waves radiated from the semiconductor integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram schematically showing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram schematically showing a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 3 is a diagram showing an actual wiring example of the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing another example of the wiring example of the embodiment shown in FIG. 1;

FIG. 5 is a circuit diagram schematically showing a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 6 is a diagram showing a schematic structure of a semiconductor integrated circuit in which the embodiment shown in FIG. 1 is shown more specifically;

FIG. 7 is a diagram showing a schematic structure of a semiconductor integrated circuit according to still another embodiment of the present invention.

FIG. 8 is a diagram for explaining a problem of the related art.

[Explanation of symbols]

101 ... pMOS (p-channel MOS transistor),
102 ... nMOS (n-channel MOS transistor),
103: input signal terminal, 104: Vcc (power supply), 10
5: GND (earth), 106: output signal terminal, 107:
Penetration current, 108: electromagnetic wave, 109: conductor, 110: current, 111: electromagnetic wave 201: input signal terminal, 202:
Bipolar transistor (npn type), 203: resistor, 204: resistor, 205: Vcc, 206: GND,
207: current, 208: electromagnetic wave, 209: conductor, 210
... current, 211 ... electromagnetic wave, 212 ... output signal terminal 301 ... Vcc, 302 ... GND, 303 ... n + poly S
i-gate, 304: gate oxide film, 305: insulating film, 3
06 ... field oxide film, 307 ... n +, 308 ... n
+, 309 ... p well, 310 ... p +, 311 ... p +,
312 ... n + poly Si gate, 313 ... gate oxide film,
314 ... n substrate, 315 ... nMOS, 316 ... pMO
S, 317: Gate terminal, 318: Source terminal, 319
... Drain terminal, 320 ... Gate terminal, 321 ... Source terminal, 322 ... Drain terminal, 323 ... Input signal terminal,
324 ... output signal terminal, 325 ... through current, 326 ... electromagnetic wave, 327 ... conductor, 328 ... through current, 329 ... electromagnetic wave 401 ... Vcc, 402 ... GND, 403 ... n + poly S
i-gate, 404: gate oxide film, 405: insulating film, 4
06 ... field oxide film, 407 ... n +, 408 ... n
+, 409 ... p well, 410 ... p +, 411 ... p +,
412: n + poly Si gate, 413: gate oxide film,
414 ... n substrate, 415 ... nMOS, 416 ... pMO
S, 417: gate terminal, 418: source terminal, 419
... Drain terminal, 420 ... Gate terminal, 421 ... Source terminal, 422 ... Drain terminal, 423 ... Input signal terminal
424: output signal terminal, 425: through current, 426: electromagnetic wave, 427: conductor, 428: through current, 429: electromagnetic wave 501: pMOS, 502: nMOS, 503: pMO
S, 504... NMOS, 505... Input signal terminal, 506
... output signal terminal, 507 ... output signal terminal, 508 ... Vc
c, 509 GND, 510 through current, 511 electromagnetic wave, 512 through current, 513 electromagnetic wave 601 pMOS, 602 nMOS, 603 input signal terminal, 604 output signal terminal, 605 pMOS, 6
06 nMOS, 607 input signal terminal, 608 output signal terminal, 609 terminal, 610 terminal, 611 Vc
c, 612 ... GND, 613 ... semiconductor chip, 614 ...
Conductor, 615: Conductor, 616: Through current, 617: Electromagnetic wave, 618: Through current, 619: Electromagnetic wave 701: pMOS, 702: nMOS, 703: Input signal terminal, 704: Output signal terminal, 705: Terminal, 706
... terminal, 707 ... Vcc, 708 ... GND, 709 ... lead, 710 ... lead, 711 ... lead, 712 ... lead, 713 ... bonding wire, 714 ... bonding wire, 715 ... bonding wire, 716 ... bonding wire, 717 ... penetrating Current, 718 ... electromagnetic wave,
719: Through current, 720: electromagnetic wave, 721: semiconductor chip, 722: sealing material 801: pMOS, 802: nMOS, 803: Vc
c, 804 ... GND, 805 ... input signal terminal, 806 ...
Output signal terminal, 807: through current, 808: electromagnetic wave, 8
09: through current, 810: electromagnetic wave 1001, input signal terminal, 1002: pMOS, 1003: nMOS, 10
04 ... output signal terminal, 1005 ... GND, 1006 ... V
cc, 1007: through current, 1008: electromagnetic wave

Claims (10)

[Claims] 1. A semiconductor integrated circuit comprising a semiconductor element and a semiconductor chip on which the semiconductor element is mounted, wherein the current path is provided near the semiconductor element and parallel to a current path flowing inside the semiconductor element. A semiconductor integrated circuit comprising: an electromagnetic wave reduction unit that causes a current flowing in a direction opposite to a current flowing through the semiconductor integrated circuit. A power supply line connecting the semiconductor element and a main power supply line; and a ground line connecting the semiconductor element and a main ground line. 2. The semiconductor integrated circuit according to claim 1, wherein? Is one of the power supply wiring and the ground wiring in the opposite direction. 3. The semiconductor integrated circuit according to claim 1, wherein said electromagnetic wave reducing means is arranged on the same surface of said semiconductor chip as said surface on which said semiconductor element is installed. 4. The semiconductor integrated circuit according to claim 1, wherein said electromagnetic wave reducing means is arranged on a different surface of said semiconductor chip from a surface on which said semiconductor element is provided. 5. The semiconductor integrated circuit according to claim 2, wherein said power supply wiring and said ground wiring are arranged near each other and such that flowing currents are in opposite directions. 6. A semiconductor integrated circuit comprising a semiconductor element and a semiconductor chip on which the semiconductor element is mounted, wherein a current is provided near the semiconductor element and flows in a direction opposite to a through current flowing through the inside of the semiconductor element. A semiconductor integrated circuit comprising an electromagnetic wave reduction unit. 7. A first connection between a semiconductor element, a semiconductor chip on which the semiconductor element is mounted, a power supply wiring and a ground wiring connected to the semiconductor element, and a power supply wiring provided in the semiconductor element. And a second connection part for connecting the ground wiring provided in the semiconductor element to the semiconductor element, wherein one of the power supply wiring and the ground wiring is provided near the semiconductor element and the first And a semiconductor integrated circuit arranged in parallel with a line segment formed by the second connection portion. 8. At least two semiconductor elements for switching an output signal in response to the same input signal are arranged at positions near a relationship where currents flowing in the respective semiconductor elements flow in opposite directions during signal switching. Semiconductor integrated circuit. 9. A CM in which pMOS and nMOS are combined
A semiconductor device in an OS inverter, wherein the pMOS and the nMOS are turned back so as to face each other and connected in series. 10. The semiconductor integrated circuit according to claim 1, wherein no other wiring is arranged between said electromagnetic wave reducing means and said semiconductor chip.