JP2000243907A - Semiconductor chip and package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip capable of selecting a pad. SOLUTION: A semiconductor integrated circuit 60, a plurality of pads 17 and 39, a selective circuit 60 for selecting one pad from the pads 17 and 39 and connected it to the semiconductor integrated circuit 60 are formed in a semiconductor chip. The selective circuit 50 has transmission gates 51 and 56 controlled by a control signal S77.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor chip,
A package having a semiconductor chip.

[0002]

2. Description of the Related Art Japanese Patent Laying-Open No. 2-263385 discloses an invention of a semiconductor memory device. In this publication,
Using a dedicated bonding pad to select whether the relationship between input data and output data is positive or complementary,
It is disclosed that the relationship between the input data and the output data of the semiconductor memory device can be switched depending on whether or not bonding is performed to the bonding pad.

Japanese Patent Application Laid-Open No. 8-340020 discloses an invention of a semiconductor device in which a plurality of types are realized by a bonding option using the same mask. In this publication, a first type signal is output from a first type input circuit connected to a first pad, and a second type signal is output from a second type input circuit connected to a second pad. The signal is output to determine the type of the semiconductor device based on the two signals. On the other hand, the configuration is such that a pad of a specific circuit required only for the specific type is used as the second pad, thereby suppressing an increase in the number of optional pads dedicated to the type determination. It is disclosed that the chip area is reduced.

A semiconductor device, especially a semiconductor memory, requires high-speed operation, and a delay between a package pin (lead terminal) and a pad and a delay between a pad and a semiconductor integrated circuit are problems of the high-speed operation. It may be. In this case, the delay can be minimized by optimizing the delay among the three by adjusting the arrangement of the pins and pads and the semiconductor integrated circuit.

[0005]

In a semiconductor chip, if the positions of the pads are fixed, it is difficult to connect the package terminals and the pads by wire bonding or the like when incorporating the pads into different types of packages.
In some cases, the bonding wires are entangled with each other to make the delay evaluation difficult. An object of the present invention is to provide a semiconductor chip capable of selecting a pad and a package having the semiconductor chip.

[0006]

According to the present invention, there is provided a semiconductor chip comprising: a semiconductor integrated circuit; a plurality of pads; selecting one of the plurality of pads to select the one pad and the semiconductor integrated circuit; And a selection circuit for connecting
The semiconductor chip of the present invention preferably has a selection control circuit for generating a control signal for the selection circuit.

In the semiconductor chip of the present invention, more preferably, the selection control circuit has a cuttable metal member, a switch circuit, and a latch circuit, and one of the one end of the metal member and one end of the switch circuit. One is supplied with a power supply voltage and the other is supplied with a ground voltage. The other end of the switch circuit is connected to the other end of the metal member, and a connection point between the metal member and the switch circuit is provided. Is connected to the latch circuit. In the semiconductor chip of the present invention,
More preferably, a power-on reset signal that is at a high level or a low level for a predetermined time when the power of the semiconductor chip is turned on is supplied to a control terminal of the switch circuit. In the semiconductor chip of the present invention, more preferably, the metal member is a fuse that can be blown by irradiation with a laser beam.

A package according to the present invention is a package having a semiconductor chip, wherein the semiconductor chip is formed by selecting a semiconductor integrated circuit, a plurality of pads, and selecting one of the plurality of pads. And a selection circuit for connecting the pad and the semiconductor integrated circuit, and the one pad is connected to a lead terminal of the package. In the package of the present invention, preferably, the semiconductor chip has a selection control circuit for generating a control signal for the selection circuit. The package according to the present invention is preferably such that
And a bonding wire for connecting the pads to the lead terminals of the package.

In the package according to the present invention, preferably, the selection control circuit has a cuttable metal member, a switch circuit, and a latch circuit, and one of one end of the metal member and one end of the switch circuit. The power supply voltage is supplied to the other and the ground voltage is supplied to the other, the other end of the switch circuit is connected to the other end of the metal member, and a connection point between the metal member and the switch circuit is The latch circuit is connected. In the package of the present invention, it is preferable that a power-on reset signal that is at a high level or a low level for a predetermined time when the power of the semiconductor chip is turned on is supplied to a control terminal of the switch circuit. In the package of the present invention, preferably, the metal member is a fuse that can be blown by irradiation with a laser beam.

The semiconductor chip of the present invention has a selection circuit for selecting one of a plurality of pads and connecting the one pad to the semiconductor integrated circuit, so that the selection circuit is controlled by controlling the selection circuit. The semiconductor integrated circuit can be accessed from each of the plurality of pads. The semiconductor chip is included in the package of the present invention, and the selection circuit can select a pad suitable for connection with a terminal of the package from the plurality of pads.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an explanatory diagram showing an example of a package (IC package) having a semiconductor chip according to the present invention, and shows a cross-sectional structure of the package.

The package 10 includes a mold resin 1
, A semiconductor chip (IC chip) 3, bonding wires 4A and 4B, lead terminals 5A and 5B, and an island (die pad) 5C. The semiconductor chip 3
The island 5C is adhered to the island 5C using an epoxy resin such as conductive epoxy.
0 is connected to a lead terminal (not shown). Pads are formed on the surface 3A of the semiconductor chip 3, and the pads and the lead terminals are connected via bonding wires. The lead terminal 5A is connected to the bonding wire 4A, and the lead terminal 5B is connected to the bonding wire 4B.
It is connected to the. The surface 3A of the semiconductor chip 3 may be subjected to inner coating with a rubber-like resin or the like.

FIG. 2 is an explanatory diagram showing an example of a semiconductor chip according to the present invention. Pads 11 to 36 are formed on the surface 3A of the semiconductor chip 3. Pads 11-
Reference numeral 23 is arranged along one of the four opposing sides of the semiconductor chip 3, and pads 24 to 36 are arranged along the other opposing side. Pads 11-23
Are located between the pad 17 located at the center of the pad and the pad 30 located at the center of the pads 24-36.
42 are arranged. The first pad 17 and the second pad 39 are shaded in FIG. 2 for easy understanding.
The semiconductor chip 3 includes a semiconductor integrated circuit such as a semiconductor memory and a plurality of pads 1 including first and second pads.
7, 39, a selection circuit for selecting one pad of the plurality of pads 17, 39 and connecting the one pad to the semiconductor integrated circuit, and a selection circuit for generating a control signal for the selection circuit A control circuit is formed.

FIG. 3 is an explanatory diagram for explaining a selection circuit included in the semiconductor chip 3. The selection circuit 50 includes transmission gates (transfer gates) 51 and 56 and an inversion circuit 5.
And 5. First pad 17 and semiconductor integrated circuit 60
Is provided between the second pad 39 and the semiconductor integrated circuit 60.
6 is provided, and one of the first and second pads 17 and 39 is connected to the semiconductor integrated circuit 60 by the selection control signal S77 supplied to the control terminal 50C. First input terminal 50A of selection circuit 50
Are connected to the first pad 17. Selection circuit 50
The second input terminal 50 </ b> B is connected to the second pad 39. The output terminal 50Z of the selection circuit 50 is connected to the input terminal 60A of the semiconductor integrated circuit 60. The control terminal 50C of the selection circuit 50 is connected to a selection control circuit 70 described later.
Of the selection control signal S7
7 is supplied.

The transmission gate 51 includes an n-channel MOS transistor 52 and a p-channel MOS transistor 53
And The drain of the n-channel MOS transistor 52 and the source of the p-channel MOS transistor 53 are connected to a node n3. p-channel type MOS
The drain of the transistor 53 and the source of the n-channel MOS transistor 52 are connected to a node n4.

The transmission gate 56 includes an n-channel MOS transistor 57 and a p-channel MOS transistor 58
And The drain of the n-channel MOS transistor 57 and the source of the p-channel MOS transistor 58 are connected to a node n6. p-channel type MOS
The drain of the transistor 58 and the source of the n-channel MOS transistor 57 are connected to a node n7.

The control terminal 50C is connected to nodes n1 and n2. The node n1 is connected to the gate of the n-channel MOS transistor 52 and the input terminal of the inverting circuit 55, and the output terminal of the inverting circuit 55 is connected to the node n5. Node n2 is connected to the gate of p-channel MOS transistor 58. Node n3
Is connected to the first input terminal 50A. Node n
Reference numeral 5 is connected to the gate of the n-channel MOS transistor 57 and the gate of the p-channel MOS transistor 53. The node n6 is connected to the second input terminal 50B. The node n8 is connected to the nodes n4 and n7 and the output terminal 50Z.

When the signal voltage of the control signal S77 is at the high level (H level) which is the power supply voltage, the selection circuit 50
The transmission gate 51 is turned on, the first pad 17 is connected to the semiconductor integrated circuit 60 to make it conductive, and the first gate 17 is turned on.
From the pad 17 can be transmitted to the semiconductor integrated circuit 60. Further, the transmission gate 56 is turned off, and the second
Between the pad 39 and the semiconductor integrated circuit 60 is cut off.

When the signal voltage of the control signal S77 is at the low level (L level) which is the ground voltage, the selection circuit 50
The transmission gate 51 is turned off, and the first pad 17 and the semiconductor integrated circuit 60 are separated and cut off. Further, the transmission gate 56 is turned on, and the second pad 39 is turned on.
And the semiconductor integrated circuit 60 is connected to make it conductive,
The signal from the second pad 39 can be transmitted to the semiconductor integrated circuit 60. As described above, the signals from different pads can be taken into the semiconductor integrated circuit 60 by the control signal S77.

FIG. 4 is a circuit diagram showing an example of the selection control circuit included in the semiconductor chip 3. This selection control circuit 70
Is a cuttable metal member 73, a switch circuit 71,
And a latch circuit 75. One end of the metal member 73 is connected to a supply line 74 of the power supply voltage Vcc, and one end of the metal member 73 is supplied with the power supply voltage Vcc. One end of the switch circuit 71 is grounded.
Is supplied with a ground voltage GND. The other end of the switch circuit 71 is connected to the other end of the metal member 73 via a node n10. The input terminal 75A of the latch circuit 75 is connected to a node n10 which is a connection point between the metal member 73 and the switch circuit 71. The input terminal 70A of the selection control circuit 70 is connected to the control terminal of the switch circuit 71, and the input terminal 70A is connected to the semiconductor chip 3
When the power is turned on, a power-on reset signal S80 which is at a high level or a low level for a predetermined time is supplied.
The power-on reset signal is supplied to the switch circuit 7
1 control terminal.

The latch circuit 75 includes an n-channel type field effect transistor 72 which is an example of a field effect transistor capable of conducting or blocking between a source which is a first terminal and a drain which is a second terminal. , First and second inverting circuits 76 and 77. The field effect transistor 72 has a source supplied with the ground voltage GND,
The drain is connected to the node n11. Node n1
1 is connected to the node n10. Switch circuit 71
Is composed of an n-channel field effect transistor, the source is supplied with the ground voltage GND, and the drain is connected to the node n1.
0, and the gate is connected to the input terminal 70A. When the signal S80 supplied to the input terminal 70A is at a high level, the switch circuit 71 is turned on, and when the signal S80 supplied to the input terminal 70A is at a low level, the switch circuit 71 is turned off. First inverting circuit 76
Is connected to the node n11. The output terminal of the first inverting circuit 76 is connected to the node n12. The node n12 is connected to the gate, which is the control terminal of the field effect transistor 72, and the input terminal of the second inverting circuit 77. The output terminal of the second inverting circuit 77 is connected to the output terminal 70Z of the selection control circuit 70.

When the power is supplied to the semiconductor chip 70 when the metal member 73 is not cut, a high-level signal is supplied to the input terminal 70A for a predetermined time, for example, and then a low-level signal is supplied. . Input terminal 70A
Is supplied with a low-level signal, the node n10 and the input terminal 75A and the node n11 connected to the node n10 become high-level, and the first inverting circuit 76 generates a low-level output signal. Then, the second field-effect transistor 72 is turned off, and the second inverting circuit 77 generates a high-level output signal and supplies it to the output terminal 70Z of the selection control circuit 70. Selection control circuit 7
0 generates a control signal S77 for selecting the first pad 17 out of the plurality of pads 17 and 39, and
Output to 0.

When the semiconductor chip 70 is turned on when the metal member 73 is cut, a high-level signal is supplied to the input terminal 70A for a predetermined time, for example, and then a low-level signal is supplied. . When a high-level signal is supplied to the input terminal 70A, the field effect transistor included in the switch circuit 71 is turned on, and the node n10 and the input terminal 75A and the node n11 connected to the node n10 are at the ground potential GND. The first inverting circuit 76 generates a high-level output signal. Then, the second field-effect transistor 72 is turned on, and the second inverting circuit 77 generates a low-level output signal and supplies it to the output terminal 70Z of the selection control circuit 70. Subsequently, when a low-level signal is supplied to the input terminal 70A, the field effect transistor included in the switch circuit 71 is turned off, and the node n10 enters a floating state. On the other hand, the first inverting circuit 76 and the second field effect transistor 72 form a loop, and the input terminal of the inverting circuit 76 is at the ground potential GND, and a high level output signal is applied to the gate of the field effect transistor 72. Then, the field effect transistor 72 is turned on to set the input terminal of the inverting circuit 76 to the ground potential GND. The inverting circuit 77 generates a low-level output signal and supplies it to the output terminal 70Z of the selection control circuit 70. Therefore, when a signal that changes from a high level to a low level is supplied to the input terminal 70A, the output terminal 70Z continues to output the low-level control signal S77. Selection control circuit 70
Is the second pad 3 of the plurality of pads 17 and 39.
9 to generate a control signal S77 for selecting
Output to

As an example, the metal member 73 may be a metal wire that can be blown by irradiation with a laser beam such as a YAG laser or a fuse made of an alloy of lead and tin. According to the semiconductor chip 3, one of the first and second pads 17 and 39 can be selected in consideration of a positional relationship with a lead terminal of a package in which the semiconductor chip 3 is incorporated, a delay time, and the like. The arrangement of pads selected by the selection circuit 50 and the number of pads to be selected are made variable according to the pin arrangement of various packages, and the number of transmission gates of the selection circuit 50 is set to the number of pads to be selected. The connection between the pad and the pin can be achieved with one kind of semiconductor chip for various packages.

Since the semiconductor chip 3 has a pad selecting function, it is possible to select a pad at a position suitable for wire bonding, thereby facilitating wire bonding. For example, when the first pad 17 is located at a position where wire bonding is easier, a control signal for selecting the first pad 17 is supplied to the selection circuit 50, and the second pad 39 is located at a position where wire bonding is easier. In the case of, a control signal for selecting the second pad 39 is supplied to the selection circuit 50. In the package 10, one pad selected by the selection circuit 50 and a lead terminal are connected by wire bonding. Further, since the semiconductor chip 3 has a pad selection function, it is possible to connect pads and pins with a single type of semiconductor chip for a plurality of packages having different pin arrangements.
Further, it is possible to prevent the evaluation of the delay between the pin and the pad from becoming difficult due to complicated bonding wires. In the selection control circuit 70, the first inversion circuit 76 and the second field effect transistor 72 in the latch circuit 75
By using the loop, the configuration can be made resistant to noise.

As the inverting circuits 55, 76, 77, CM
An OS (Complimentary Metal Oxide Semiconductor) inverter may be used. Field effect transistor 71,
Reference numeral 72 may be an insulated gate field effect transistor, and transmission gates 51 and 56 may be configured using an insulated gate field effect transistor. The control terminal 50C of the selection circuit 50 is connected to a ground terminal and a power terminal using the metal member, and the metal member between the control terminal 50C and the ground terminal, or between the control terminal 50C and the power terminal. Is cut off, and the power supply voltage V is applied to the control terminal 50C.
It may be configured to supply cc or the ground voltage GND.
The above embodiment is an example of the present invention, and the present invention is not limited to the above embodiment.

[0027]

Since the semiconductor chip of the present invention has a pad selection function, it is possible to select a pad at a position suitable for connection between the semiconductor chip and an external terminal, thereby facilitating connection with the external terminal. It is possible. Further, when the arrangement of the external terminals is different, the connection between the pads and the external terminals can be made by one kind of semiconductor chip by selecting the pads.

Since the semiconductor chip of the package of the present invention has a pad selecting function, a pad at a position suitable for connection between the semiconductor chip and the external terminal can be selected, and connection with the external terminal can be facilitated. It is possible. Further, for a plurality of packages having different pin arrangements, the connection between the pad and the pin can be performed with one type of semiconductor chip.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing an example of a package having a semiconductor chip according to the present invention.

FIG. 2 is an explanatory diagram illustrating an example of a semiconductor chip according to the present invention.

FIG. 3 is an explanatory diagram illustrating an example of a selection circuit included in the semiconductor chip of FIG. 2;

FIG. 4 is a circuit diagram illustrating an example of a selection control circuit included in the semiconductor chip of FIG. 2;

[Explanation of symbols]

1 ... mold resin, 3 ... semiconductor chip (IC chip),
3A: Surface (circuit forming surface), 4A, 4B: Bonding wire, 5A, 5B: Lead terminal (pin), 5C: Island (die pad), 10: Package, 11 to 36
... Pads, 50 ... Selection circuits, 51, 56 ... Transmission gates (transfer gates), 52,57 ... Field effect transistors (n-channel field effect transistors), 5
3, 58 ... field-effect transistor (p-channel type field-effect transistor), 50A ... first input terminal, 50B ...
2nd input terminal, 50C: control terminal, 50Z: output terminal, 60: semiconductor integrated circuit, 60A: input terminal, 70 ...
Selection control circuit, 70A: input terminal, 70Z: output terminal,
71: Field effect transistor, 72: Field effect transistor (switch circuit), 73: Metal member, 74: Power supply line, 76: First inversion circuit, 77: Second inversion circuit, G
ND: ground voltage (ground voltage), n1 to n8, n1
1, n12 node, n10 node (connection point), S7
7: control signal, Vcc: power supply voltage.

Claims (13)

[Claims] A semiconductor integrated circuit, a plurality of pads, and a pad selected from the plurality of pads.
A semiconductor chip having a plurality of pads and a selection circuit for connecting the semiconductor integrated circuit. 2. The semiconductor chip according to claim 1, further comprising a selection control circuit for generating a control signal for said selection circuit. 3. The selection control circuit has a cuttable metal member, a switch circuit, and a latch circuit, and one of one end of the metal member and one end of the switch circuit is supplied with a power supply voltage. At the same time, a ground voltage is supplied to the other end, the other end of the switch circuit is connected to the other end of the metal member, and the connection point between the metal member and the switch circuit is connected to the latch circuit. The semiconductor chip according to claim 2. 4. The semiconductor chip according to claim 3, wherein a control terminal of said switch circuit is supplied with a power-on reset signal which becomes a high level or a low level for a predetermined time when power is supplied to said semiconductor chip. 5. The switch circuit includes a first field-effect transistor capable of conducting or cutting off between a first terminal and a second terminal, and the latch circuit includes a first field-effect transistor. A second field-effect transistor capable of conducting or blocking between a first terminal and a second terminal, and first and second inverting circuits, wherein the first and second electric fields The first terminal of the effect transistor is supplied with the ground voltage, the second terminals of the first and second field effect transistors are connected to the connection point, and the input terminal of the first inverting circuit Is connected to a second terminal of the second field-effect transistor, and an output terminal of the first inversion circuit is a control terminal of the second field-effect transistor and an input of the second inversion circuit. Connected to the terminal, Serial output terminal of the second inverting circuit, said latch circuit according to claim 3, wherein the semiconductor chip is connected to the output terminal of the. 6. The semiconductor chip according to claim 3, wherein said metal member is a fuse that can be blown by irradiation of a laser beam. 7. A package having a semiconductor chip, wherein the semiconductor chip comprises: a semiconductor integrated circuit; a plurality of pads; and selecting one of the plurality of pads to select one of the plurality of pads.
A package having a selection circuit for connecting the plurality of pads and the semiconductor integrated circuit, wherein the one pad and a lead terminal of the package are connected; 8. The package according to claim 7, wherein said semiconductor chip has a selection control circuit for generating a control signal for said selection circuit. 9. The selection control circuit includes a cuttable metal member, a switch circuit, and a latch circuit, and one of one end of the metal member and one end of the switch circuit is supplied with a power supply voltage. At the same time, a ground voltage is supplied to the other end, the other end of the switch circuit is connected to the other end of the metal member, and the connection point between the metal member and the switch circuit is connected to the latch circuit. The package according to claim 8. 10. The package according to claim 9, wherein a control terminal of said switch circuit is supplied with a power-on reset signal which becomes a high level or a low level for a predetermined time when power is supplied to said semiconductor chip. 11. A switch circuit comprising a first terminal and a second terminal.
The first terminal capable of conducting or blocking between the first terminal and the second terminal
Wherein the latch circuit has a second field-effect transistor capable of conducting or blocking between a first terminal and a second terminal; and a first and second field-effect transistor. And an inverting circuit, wherein the ground voltage is supplied to first terminals of the first and second field effect transistors, and a second terminal of the first and second field effect transistors is An input terminal of the first inverting circuit is connected to a second terminal of the second field-effect transistor; an output terminal of the first inverting circuit is connected to the 10. The control terminal of the second field-effect transistor and an input terminal of the second inverting circuit, and an output terminal of the second inverting circuit is connected to an output terminal of the latch circuit. Package. 12. The package according to claim 9, wherein said metal member is a fuse which can be blown by irradiation of a laser beam. 13. The package according to claim 7, further comprising a bonding wire connecting said one pad and a lead terminal of said package.