JPH0530074B2 - - Google Patents

Info

Publication number
JPH0530074B2
JPH0530074B2 JP58197524A JP19752483A JPH0530074B2 JP H0530074 B2 JPH0530074 B2 JP H0530074B2 JP 58197524 A JP58197524 A JP 58197524A JP 19752483 A JP19752483 A JP 19752483A JP H0530074 B2 JPH0530074 B2 JP H0530074B2
Authority
JP
Japan
Prior art keywords
insulating film
type
island
channel mos
mos element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58197524A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6089957A (ja
Inventor
Tetsutada Sakurai
Akikazu Oono
Katsutoshi Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58197524A priority Critical patent/JPS6089957A/ja
Publication of JPS6089957A publication Critical patent/JPS6089957A/ja
Publication of JPH0530074B2 publication Critical patent/JPH0530074B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP58197524A 1983-10-24 1983-10-24 相補形半導体装置 Granted JPS6089957A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58197524A JPS6089957A (ja) 1983-10-24 1983-10-24 相補形半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58197524A JPS6089957A (ja) 1983-10-24 1983-10-24 相補形半導体装置

Publications (2)

Publication Number Publication Date
JPS6089957A JPS6089957A (ja) 1985-05-20
JPH0530074B2 true JPH0530074B2 (https=) 1993-05-07

Family

ID=16375895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58197524A Granted JPS6089957A (ja) 1983-10-24 1983-10-24 相補形半導体装置

Country Status (1)

Country Link
JP (1) JPS6089957A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01179341A (ja) * 1988-01-06 1989-07-17 Hitachi Ltd 複合絶縁分離基板およびその製造方法
JPH0290546A (ja) * 1988-09-27 1990-03-30 Matsushita Electric Works Ltd 絶縁層分離基板の製造方法
US7989282B2 (en) * 2009-03-26 2011-08-02 International Business Machines Corporation Structure and method for latchup improvement using through wafer via latchup guard ring

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5725983B2 (https=) * 1973-12-27 1982-06-02
JPS5840852A (ja) * 1981-09-03 1983-03-09 Toshiba Corp 相補型ｍｏｓ半導体装置及びその製造方法
JPS5840851A (ja) * 1981-09-03 1983-03-09 Toshiba Corp 相補型ｍｏｓ半導体装置及びその製造方法
JPS5919347A (ja) * 1982-07-23 1984-01-31 Matsushita Electric Ind Co Ltd 半導体集積回路およびその製造方法
JPS59208851A (ja) * 1983-05-13 1984-11-27 Hitachi Ltd 半導体装置とその製造法

Also Published As

Publication number Publication date
JPS6089957A (ja) 1985-05-20

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