JPH05299436A - Thin-film transistor and liquid crystal display using the thin-film transistor - Google Patents

Thin-film transistor and liquid crystal display using the thin-film transistor

Info

Publication number
JPH05299436A
JPH05299436A JP10640192A JP10640192A JPH05299436A JP H05299436 A JPH05299436 A JP H05299436A JP 10640192 A JP10640192 A JP 10640192A JP 10640192 A JP10640192 A JP 10640192A JP H05299436 A JPH05299436 A JP H05299436A
Authority
JP
Japan
Prior art keywords
semiconductor film
liquid crystal
crystal display
film transistor
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10640192A
Other languages
Japanese (ja)
Inventor
Masaru Takahata
勝 高畠
Makoto Tsumura
津村  誠
Keiji Nagae
慶治 長江
Ryoji Oritsuki
良二 折付
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10640192A priority Critical patent/JPH05299436A/en
Publication of JPH05299436A publication Critical patent/JPH05299436A/en
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To obtain a low-cost active matrix liquid crystal display by a method wherein the resist is patterned on an intrinsic semiconductor film and then an extrinsic semiconductor film and a source/drain electrode are deposited and after that, the resist is removed and the extrinsic semiconductor film and the source/drain electrode are patterned. CONSTITUTION:The resist is patterned on an intrinsic semiconductor film 'i'. Then, an extrinsic semiconductor film n<+> and a source/drain electrode Cr are deposited. After that, the extrinsic semiconductor film n<+> and the source/drain electrode Cr are patterned by removing the resist. In this TET manufacturing method, the extrinsic semiconductor film n<+> is not etched and therefore a channel protective film is not required to be inserted and eventually the intrinsic semiconductor film 'i' can be formed very thin. Consequently, the number of masks is reduced and the number of layers of the TFT is also reduced and therefore the active matrix liquid crystal display manufacturing cost can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は液晶表示装置に係り、特
にアクティブマトリクス液晶表示装置の低コスト化に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to cost reduction of an active matrix liquid crystal display device.

【0002】[0002]

【従来の技術】従来、アクティブマトリクス液晶表示装
置に用いる薄膜トランジスタ(以下、TFTと略す)の
デバイス構造としては、例えば、日経エレクトロニク
ス、日経マイクロデバイス編『フラットパネル・ディス
プレイ '91』に記されているように、真性半導体膜と
ソース/ドレイン電極間に外因性半導体膜を挿入してい
た。図4は従来のTFTのデバイス構造であり、図中に
おいて、下方のCrはゲート電極、下方のSiNはゲー
ト絶縁膜、iは真性半導体膜、上方のSiNはチャネル
保護膜、n+は外因性半導体膜、上方のCrはソース/
ドレイン電極である。ここで、上記TFTの真性半導体
膜厚は、通常、0.1μm 以下である。TFTにおいて
は、真性半導体膜厚が極薄になると、TFTのオン電流
は増大し、オフ電流は低減される。
2. Description of the Related Art Conventionally, a device structure of a thin film transistor (hereinafter abbreviated as TFT) used in an active matrix liquid crystal display device is described in, for example, "Flat Panel Display '91" edited by Nikkei Electronics, Nikkei Microdevices. As described above, the extrinsic semiconductor film is inserted between the intrinsic semiconductor film and the source / drain electrodes. FIG. 4 shows a conventional TFT device structure. In the figure, Cr below is a gate electrode, SiN below is a gate insulating film, i is an intrinsic semiconductor film, SiN above is a channel protective film, and n + is an extrinsic semiconductor. Membrane, upper Cr is source /
It is a drain electrode. Here, the intrinsic semiconductor film thickness of the TFT is usually 0.1 μm or less. In the TFT, when the intrinsic semiconductor film thickness becomes extremely thin, the on-current of the TFT increases and the off-current decreases.

【0003】[0003]

【発明が解決しようとする課題】上記した従来技術は、
次のような問題点を有していた。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
It had the following problems.

【0004】すなわち、上記デバイス構造だとn+層の
パターニングの際にチャネル部となるi層がエッチング
されないようチャネル保護膜が追加される。これは、エ
ッチングにおける、n+層とi層の選択比がない理由に
よるものである。このことにより、マスク枚数が増加
し、かつ、TFTの層数が増加するので、アクティブマ
トリクス液晶表示装置のコストが増加する。
That is, in the above device structure, a channel protective film is added so as to prevent the i layer serving as a channel portion from being etched when the n + layer is patterned. This is because there is no selection ratio between the n + layer and the i layer in etching. This increases the number of masks and the number of TFT layers, which increases the cost of the active matrix liquid crystal display device.

【0005】本発明の目的は、以上に述べた問題点を解
決し、低コストのアクティブマトリクス液晶表示装置を
提供することである。
An object of the present invention is to solve the above problems and provide a low cost active matrix liquid crystal display device.

【0006】[0006]

【課題を解決するための手段】前記の問題点を解決する
ために、本発明は電界効果型の薄膜トランジスタの製造
方法において、真性半導体膜上にレジストをパターニン
グし、その後、外因性半導体膜,ソース/ドレイン電極
を堆積し、その後、上記レジストを取り除くことにより
外因性半導体膜,ソース/ドレイン電極をパターニング
する製造方法を有する薄膜トランジスタ及びそれを用い
た液晶表示装置を提案するものである。
In order to solve the above problems, the present invention provides a method for manufacturing a field effect type thin film transistor, in which a resist is patterned on an intrinsic semiconductor film, and then an extrinsic semiconductor film and a source are formed. This invention proposes a thin film transistor and a liquid crystal display device using the thin film transistor, which has a manufacturing method of patterning an extrinsic semiconductor film and a source / drain electrode by depositing a / drain electrode and then removing the resist.

【0007】[0007]

【作用】上記したTFTの製造方法では、外因性半導体
膜のエッチングを用いないので、チャネル保護膜を挿入
せずに真性半導体膜厚を極薄にできる。したがって、マ
スク枚数は低減され、かつ、TFTの層数が減少するの
でアクティブマトリクス液晶表示装置のコストが低減で
きる。
In the TFT manufacturing method described above, since the etching of the extrinsic semiconductor film is not used, the intrinsic semiconductor film can be made extremely thin without inserting the channel protective film. Therefore, the number of masks is reduced and the number of TFT layers is reduced, so that the cost of the active matrix liquid crystal display device can be reduced.

【0008】[0008]

【実施例】以下に図面を参照して本発明を詳細に説明す
る。
The present invention will be described in detail below with reference to the drawings.

【0009】図1は本発明のTFTの製作手順を示した
ものである。すなわち、真性半導体膜上にレジストをパ
ターニングし((a)参照)、その後、外因性半導体
膜,ソース/ドレイン電極を堆積し((b)参照)、そ
の後、上記レジストを取り除くことにより外因性半導体
膜,ソース/ドレイン電極をパターニングする((c)
参照)製作手順である。上記したTFTの製造方法で
は、外因性半導体膜のエッチングを用いないので、チャ
ネル保護膜を挿入せずに真性半導体膜厚を極薄にでき
る。したがって、マスク枚数は低減され、かつ、TFT
の層数が減少するのでアクティブマトリクス液晶表示装
置のコストが低減できる。
FIG. 1 shows a manufacturing procedure of the TFT of the present invention. That is, a resist is patterned on the intrinsic semiconductor film (see (a)), then an extrinsic semiconductor film and source / drain electrodes are deposited (see (b)), and then the resist is removed to remove the extrinsic semiconductor. Pattern the film and the source / drain electrodes ((c))
Refer to) Manufacturing procedure. In the above-mentioned TFT manufacturing method, since the etching of the extrinsic semiconductor film is not used, the intrinsic semiconductor film thickness can be made extremely thin without inserting the channel protective film. Therefore, the number of masks is reduced, and the TFT
Since the number of layers is reduced, the cost of the active matrix liquid crystal display device can be reduced.

【0010】図2,図3,図4は本発明のTFTをアク
ティブマトリクス液晶ディスプレイに適用した場合の製
作手順である。
2, FIG. 3 and FIG. 4 show a manufacturing procedure when the TFT of the present invention is applied to an active matrix liquid crystal display.

【0011】まず、ガラス基板上にITO(Indiu
m Tin Oxide),Ti,Al−Si−Tiを
スパッタリングし、パターニングする((a)参照)。
次に、SiN,iを連続堆積し((b)参照)、i,S
iN,Al−Si−Ti,Tiをパターニングする
((c)参照)。次に、i層上にレジストをパターニン
グし、その後、n+層,Cr電極を堆積し((d)参
照)、その後、上記レジストを取り除くことによりn+
層,Cr電極をパターニングする。次に、PAS膜を堆
積しパターニングし((e)参照)、その後、液晶工程
を行う((f)参照)。
First, ITO (Indiu) is formed on a glass substrate.
m Tin Oxide), Ti, and Al-Si-Ti are sputtered and patterned (see (a)).
Next, SiN, i is continuously deposited (see (b)), and i, S
iN, Al-Si-Ti, and Ti are patterned (see (c)). Next, a resist is patterned on the i layer, then an n + layer and a Cr electrode are deposited (see (d)), and then the resist is removed to remove n +.
The layer and the Cr electrode are patterned. Next, a PAS film is deposited and patterned (see (e)), and then a liquid crystal process is performed (see (f)).

【0012】以上、本発明のTFTを用いるとTFT基
板は4枚マスクで形成できる。したがって、アクティブ
マトリクス液晶表示装置のコストが低減できる。
As described above, when the TFT of the present invention is used, the TFT substrate can be formed with four masks. Therefore, the cost of the active matrix liquid crystal display device can be reduced.

【0013】図5は本発明のTFTをアクティブマトリ
クス液晶ディスプレイに適用した場合の端子部の構造で
ある。図中に示すように接続端子部にはITOのみが露
出しているので信頼性は高い。
FIG. 5 shows the structure of a terminal portion when the TFT of the present invention is applied to an active matrix liquid crystal display. As shown in the figure, only the ITO is exposed at the connection terminal portion, so the reliability is high.

【0014】[0014]

【発明の効果】以上の説明から明らかなように、本発明
によれば、外因性半導体膜のエッチングを用いないの
で、チャネル保護膜を挿入せずに真性半導体膜厚を極薄
にできる。したがって、マスク枚数は低減され、かつ、
TFTの層数が減少するのでアクティブマトリクス液晶
表示装置のコストが低減できる。
As is apparent from the above description, according to the present invention, since the etching of the extrinsic semiconductor film is not used, the intrinsic semiconductor film thickness can be made extremely thin without inserting the channel protective film. Therefore, the number of masks is reduced, and
Since the number of TFT layers is reduced, the cost of the active matrix liquid crystal display device can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のTFTの製作手順を示す図である。FIG. 1 is a diagram showing a manufacturing procedure of a TFT of the present invention.

【図2】本発明のTFTをアクティブマトリクス液晶デ
ィスプレイに適用した場合の製作手順を示す図である。
FIG. 2 is a diagram showing a manufacturing procedure when the TFT of the present invention is applied to an active matrix liquid crystal display.

【図3】同じく製作手順を示す図である。FIG. 3 is a diagram showing a manufacturing procedure of the same.

【図4】同じく製作手順を示す図である。FIG. 4 is a diagram showing a manufacturing procedure of the same.

【図5】本発明のTFTをアクティブマトリクス液晶デ
ィスプレイに適用した場合の端子部の構造図である。
FIG. 5 is a structural diagram of a terminal portion when the TFT of the present invention is applied to an active matrix liquid crystal display.

【図6】従来のTFTのデバイス構造図である。FIG. 6 is a device structure diagram of a conventional TFT.

【符号の説明】[Explanation of symbols]

Cr…クロム、SiN…窒化シリコン膜、i…真性半導
体膜、ITO…インジウム・ティン・オキサイド、Ti
…チタン、Al−Si−Ti…アルミニウム−シリコン
−チタン、PAS膜…保護膜、n+…外因性半導体膜。
Cr ... Chromium, SiN ... Silicon nitride film, i ... Intrinsic semiconductor film, ITO ... Indium tin oxide, Ti
... Titanium, Al-Si-Ti ... Aluminum-silicon-titanium, PAS film ... Protective film, n + ... Extrinsic semiconductor film.

フロントページの続き (72)発明者 折付 良二 千葉県茂原市早野3300番地 株式会社日立 製作所茂原工場内Front page continued (72) Inventor Ryoji Oritsuki 3300 Hayano, Mobara-shi, Chiba Hitachi Ltd. Mobara factory

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】電界効果型の薄膜トランジスタの製造方法
において、真性半導体膜上にレジストをパターニング
し、その後、外因性半導体膜,ソース/ドレイン電極を
堆積し、その後、上記レジストを取り除くことにより外
因性半導体膜,ソース/ドレイン電極をパターニングす
ることを特徴とする薄膜トランジスタ。
1. A method of manufacturing a field effect thin film transistor, wherein a resist is patterned on an intrinsic semiconductor film, and then an extrinsic semiconductor film and source / drain electrodes are deposited, and then the resist is removed to remove the extrinsic film. A thin film transistor characterized by patterning a semiconductor film and source / drain electrodes.
【請求項2】請求項1記載の薄膜トランジスタの真性半
導体膜厚は0.1μm 以下であることを特徴とする薄膜
トランジスタ。
2. The thin film transistor according to claim 1, wherein the intrinsic semiconductor film thickness is 0.1 μm or less.
【請求項3】画素トランジスタとして、請求項2記載の
薄膜トランジスタを用いることを特徴とする液晶表示装
置。
3. A liquid crystal display device using the thin film transistor according to claim 2 as a pixel transistor.
JP10640192A 1992-04-24 1992-04-24 Thin-film transistor and liquid crystal display using the thin-film transistor Pending JPH05299436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10640192A JPH05299436A (en) 1992-04-24 1992-04-24 Thin-film transistor and liquid crystal display using the thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10640192A JPH05299436A (en) 1992-04-24 1992-04-24 Thin-film transistor and liquid crystal display using the thin-film transistor

Publications (1)

Publication Number Publication Date
JPH05299436A true JPH05299436A (en) 1993-11-12

Family

ID=14432670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10640192A Pending JPH05299436A (en) 1992-04-24 1992-04-24 Thin-film transistor and liquid crystal display using the thin-film transistor

Country Status (1)

Country Link
JP (1) JPH05299436A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812489B2 (en) 1996-07-03 2004-11-02 Hitachi, Ltd. Liquid crystal display
KR100529569B1 (en) * 1997-12-09 2006-02-08 삼성전자주식회사 Manufacturing method of thin film transistor for liquid crystal display device
KR100865257B1 (en) * 2002-09-16 2008-10-24 엘지디스플레이 주식회사 Method of manufacturing Thin Film Transistor for Liquid Crystal Display Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812489B2 (en) 1996-07-03 2004-11-02 Hitachi, Ltd. Liquid crystal display
KR100529569B1 (en) * 1997-12-09 2006-02-08 삼성전자주식회사 Manufacturing method of thin film transistor for liquid crystal display device
KR100865257B1 (en) * 2002-09-16 2008-10-24 엘지디스플레이 주식회사 Method of manufacturing Thin Film Transistor for Liquid Crystal Display Device

Similar Documents

Publication Publication Date Title
JP3238020B2 (en) Method for manufacturing active matrix display device
JP2637079B2 (en) Method of fabricating a thin film field effect transistor in an active matrix liquid crystal display
JP2000002892A (en) Liquid crystal display device, matrix array substrate, and manufacture thereof
JPH06295924A (en) Manufacture of liquid crystal display device
JPH0282571A (en) Active matrix substrate and its manufacture
JPH04372934A (en) Manufacture of array substrate for liquid crystal display device
JP3352191B2 (en) Method for manufacturing thin film transistor
US6291255B1 (en) TFT process with high transmittance
JP3234168B2 (en) Method for manufacturing TFT array substrate
KR100272255B1 (en) Manufacturing mathod for thin film transistor
JPH05299436A (en) Thin-film transistor and liquid crystal display using the thin-film transistor
TW400653B (en) Thin film transistor, LCD having thin film transistors, and method for making TFT array board
JPH07153965A (en) Manufacture of thin-film transistor
JP2574837B2 (en) Thin film transistor matrix and manufacturing method thereof
JPH06242453A (en) Active matrix type liquid crystal display device
JPH10209452A (en) Thin film transistor and its manufacture
JPH04240824A (en) Array substrate for liquid crystal display device
JPH07110496A (en) Production of active matrix panel
JPS63119256A (en) Manufacture of active matrix substrate
JP2775883B2 (en) Method of manufacturing thin film transistor matrix
JP3200638B2 (en) Wiring formation method
JPH07325321A (en) Production of liquid crystal display device
JPH01227127A (en) Thin-film transistor array
JPH039569A (en) Thin film transistor
JPH06252171A (en) Manufacture of active matrix panel