JPH07153965A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To taper a cross section of a gate electrode by a method wherein a Cr film is formed and a mixed liquid containing cerium nitrate ammonium, nitrate and water as main components is used as an etchant to etch Cr to form a gate electrode. CONSTITUTION:A Cr 19 film is formed on a transparent substrate 10 by sputtering, etc. A resist film 20 is rotatably applied and formed on the Cr film and exposed to light and developed to form gate wiring patterns. This substrate 10 is etched with a mixed liquid of cerium nitrate ammonium, nitrate and water as an etchant and with the resist film 20 as a mask, and the Cr 19 is patterned on a gate wiring. Thus, a gate electrode 11 can be tapered and throughput can be enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor which is frequently used as a switching element in an active matrix type liquid crystal display (LCD).

[0002]

2. Description of the Related Art Liquid crystal display devices have advantages such as small size, thin shape, and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a thin film transistor (hereinafter abbreviated as TFT) as a switching element can display a fine moving image,
Is used for display devices such as.

The active matrix type liquid crystal display device is
The structure is such that a substrate on which display electrodes connected to TFTs are arranged in a matrix and a substrate having a common electrode are attached with a liquid crystal layer interposed therebetween. The TFT is a switching element that selects an input data signal to the display electrode, and is a FET that uses amorphous silicon (a-Si) or polysilicon (p-Si) as a channel layer. The gate electrode and the drain electrode are connected to the gate line and the drain line, respectively, and the source electrode is connected to the display electrode. The display electrode and the common electrode are transparent electrodes formed of, for example, a mixture of indium oxide and tin oxide (hereinafter abbreviated as ITO).

The gate line group is line-sequentially scanned and selected, all the TFTs in the same row are turned on, and a data signal synchronized with the scanning signal is input to the display electrodes. The potential of the common electrode is also set in synchronization with the scanning signal, and the desired effective voltage is applied to the liquid crystal layer in the gap with the display electrode to drive the liquid crystal, and the light transmittance is adjusted for each pixel. It The driving state of the liquid crystal is stored as liquid crystal capacitance for one frame period when the TFT is turned off, and is rewritten by AC inversion in the next frame.

FIG. 6 shows a cross-sectional structure of a conventional thin film transistor. A gate electrode (11) patterned with Cr is provided on a transparent substrate (10) such as glass,
A-Si (13), an etching stopper (14), and N ⁺ a-Si (15) are laminated in an island shape on the gate electrode (11) with a gate insulating film (12) such as SiN _x interposed therebetween. Further, source / drain electrodes (16, 17) of Al or the like are provided on the N ⁺ a-Si (15). The source electrode (16) is connected to the ITO display electrode (18).

The gate electrode (11) is formed as follows. First, 1500 by sputtering Cr
After being laminated to a thickness of about Å, a resist film having a thickness of about 1.5 μm is coated, and baking (prebaking) at about 70 ° C. is performed as a pretreatment for exposure. Then, after exposure and development are performed to transfer the mask pattern, as a post-exposure treatment, 14
Baking (post-baking) at around 0 ° C is performed. Then, using this resist as a mask, etching is performed using a mixed solution of cerium ammonium nitrate, perchloric acid and water as an etchant, and finally, the resist that is no longer needed is removed.

[0007]

Baking before and after exposure is mainly performed to improve the adhesion between the resist film and the film to be etched, that is, Cr. For example, prebaking
The solvent of the resist is removed and post-baking is performed for the purpose of drying the resist in order to remove the developing solution, rinse solution, water, etc. in the resist remaining after the development.
When the adhesiveness of the resist is improved in this way, the cross-sectional shape of Cr by etching is almost vertical, and the taper angle is at least 70 ° or more. As is clear from FIG.
A step is formed at the edge of the gate electrode (11).

Generally, in a reverse stagger type TFT in which a gate electrode is formed in a lower layer and a source / drain electrode is formed in an upper layer with a-Si sandwiched therebetween, a step of the gate wiring causes disconnection of the upper layer and deterioration of coverage. . If the upper layer is made thicker as a measure against this, there is a problem that the throughput is reduced. An object of the present invention is to provide a Cr taper etching technique by improving a photolithography process so that a gate electrode has a tapered cross section.

[0009]

In order to achieve the above-mentioned object, the present invention is, firstly, a mixed solution of cerium ammonium nitrate as an etchant, nitric acid and water, in which the concentration of nitric acid is 30 wt% or more. Is used. Second
In addition, the prebake temperature is set to 70 ° C. or lower.

Third, the temperature of the etchant during etching is set to room temperature or higher.

[0011]

In photolithography in LSI, the resolution and the high aspect ratio are important, whereas in LCD, the line width is 10 times or more for a film thickness of 1 μm or less, so that it is more equal than anisotropy. Etching with a low taper angle is desired in order to prevent a decrease in the step coverage in the step and the step. Conventionally, in wet etching, etching with a high taper angle has been performed by improving the adhesion between the resist film and the film to be etched, but in the present invention, the direction of decreasing the adhesion between the resist film and the film to be etched By adjusting various etching conditions, the side etch can be increased and the taper angle can be reduced.

[0012]

EXAMPLES First, Tables 1 to 4 show the results of measuring the taper angles under various conditions using the resists A and B for the etching of Cr. The adhesive force of the resist A is stronger than that of B, and the etchant X in the table is a mixed solution of cerium ammonium nitrate, nitric acid and water with a nitric acid concentration of 30 wt%, and the etchant Y is nitric acid. It is a mixed solution of cerium ammonium, perchloric acid and water. The etchant temperature RT is room temperature, that is, about 20 °.

[0013]

[Table 1]

[0014]

[Table 2]

[0015]

[Table 3]

[0016]

[Table 4]

From Table 1, when the pre-bake temperature is 70 ° C. and the etchant temperature is 35 ° C., the taper angle when Y is used as the etchant is 48 °, while the taper when X is used as the etchant. The angle is 4 °. Also,
When the pre-bake temperature is 70 ° C. and the etchant temperature is RT, it is 74 ° when the etchant is Y.
It is 30 ° for etchant X. Table 4 from the same viewpoint
Therefore, comparing the cases where Y and X are used as etchants,
The taper angles are 5 ° for 14 ° and 13 ° for 71 °, respectively. From this, the etchant is Y
It can be seen that the taper angle becomes smaller when X is used, that is, when nitric acid is used rather than perchloric acid.

In Table 1, the prebaking temperature is 70 ° C.,
When post-baking is not performed, the etchant is X, the etchant temperature is 35 ° C., the taper angle is 4 °, and the pre-bake temperature is 90 ° C. and other conditions are the same.
° smaller than Similarly, in Table 4, the taper angle at the prebaking temperature of 70 ° C. is 5 °, which is smaller than the taper angle of 58 ° at the prebaking temperature of 90 ° C. From this, it is understood that the taper angle becomes smaller as the prebake temperature becomes lower.

Further, in Table 1, the prebaking temperature is 70 ° C.,
When the etchant is X, the taper angles at the etchant temperature of 35 ° C. and RT are 4 ° and 30 °, respectively, the prebake temperature is 70 ° C., and the etchant is Y.
In the case of, the taper angles at the etchant temperature of 35 ° C. and RT are 48 ° and 74 °, respectively. Similarly in Table 4, when the pre-bake temperature is 70 ° C. and the etchant is X, the taper angles are 5 ° and 13 ° when the etchant temperature is 35 ° C. and RT, respectively, and the pre-bake temperature is 70 ° C. and the etchant is In the case of Y, when the etchant temperature is 35 ° C. and RT, the taper angle is 14 each.
And 71 °. From this, the etchant temperature is R
It can be seen that the taper angle becomes smaller when the etchant temperature is higher than T by 35 ° C., that is, higher.

Further, in Table 1, the prebaking temperature is 90 ° C.,
When the etchant is X and the etchant temperature is 35 ° C,
The taper angles of post-baking at 120 ° C. and those not post-baking are 59 ° and 66 °, respectively, which are not so different. Similarly in Table 4, the taper angles were 54 ° and 58 °, respectively. From this, it can be seen that the presence or absence of post bake is irrelevant to the taper angle.

Further, comparing Tables 1 and 4, under the same conditions, the taper angle in Table 4 is smaller overall, and the resist B, that is, the resist having a weaker adhesion than the resist A, is used. It can be seen that the corner becomes smaller.
Further, in Table 1, Table 2 and Table 3, the pre-baking temperature is 90.
℃, post bake temperature is 120 ℃, etchant is X,
When the film thickness of the resist A is different under the same etchant temperature of 35 ° C., there is not much difference in taper angle.

From the above results, in order to decrease the taper angle, firstly, a nitric acid-based etchant is used, secondly, the prebaking temperature is lowered, and thirdly, the etchant temperature is raised. I understand that it is good. The presence or absence of post-baking and the film thickness of the resist film are irrelevant to the taper angle, and the taper angle becomes smaller when a resist having a weak adhesion (A> B) is used.

The taper angle of the cross section of the film to be etched can be controlled by adjusting the etching conditions based on this result. For the formation of the Cr gate, a pre-bake temperature is set to 70 ° C. as a photolithography condition, a mixed solution of cerium ammonium nitrate, nitric acid and water having a nitric acid concentration of 30 wt% is used as an etchant. An example will be described by setting the temperature to 35 ° C.

FIG. 1 shows a sectional structure of the TFT manufactured as described above. C is formed on the transparent substrate (10) such as glass.
r patterned gate electrode (11) is provided with, on the gate electrode (11) across the gate insulating film such as _{SiN X (12), a-} Si (13), an etching stopper (14), N ⁺ a-Si (15) is laminated in an island shape, and further source / drain electrodes (16, 17) such as Al are provided on the N ⁺ a-Si (15). The source electrode (16) is an ITO display electrode (1
8) is connected. As is clear from the figure, the gate electrode (11) has a tapered edge portion.
Although it is inaccurate for the convenience of illustration, the film thickness is actually 150.
The line width is about 10 μm and the taper angle is 10 ° C. or less with respect to about 0 Å.

Next, a method of forming the gate electrode (11) will be described with reference to FIGS. First, the transparent substrate (1
0) on top of Cr (19) by sputtering etc.
The layers are laminated to a thickness of about 500Å, and a resist film (20) is coated on the Cr (19) by spin coating to a thickness of about 1.5 μm (see FIG. 2 above). Next, after prebaking at 70 ° C., the resist film (20) is exposed by irradiating ultraviolet rays or deep ultraviolet rays through a mask having a predetermined pattern, and is formed into a gate wiring pattern by development (above). , See FIG. 3). Then, this substrate was placed in an etchant containing a mixture of cerium ammonium nitrate, nitric acid and water and having a nitric acid concentration of 30 wt% and a temperature of 35 ° C.
The resist film (20) is used as a mask to carry out etching to pattern Cr (19) on the gate wiring (see FIG. 4 above). In the present invention, since the adhesiveness of the resist film (20) is adjusted as described above, the etching of Cr (19) has a large number of side etches as shown in the figure, and the taper angle is 10 ° or less. We were able to. Finally, the unnecessary resist film (20) is removed by a peeling agent or ashing to complete the gate electrode (11) (see FIG. 5).
Since the post bake is irrelevant to the taper angle, it is omitted for cost reduction.

[0026]

As is apparent from the above description, the etching conditions are adjusted to control the adhesiveness between the resist film and the film to be reduced, thereby making the cross section of the film to be etched into a tapered shape. We were able to. As a result, the coverage of the upper layer is improved to prevent disconnection, and the film thickness of the upper layer can be reduced to improve the throughput.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a TFT according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a TFT according to an example of the present invention.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a TFT according to an example of the present invention.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a TFT according to an example of the present invention.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a TFT according to an example of the present invention.

FIG. 6 is a cross-sectional view of a conventional TFT.

[Explanation of symbols]

10 transparent substrate 11 gate electrode 12 gate insulating film 13 a-Si 14 etching stopper 15 N ⁺ a-Si 16 source electrode 17 drain electrode 18 display electrode 19 Cr 20 resist film

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[Procedure amendment]

[Submission date] December 27, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Claims (4)

[Claims] 1. A gate electrode formed on a substrate, a non-single-crystal semiconductor layer formed on the gate electrode with an insulating film interposed therebetween, and source and drain electrodes covering both ends of the non-single-crystal semiconductor layer. In the method of manufacturing a thin film transistor according to the above, the gate electrode is formed by a photolithography process including a step of forming a Cr film and an etching step of the Cr using a mixed liquid containing cerium ammonium nitrate, nitric acid and water as an etchant. A method of manufacturing a thin film transistor, which is characterized by being formed. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the etchant has a nitric acid concentration of 30 wt% or more. 3. A gate electrode provided on a substrate, a non-single crystal semiconductor layer provided on the gate electrode with an insulating film interposed therebetween, and source and drain electrodes covering both ends of the non-single crystal semiconductor layer. The method of manufacturing a thin film transistor according to claim 1, wherein the gate electrode is formed by a photolithography process including a step of depositing Cr and a prebaking step at 70 ° C. or less. 4. A gate electrode provided on a substrate, a non-single crystal semiconductor layer provided on the gate electrode with an insulating film interposed therebetween, and source and drain electrodes covering both ends of the non-single crystal semiconductor layer. The method of manufacturing a thin film transistor according to claim 1, wherein the gate electrode is formed by a photolithography process including a step of depositing Cr and an etching step in which the temperature of the Cr etchant is room temperature or higher. .