USRE43471E1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

Info

Publication number
USRE43471E1
USRE43471E1 US10/960,898 US96089804A USRE43471E US RE43471 E1 USRE43471 E1 US RE43471E1 US 96089804 A US96089804 A US 96089804A US RE43471 E USRE43471 E US RE43471E
Authority
US
United States
Prior art keywords
film
exposure
conductive film
photo resist
bake
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/960,898
Inventor
Ichiro Uehara
Kazuhiro Toshima
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US10/960,898 priority Critical patent/USRE43471E1/en
Application granted granted Critical
Publication of USRE43471E1 publication Critical patent/USRE43471E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to a semiconductor device having a circuit formed of thin film transistors (thereafter, referred to as TFTs) and a method of manufacturing the same.
  • the semiconductor device includes, for example, an electro-optical device such as a liquid crystal display formed of TFTs.
  • the present invention relates to a method of manufacturing a semiconductor device having inverted staggered type TFTs with a bottom gate structure, and more particularly to a photolithography for patterning, the semiconductor device.
  • an active matrix liquid crystal display technology using TFTs is of great interest. Since an active matrix display is provided with a TFT switch on each pixel, a liquid crystal orientation state of TN (i.e., twisted nematic) mode is available, and it is advantageous in terms of response speed, viewing angle and contrast, compared with a passive matrix display, it is mainly used in the current liquid crystal display.
  • TN i.e., twisted nematic
  • an inverted stagger type TFT which has a bottom gate structure having a channel forming region formed of an amorphous silicon film conventionally capable of being produced on a large area substrate with a low temperature process at 300° C. or less.
  • the above-mentioned inverted stagger type TFT is basically advantageous of low cost, since a low cost glass substrate and the low temperature process at 300° C. or less are employed. However, since low cost is further required, the improvement of the productivity for attaining the low cost has been considered. Since shortening the process is most effective for improving the productivity, shortening the process has been considered in the industry. Therefore, reducing a photolithography step which is a pattering step, that is, reducing the number of photo masks is considered for shortening the process.
  • DNQ diazo naphthoquinone
  • the resist shape of a fine pattern (about 0.3-3 ⁇ m) is a good rectangular pattern, but in a larger pattern (about 10 ⁇ m or more), deformation in the pattern with variation in taper angle occurs on a side wall of the resist shape, and it is observed that the taper angle is reduced (see FIG. 1 ).
  • the phenomenon occurs under a process condition, i.e., pre-bake temperature (90° C. for one minute), followed by PEB (post exposure bake) temperature (110° C. for three minutes) and post-bake temperature (120° C. for four minutes), in which the post-bake temperature after development is higher than the PEB temperature, the phenomenon is considered to be caused due to evacuation of residual solvent from the resist pattern at the post-bake. Also, in a photolithography step without PEB process, it is observed that deformation in the resist pattern due to volume contraction from the resist pattern at the post-bake occurs in the case of large difference between the pre-bake temperature and the post-bake temperature.
  • DNQ diazo naphthoquinone
  • pattern deformation with variation of side wall taper angle of large area photo resist pattern occurred as shown in FIG. 1 in a photolithography step with diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist. Since this pattern deformation dose not occur in fine pattern (about 3 82 m or less) formed simultaneously, it is observed that the pattern deformation is dependent on the dimension of the photo resist pattern, i.e., the area of the photo resist pattern (see FIG. 1 ).
  • DNQ diazo naphthoquinone
  • a reduction projection exposure apparatus is used as an exposure apparatus, in which a single wavelength (specifically, i-ray of an extra high-pressure mercury-vapor lamp) is used for accounting for chromatic aberration. Therefore, PEB process is generally applied between exposure and development because of adverse effect by standing wave due to a single wavelength of the exposed light. This company uses the PEB process in performing a photolithography step using the reduction projection exposure apparatus.
  • the photo resist pattern deformation with variation of side wall taper angle occurs in a photolithography step applying the PEB process between exposure and development, i.e., in a sequence of photo processes consisting of a photo resist coating ⁇ pre-bake (90° C. for one minute) ⁇ exposure (using the reduction projection exposure apparatus)-PEB (110° C. for three minutes) ⁇ development, and post-bake (120° C. for four minutes).
  • a photo resist coating ⁇ pre-bake (90° C. for one minute) ⁇ exposure (using the reduction projection exposure apparatus)-PEB (110° C. for three minutes) ⁇ development, and post-bake (120° C. for four minutes).
  • the photo resist pattern deformation occurs after the post-bake process (120° C. for four minutes) at glass transition temperature (about 150° C.) or less, which can be a softening point of the photo resist, it is apparent that the photo resist pattern deformation dose not occur due to thermal softening of the photo resist. Therefore, factors of the photo resist pattern de
  • the influence on the dimension of the large area resist pattern edge was measured as changing PEB temperature from 110° C. to 150° C.
  • the dimension of the large area resist pattern edge was then measured by means of a measurement SEM (see FIGS. 2A and 2B ).
  • FIG. 2A is a plot of PEB temperature (horizontal axis) and pattern edge width ( ⁇ m).
  • the large area pattern is a part of a concave LSA mark and the periphery of the mark is a resist region.
  • the exposure time was adjusted so that the line length of 0.8 ⁇ m L/S becomes substantially 0.8 ⁇ m ever, PEB condition. Focus is 0.0 ⁇ m. Referring to FIGS.
  • the dimension of the large area resist pattern edge is Gradually decreased in response to the rise of the PEB temperature, and it was observed that it is tended to be stable at the higher PEB temperature than that close to post-bake temperature (120° C.), i.e., the pattern deformation with variation in the side wall taper angle of the large area resist pattern due to volume contraction phenomenon is reduced in a region at the higher temperature region than that close to post-bake temperature (120° C.).
  • the PEB process is a step introduced to reduce interference fringes on the post-development resist pattern side wall occurring at a single wavelength exposure by the reduction projection exposure apparatus.
  • the PEB process may not be necessarily introduced because interference fringes on the post-development resist pattern side wall basically do not occur in exposing by means of an equivalent projection exposure apparatus capable of multi-wavelength exposure (for example, g-ray, h-ray and i-ray of an extra high-pressure mercury-vapor lamp).
  • a photo process without PEB process i.e., a photo process consisting of a sequence of photo resist coating ⁇ pre-bake ⁇ exposure ⁇ development ⁇ post-bake is generally used.
  • the post-bake temperature normally, about 110-140° C.
  • the pre-bake temperature normally, about 90-100° C.
  • FIGS. 3A-3C are SEMI photographs of the resist pattern cross-section, at pre-bake temperature 90° C. ( FIG. 3A ), 110° C. ( FIG. 3B ) and 130° C. ( FIG. 3C ), respectively, wherein exposure is performed by means of an equivalent projection exposure apparatus using multi-wavelengths, and development and post-bake (140° C.) are directly performed without the PEB process.
  • pre-bake temperature 90° C.
  • FIG. 3B 110° C.
  • 130° C. FIG. 3C
  • the difference between the pre-bake temperature and the post-bake temperature must be 10° C. or less.
  • the large area photo resist pattern (10 ⁇ m or more) is not measured. If the large area photo resist pattern is measured, appropriate range of the pre-bake temperature would be equal to or greater than that of the post-bake temperature similarly to a measurement with the PEB process because of severer condition of the measurement in terms of deformation phenomenon occurred due to volume contraction by evacuation of solvent at the post-bake. However, if the appropriate range of the pre-bake temperature is equal to or greater than that of the post-bake temperature, it is possible that exposure property such as sensitivity is adversely affected as pre-bake temperature rises. Preferably, the post-bake temperature is not excessively reduced for adherence of the photo resist pattern to the underlying substrate. From this point, the pre-bake temperature was measured using normal photo resist pattern (3 ⁇ m line pattern) rather than the large area photo resist pattern, and the bake condition was restricted so that pre-bake temperature is within ⁇ 10° C. relative to the post-bake temperature.
  • a solution which can solve a problem of the area dependence of the photo resist pattern side wall taper angle inducing the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake.
  • the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake is solved by restricting the pre-bake temperature within ⁇ 10° C. relative to the post-bake temperature.
  • the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake is solved by restricting the PEB temperature so as to be equal to or higher than the post-bake temperature.
  • a method of manufacturing a semiconductor device having inverted stagger type TFTs reduction of patterning steps is considered to reduce the overall process steps, and the present invention relates to a method of manufacturing the semiconductor device using three photo masks.
  • the method of manufacturing the semiconductor device means solution for solving the area dependence of photo resist pattern side wall taper angle which is a problem of a photolithography step is described below.
  • a method of manufacturing a semiconductor device in accordance with the present invention includes a first step of forming a first conductive film on an insulating surface, a second step of forming a resist pattern on the first conductive film, a third step of dry-etching the first conductive film to form a first pattern, a fourth step of forming a first insulating film on the first pattern, a fifth step of forming a first semiconductor film on the first insulating film, a sixth step of forming a one conductivity type second semiconductor film on the first semiconductor film, a seventh step of forming a second conductive film on the one conductivity type second semiconductor film, an eighth step of forming a resist pattern on the second conductive film, a ninth step of dry-etching the first semiconductor film, the one conductivity type second semiconductor film, and the second conductive film to form a second pattern, a tenth step of forming a third conductive film on the second pattern, an eleventh step of forming a resist pattern on the third conductive film, and a
  • the third pattern formed by the twelfth step is patterned by etching not only the third conductive film but also the second pattern (formed by the ninth step).
  • a method of manufacturing a semiconductor device in accordance with the present invention comprises a first step of forming a first conductive film on an insulating film, a second step of forming a resist pattern on the first conductive film, a third step of dry-etching the first conductive film to form a gate electrode, a fourth step of forming a first insulating film on the gate electrode, a fifth step of forming a first semiconductor film on the first insulating film, a sixth step of forming a one conductivity type second semiconductor film on the first semiconductor film, a seventh step of forming a second conductive film on the one conductivity type second semiconductor film, an eighth step of forming a resist pattern on the second conductive film, a ninth step of dry-etching the first semiconductor film, the one conductivity type second semiconductor film, and the second conductive film to form a source wiring and an active layer, a tenth step of forming a third conductive film on the source wiring and the active layer, an eleventh step of forming a resist pattern
  • the first insulating film formed by the fourth step is a gate insulating film.
  • the source wiring and the active layer formed by the ninth step are formed of a laminated pattern consisting of the first semiconductor film and the one conductivity type second semiconductor film. According to a pattern forming by the twelfth step, while the pixel electrode is formed of the third conductive film, in addition, a channel region is formed of the first semiconductor film, a source region and a drain region are formed of the one conductivity type second semiconductor film, and a source electrode and a drain electrode are formed of the second conductive film.
  • each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, developing, and post-baking, characterized in that difference between the pre-bake temperature and the post-bake temperature is within ⁇ 10° C.
  • each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, developing, and post-baking, characterized in that the pre-bake temperature is within ⁇ 10° C. relative to the post-bake temperature.
  • each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, post-exposure baking, developing, and post-baking, characterized in that difference between the post-exposure bake temperature and the post-bake temperature is within ⁇ 10° C.
  • FIG. 1 An SEM photograph illustrating deformation of a resist shape in a conventional large area resist pattern.
  • FIG. 2A A graph illustrating PEB temperature dependence of the dimension of a large area resist pattern edge in accordance with the present invention.
  • FIG. 2B An SEM photograph specifically illustrating measurement position shown in FIG. 2A .
  • FIGS. 3A-3C SEM photographs of the resist pattern shapes in an equivalent projection exposure apparatus (MPA) in accordance with the present invention.
  • FIGS. 4A-4D Cross-sectional views illustrating the structure of an inverted stagger type TFT and a method of manufacturing the same in accordance with the present invention.
  • FIGS. 5A and 5B Cross-sectional views illustrating the structure of an inverted stagger type TFT and a method of manufacturing the same in accordance with the present invention.
  • FIG. 6 A top view illustrating the structure of a pixel region in an active matrix liquid crystal display device having the inverted stagger type TFTs.
  • the present invention relates to a structure of an inverted stagger type TFThaving a bottom gate structure and a method of manufacturing the same, characterized in that, by restricting a bake condition between a pre-bake temperature or PEB temperature and a post-bake temperature in a photolithographystep, taper angles of various dimensions of resist patterns are accurately controlled, as a result, accurately controlling shapes of various dimensions of etching patterns.
  • Specific embodiment mode of the structure of the inverted stagger type TFT and the method of manufacturing the same in accordance with the present invention are described below with reference to FIGS. 4A-4D , FIGS. 5A-5B and FIG. 6 .
  • FIGS. 4A-4D and FIGS. 5A-5B are cross-sectional views illustrating a manufacturing steps of an active matrix liquid crystal display device
  • FIG. 6 is a top view illustrating configuration of a pixel region in the active matrix liquid crystal display device.
  • the cross-sectional views of FIGS. 4A-4D and FIGS. 5A-5B are taken along a line A-A′ and a line B-B′ in FIG. 6 , respectively.
  • a terminal portion, a pixel TFT portion and a capacitor portion are shown from the left side.
  • a first conductive film (not shown) used as a (gate electrode material is deposited on the overall surface of an insulating transparent substrate 101 such as a glass substrate by sputtering or the like (a first step).
  • the first conductive film (not shown) is used as a material for forming a gate wiring (including a gate electrode), a capacitor wiring (including a capacitor electrode) and the others, and preferably made from a low-resistance metal, such as Al (aluminum).
  • a low-resistance metal such as Al (aluminum).
  • Al aluminum alone has problems such as less heat-resistance and susceptibility to corrosion
  • the first conductive film is generally made of a laminate film consisting of a low-resistance metal and a heat-resistant material.
  • the laminated film includes a two-layer structure of a low-resistance material (e.g., Al) and a heat-resistant material, and a three-layer structure in which a low-resistance material is sandwiched between two heat-resistant material, i.e., a three-layer structure consisting of a heat-resistant material (e.g., Al)/ a low resistance material/a heat-resistant material (see FIG. 4A ).
  • a low-resistance material e.g., Al
  • a heat-resistant material e.g., Al
  • a low resistance material is a material including Al as its principal component added with Sc (scandium), Ti (titanium), Cu (copper), Si (silicon) or the like at about 0.01-5%.
  • a heat-resistant material is a high-melting metal such as Ti (titanium), Ta (tantalum), W (tungsten), Mo (molybdenum), Cr (chromium), or the like; a metal silicide which is a compound of the high-melting metal and silicon; or a metal nitride which is a compound of the high-melting metal and nitrogen.
  • the first conductive film (not shown) consisting of Ti (50 ⁇ m thick)/Al (200 nm thick)/Ti (50 nm thick) was deposited by sputtering (see FIG. 4A ).
  • a resist mask is formed by a first photolithography step (a second step)
  • the bake condition is restricted so that PEB temperature is equal to or higher than the post-bake temperature
  • the bake condition is restricted so that the pre-bake temperature is equal to the post-bake temperature or difference between the pre-bake temperature and the post-bake temperature is within about 10° C.
  • a resist mask (not shown) is formed having a taper angle accurately controlled (see FIG. 4A ).
  • the photolithography step without PEB process is applied and the bake condition is restricted so that the pre-bake temperature is within ⁇ 10° C. relative to the post-bake temperature. Therefore, the problem of the area dependency of the photo resist pattern side wall taper angle is solved which is deformation phenomenon due to the volume contraction occurred by evacuation of solvent at the post-bake.
  • wiring and electrodes are formed by etching out and then removing the resist mask (not shown) (a third step). In this case, the etching is performed so that a forward taper portion is formed at the end of the grate wiring 102 (see FIG. 4A ).
  • a gate insulating film 105 a which is formed of a silicon oxide film, a silicon oxide nitride film or a silicon nitride film having a thickness of 50-200 nm is deposited by plasma CVD or sputtering (a fourth step).
  • a first amorphous semiconductor film 106 having a thickness of 50-200 nm is deposited on the gate insulating film 105 a by plasma CVD or sputtering (a fifth step).
  • the first amorphous semiconductor film 106 formed of an amorphous silicon film and having the thickness of 100 nm was deposited by sputtering (see FIG. 4A ).
  • a second conductive film 108 made from metal material is deposited by sputtering (a seventh step).
  • Any metal material having ohmic contact characteristics to the underlying second amorphous semiconductor film 107 is non-limited used as material of the second conductive film 108 .
  • used may be a single-layer film formed of a single element or any alloys made from a plurality of elements, such as Al (aluminum), Cr (chromium), Ta (tantalum), and Ti (titanium), and a laminated layer consisting of the single layer film.
  • the second conductive film 108 having a three-layer structure consisting of Ti (100 nm thick),/Al (350 nm thick)/Ti (100 nm thick) was deposited by sputtering (see FIG. 4A ).
  • the gate insulating film 105 a having 50-200 nm thickness, the first amorphous semiconductor film 106 having 50-200 nm thickness, the second amorphous semiconductor film 107 having 20-80 nm thickness containing one conductivity type (n-type or p-type) impurity element, and the second conductive film 108 made from metal material are sequentially deposited.
  • any metal material having ohmic contact characteristics to the second amorphous semiconductor film 107 is non-limitedly used as material of the second conductive film 108 (see FIG. 4A ).
  • a resist mask 109 with a taper angle being accurately controlled is formed by a second photolithography step (an eighth step), and then a wiring 112 (in the subsequent step, becoming a source wiring and a drain electrode) is formed by etching (a ninth step).
  • the second conductive film 108 , the second amorphous semiconductor film 107 containing an impurity element imparting n-type, and the first amorphous semiconductor film 106 are sequentially etched by using the resist mask 109 as a mask, and in a pixel TFT portion, the wiring 112 consisting of the second conductive film 108 , the second amorphous semiconductor film 111 containing the impurity element imparting n-type, and the first amorphous semiconductor film 110 are sequentially formed (see FIG. 4B ).
  • the second conductive film 108 having a three-layer structure consisting of Ti (100 nm thick)/Al (350 nm thick)/Ti (100 nm thick) is dry-etched by using the mixed gas of SiCl 4 , Cl 2 , and BCl 3 as dry etching gas, and the second amorphous semiconductor film 107 and the first amorphous semiconductor film 106 are dry-etched by using the mixed gas of CF 4 and O 2 .
  • the gate insulating film 105 a in the capacitor portion and the terminal portion remains without being dry-etched.
  • the dry etching step since a laminated pattern consisting of the wiring 112 for forming a source and a drain electrodes, the second amorphous semiconductor film 111 for forming a source and a drain regions, and the first amorphous semiconductor film 110 for forming a channel region is dry-etched by using the photo resist mask 109 with little variation of the side wall taper angle as a mask, a stable etching shape can be obtained.
  • a resist mask (not shown) is formed using a shadow mask, and an insulating film 105 b is formed by selectively removing a portion of the insulating film 105 a, which covers a pad portion of the terminal portion. Thereafter, the resist mask (not shown) is removed (see FIG. 4C ).
  • a third conductive film 113 formed of a transparent conductive film is deposited overall thereon (a tenth step).
  • Material of the third conductive film 113 includes indium oxide (In 2 O 3 ), indium oxide-tin oxide alloy (In 2 O 3 —SnO 2 : hereafter referred to as ITO) and the others (see FIG. 4D ).
  • the third conductive film 113 made of ITO film having a thickness of 100 nm was deposited by sputtering.
  • photo resist masks 114 a- 114 c with taper angle being accurately controlled are formed by a third photolithography step (an eleventh step) (see FIG. 5A ).
  • the photolithography without PEB process is applied as well as in the second step and the eighth step, and the bake condition is restricted so that the pre-bake temperature is within ⁇ 10° C. relative to the post-bake temperature. Therefore, the problem of the area dependency of the photo resist pattern side wall taper angle is solved which is deformation phenomenon due to the volume contraction occurred by evacuation of solvent at the post-bake.
  • a first amorphous semiconductor film 115 ; a source region 116 and a drain region 117 ; a source electrode 118 and a drain electrode 119 ; and a pixel electrode 120 are formed by etching.
  • the third conductive film 113 is patterned, while an opening is formed by etching out a portion of the wiring 112 , a portion of the second amorphous semiconductor film 111 containing an impurity element imparting n-type, and a portion of the first amorphous semiconductor film 110 .
  • the bottom of the opening reaches the first amorphous semiconductor film 110 , so that the first amorphous semiconductor film 115 having a concave portion is formed.
  • the opening divides the wiring 112 into the source electrode (source wiring) 118 and the drain electrode 119 , and the second amorphous semiconductor film 111 containing an impurity element imparting n-type is separated into the source region 116 and the drain region 117 (see FIG. 5A ).
  • wet-etching is used to etch the third conductive film 113 .
  • an organic acid about 3.4% solution: ITO-04 etchant
  • a mixture of nitric acid and hydrochloric acid, and ferric chloride solution are used as etchant.
  • the third conductive film (ITO film) 113 is selectively wet-etched by using the organic acid (about 3.4% solution: ITO-04N etchant).
  • dry-etching is applied for the laminated film consisting of the wiring 112 / the second amorphous semiconductor film 111 / the first amorphous semiconductor film 110 .
  • the wiring 112 for forming(y the source and, the drain electrodes having a three-layer structure consisting of Ti (100 nm thick)/Al (350 nm thick)/Ti (100 nm thick) was dry-etched using chlorine-based mixed gas (SiCl 4 , Cl 2 , and BCl 3 ), while the second amorphous semiconductor film 111 for forming the source and drain regions consisting of an amorphous silicon film having 50 nm thickness containing P (phosphorus) element, and the first amorphous semiconductor film 110 for forming a channel region consisting of an amorphous silicon film having 100 nm thickness were dry-etched using fluorine-based gas (CF 4 and O 2 .).
  • fluorine-based gas CF 4 and O 2 .
  • the etching shapes of the source electrode 118 , the drain electrode 119 , the source region 116 , the drain region 117 and the others formed by the dry-etching step are stable because of little variation of the photo resist pattern side wall taper angle.
  • a third conductive film 121 in contact with the source electrode (source wiring) 118 plays a role to cover the source electrode (source wiring) 118 and prevent electro statics from occurring by rubbing in the subsequent manufacturing steps.
  • a storage capacitor 202 is formed with the capacitor wiring 103 and the pixel electrode 120using the insulating film 105 b in the capacitor portion as dielectric.
  • a third conductive film remains which is formed of a transparent conductive film covered with a resist mask 114 c and formed on the terminal portion.
  • the resist masks 114 a- 114 c are removed (see FIG. 5B ).
  • FIG. 6 A plane configuration of a pixel region in the active matrix liquid crystal display device formed on the basis of the above manufacturing steps is shown in FIG. 6 .
  • the above manufacturing steps of the active matrix liquid crystal display device ( FIGS. 4A-4D and FIGS. 5A-5B ) is shown in cross-sectional views taken along the line of A-A′ (corresponding to the pixel TFT portion) and B-B′ (corresponding to the capacitor portion) in FIG. 6 .
  • a plurality of gate wirings 102 positioned in parallel with each other and a plurality of source electrodes (source wirings) 118 each orthogonal to each of the gate wirings 102 are formed, and the pixel electrode 120 is provided in a region surrounded with the gate wiring 102 and the source electrode (source wiring) 118 .
  • the third conductive film 121 which is a transparent electrode wiring formed simultaneously with the pixel electrode 120 , is provided so as to overlap the source electrode (source wiring) 118 , and plays a role to prevent electro statics from occurring by rubbing in the subsequent step. In the embodiment, while the third conductive film 121 overlaps the source electrode (source wiring,) 118 , the third conductive film 121 may not be formed.
  • the capacitor wiring 103 is provided adjacent to and in parallel with the gate wiring 102 .
  • the capacitor wiring (including the capacitor electrode) 103 is provided in each of all pixels, the storage capacitor 202 is formed using a gate insulating film 104 b between the capacitor wiring 103 and the pixel electrode 120 as dielectric.
  • an inverted stagger type n-channel TFT 201 is formed which functions as a switching element (see FIG. 6 ).
  • a photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist without PEB process is applied, and the bake condition is restricted so that the pre-bake temperature is within ⁇ 10° C. relative to the post-bake temperature. Therefore, an excellent photo resist pattern is formed without deformation phenomenon due to volume contraction occurred by evacuation of solvent at the post-bake. Since no deformation phenomenon occurs due to volume contraction, it is characterized in that the photo resist pattern has no problem of the area dependency of the photo resist pattern side wall taper angle.
  • DNQ diazo naphthoquinone
  • the inverted stagger type TFT having the bottom gate structure of the present invention is manufactured using photo masks three times, and thus, it is characterized in that low-cost and improvement of yield are achieved.
  • the bake condition is restricted so that the PEB temperature is equal to or higher than the post-bake temperature, while without the PEB process, the bake condition is restricted so that the pre-bake temperature is equal to or within ⁇ 10° C. relative to the post-bake temperature, so that the resist pattern can be formed with the taper angle being accurately controlled, thereby obtaining the etching pattern accurately controlled.
  • the bake condition is restricted so that the pre-bake temperature is within ⁇ 10° C. relative to the post-bake temperature, while for a photolithography step with the PEB process, the bake condition is restricted so that the PEB temperature is equal to or higher than the post-bake temperature.
  • the photolithography step which is a manufacturing process of the semiconductor device having inverted stagger type TFTs
  • a stable etching shape independent on the pattern area can be achieved in the subsequent dry-etching step.
  • variation of the photo resist pattern side wall taper angle might sensitively influence the dry-etching shape. Accordingly, stabilization of the photo resist pattern side wall taper angle may advantageously affect stabilization of the etching shape.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

In a patterning process of a semiconductor device having inverted stagger type TFTs, a normal photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist is applied, and a problem of the area dependency of the photo resist pattern side wall taper angle may occur. The problem is critical for the reason of influence on variation of an etching shape in a dry-etching step. The present invention has an object to solve the above problem. In a photolithography step, which is patterning step of a semiconductor device having inverted stagger type TFTs, by adjusting a pre-bake temperature or a PEB (post-exposure-bake) temperature, and positively performing evacuation of solvent in a state of a photo resist film, the volume contraction by evacuation of solvent at the post-bake is reduced, and the problem of the area dependency of the photo resist pattern side wall taper angle is solved, which is deformation due to the volume contraction.

Description

TECHNICAL FIELD TO WHICH THE INVENTION BELONGS
The present invention relates to a semiconductor device having a circuit formed of thin film transistors (thereafter, referred to as TFTs) and a method of manufacturing the same. The semiconductor device includes, for example, an electro-optical device such as a liquid crystal display formed of TFTs.
More specifically, the present invention relates to a method of manufacturing a semiconductor device having inverted staggered type TFTs with a bottom gate structure, and more particularly to a photolithography for patterning, the semiconductor device.
PRIOR ART
In recent years, an active matrix liquid crystal display technology using TFTs is of great interest. Since an active matrix display is provided with a TFT switch on each pixel, a liquid crystal orientation state of TN (i.e., twisted nematic) mode is available, and it is advantageous in terms of response speed, viewing angle and contrast, compared with a passive matrix display, it is mainly used in the current liquid crystal display.
In the electro-optical device including such a liquid crystal display with the active matrix display, high definition, high aperture ratio and high reliability, along with enlarging the area of a screen have been greatly required, while low cost along with improvement of the productivity has been further greatly required. In particular, in response to the low cost requirement, an inverted stagger type TFT is widely adopted, which has a bottom gate structure having a channel forming region formed of an amorphous silicon film conventionally capable of being produced on a large area substrate with a low temperature process at 300° C. or less.
The above-mentioned inverted stagger type TFT is basically advantageous of low cost, since a low cost glass substrate and the low temperature process at 300° C. or less are employed. However, since low cost is further required, the improvement of the productivity for attaining the low cost has been considered. Since shortening the process is most effective for improving the productivity, shortening the process has been considered in the industry. Therefore, reducing a photolithography step which is a pattering step, that is, reducing the number of photo masks is considered for shortening the process.
A normal photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist, and an etchings step such as dry etching and wet etching are applied in the patterning step to he reduced.
In the normal photolithography step consisting of a combination of the diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist and a reduction projection exposure apparatus (also referred to as a stepper) which is a single wavelength (g-ray and i-ray of high-pressure mercury-vapor lamp) exposure apparatus, it has been apparent that fluctuation in taper angle of the resist pattern occurs due to variation in size of the resist pattern. Namely, the resist shape of a fine pattern (about 0.3-3 μm) is a good rectangular pattern, but in a larger pattern (about 10 μm or more), deformation in the pattern with variation in taper angle occurs on a side wall of the resist shape, and it is observed that the taper angle is reduced (see FIG. 1).
Since the above phenomenon occurs under a process condition, i.e., pre-bake temperature (90° C. for one minute), followed by PEB (post exposure bake) temperature (110° C. for three minutes) and post-bake temperature (120° C. for four minutes), in which the post-bake temperature after development is higher than the PEB temperature, the phenomenon is considered to be caused due to evacuation of residual solvent from the resist pattern at the post-bake. Also, in a photolithography step without PEB process, it is observed that deformation in the resist pattern due to volume contraction from the resist pattern at the post-bake occurs in the case of large difference between the pre-bake temperature and the post-bake temperature.
In producing the inverted stagger type TFT with a bottom gate structure, while the photolithography step without PEG process is generally adopted, it is not advantageous that as described above, deformation in the resist pattern due to volume contraction at the post-bake occurs. Since various dimensions of circuit patterns exist in a liquid crystal display, deformation in the resist pattern with variation in taper angle depending on variation in the area of the resist pattern influences the etched shape, and thus is a critical problem.
Also, for low cost and enhancement of yield, reduction of the photolithography step is required. In this case, since a plurality of thin film layers, are patterned simultaneously using the resist pattern as a mask, variation of the resist pattern side wall taper angle is a critical problem because it is observed that it also greatly influences the etched shape.
In light of the above problem, in a photolithography step which is a patterning step for a semiconductor device having an inverted stagger type TFT, a phenomenon in which the greater the dimension of the photo resist pattern is, the smaller the taper angle on the side wall is, i.e., the area dependence of the photo resist pattern side wall taper angle is worried. The problem of the area dependence of the photo resist pattern side wall taper angle is found in other companies, and the details are disclosed in Japanese Patent Application Laid-open No. Hei 09-54438.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an semiconductor device formed of inverted stagger type TFTs and a method of manufacturing the same, which can solve the above described problems.
Thus, it is an object of the present invention to solve the area dependence of photo resist pattern side wall taper angle in a photolithography step with diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist. In particular, it is an object of the present invention to the area dependence of the photo resist pattern side wall taper angle in a photolithography step which is a production process of a semiconductor device having inverted stagger type TFTs.
(Means for Solving Photo Resist Pattern Deformation)
First, a description will be made of means for solving resist pattern deformation with variation in taper angle dependent on the pattern area in a photolithography step.
As described above, pattern deformation with variation of side wall taper angle of large area photo resist pattern (about 10 μm or more) occurred as shown in FIG. 1 in a photolithography step with diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist. Since this pattern deformation dose not occur in fine pattern (about 3 82 m or less) formed simultaneously, it is observed that the pattern deformation is dependent on the dimension of the photo resist pattern, i.e., the area of the photo resist pattern (see FIG. 1).
The problem of the area dependence of the photo resist pattern side wall taper angle is found in other companies, and the details are disclosed in Japanese Patent Application Laid-open No. Hei 09-54438.
In patterning the photo resist pattern shown in FIG. 1, a reduction projection exposure apparatus is used as an exposure apparatus, in which a single wavelength (specifically, i-ray of an extra high-pressure mercury-vapor lamp) is used for accounting for chromatic aberration. Therefore, PEB process is generally applied between exposure and development because of adverse effect by standing wave due to a single wavelength of the exposed light. This company uses the PEB process in performing a photolithography step using the reduction projection exposure apparatus.
As described above, the photo resist pattern deformation with variation of side wall taper angle occurs in a photolithography step applying the PEB process between exposure and development, i.e., in a sequence of photo processes consisting of a photo resist coating→pre-bake (90° C. for one minute)→exposure (using the reduction projection exposure apparatus)-PEB (110° C. for three minutes)→development, and post-bake (120° C. for four minutes). In the photo process, since the photo resist pattern deformation occurs after the post-bake process (120° C. for four minutes) at glass transition temperature (about 150° C.) or less, which can be a softening point of the photo resist, it is apparent that the photo resist pattern deformation dose not occur due to thermal softening of the photo resist. Therefore, factors of the photo resist pattern deformation other than the thermal softening are discussed as described below (see FIG. 1).
In the normal photolithography step consisting of a combination of the diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist and a reduction projection exposure apparatus (also referred to as a stepper) which is a single wavelength (g-ray and i-ray of high-pressure mercury,-vapor lamp) exposure apparatus, it is considered that volume contraction phenomenon in the resist pattern due to evacuation of residual solvent at the post-bake causes a pattern deformation on the side wall of large area photo resist pattern (about 10 μm or more). Accordingly, it is expected that if PEB temperature for baking the entire resist film after exposure is equal to or greater than the post-bake temperature, evacuation of solvent component at the PEB process is promoted, and evacuation of the solvent from the resist pattern at post-bake is relatively reduced.
For verifying the above expectation, the influence on the dimension of the large area resist pattern edge was measured as changing PEB temperature from 110° C. to 150° C. The dimension of the large area resist pattern edge was then measured by means of a measurement SEM (see FIGS. 2A and 2B).
FIG. 2A is a plot of PEB temperature (horizontal axis) and pattern edge width (μm). In Fill. 2B, the large area pattern is a part of a concave LSA mark and the periphery of the mark is a resist region. The exposure time was adjusted so that the line length of 0.8 μm L/S becomes substantially 0.8 μm ever, PEB condition. Focus is 0.0 μm. Referring to FIGS. 2A and 2B, the dimension of the large area resist pattern edge is Gradually decreased in response to the rise of the PEB temperature, and it was observed that it is tended to be stable at the higher PEB temperature than that close to post-bake temperature (120° C.), i.e., the pattern deformation with variation in the side wall taper angle of the large area resist pattern due to volume contraction phenomenon is reduced in a region at the higher temperature region than that close to post-bake temperature (120° C.).
In other words, since decreasing the dimension of the large area photo resist pattern edge increases the side wall taper angle of the large area photo resist pattern, which means that the taper angle becomes sharp, it is understood that in a region at the PEB temperature higher than the post-bake temperature (120° C.), the side wall taper angle of the large area photo resist pattern is large and stable (see FIGS. 2A and 2B).
Accordingly, it is demonstrated that the pattern deformation with variation in the resist taper angle in the large area photo resist pattern is effectively controlled by rising PEB temperature equal to or higher than the post-bake temperature (see FIGS. 2A and 2B).
Actually, the PEB process is a step introduced to reduce interference fringes on the post-development resist pattern side wall occurring at a single wavelength exposure by the reduction projection exposure apparatus. The PEB process may not be necessarily introduced because interference fringes on the post-development resist pattern side wall basically do not occur in exposing by means of an equivalent projection exposure apparatus capable of multi-wavelength exposure (for example, g-ray, h-ray and i-ray of an extra high-pressure mercury-vapor lamp).
In practice, in a photolithography step for an inverted stagger type TFT manufactured on a large glass substrate, since the equivalent projection exposure apparatus using multi-wavelength is used for convenience of the production, a photo process without PEB process, i.e., a photo process consisting of a sequence of photo resist coating→pre-bake→exposure→development→post-bake is generally used.
Also, in this case, if the post-bake temperature (normally, about 110-140° C.) is higher than the pre-bake temperature (normally, about 90-100° C.), evacuation of residual solvent from the resist pattern at the post-bake is accelerated and the resist pattern deformation with variation in the taper angle due to volume contraction of the resist pattern may occur depending on the difference of the temperatures.
Based on the above discussion, in the photolithography step without PEB process, deformation of the photo resist pattern shape was measured as changing the pre-bake temperature (90° C., 110° C., and 130° C. -1.5 minutes) with the post-bake temperature being fixed (140° C. -two minutes). The photo resist pattern shape obtained is observed by means of cross-section SEM, and the measured results are shown in FIGS. 3A-3C. In the measurement, MPA (Canon inc.), which is an equivalent projection exposure apparatus, is used as an exposure apparatus, and a photo resist pattern having 3 μm line is used as measurement pattern.
FIGS. 3A-3C are SEMI photographs of the resist pattern cross-section, at pre-bake temperature 90° C. (FIG. 3A), 110° C. (FIG. 3B) and 130° C. (FIG. 3C), respectively, wherein exposure is performed by means of an equivalent projection exposure apparatus using multi-wavelengths, and development and post-bake (140° C.) are directly performed without the PEB process. As seen in the figures, for the pre-bake at 90° C. and 110° C., compared with the pre-bake at 130° C., volume contraction phenomenon of the resist pattern due to evacuation of the solvent at the post-bake is large, and deformation of the resist pattern is observed. To solve the problem, the difference between the pre-bake temperature and the post-bake temperature must be 10° C. or less.
In the measurement, the large area photo resist pattern (10 μm or more) is not measured. If the large area photo resist pattern is measured, appropriate range of the pre-bake temperature would be equal to or greater than that of the post-bake temperature similarly to a measurement with the PEB process because of severer condition of the measurement in terms of deformation phenomenon occurred due to volume contraction by evacuation of solvent at the post-bake. However, if the appropriate range of the pre-bake temperature is equal to or greater than that of the post-bake temperature, it is possible that exposure property such as sensitivity is adversely affected as pre-bake temperature rises. Preferably, the post-bake temperature is not excessively reduced for adherence of the photo resist pattern to the underlying substrate. From this point, the pre-bake temperature was measured using normal photo resist pattern (3 μm line pattern) rather than the large area photo resist pattern, and the bake condition was restricted so that pre-bake temperature is within ±10° C. relative to the post-bake temperature.
From the above discussion, for controlling variation of the taper angle dependent on change in size of the resist pattern regardless of the PEB process. Generally, it is understood that evacuation of residual solvent within the resist film is preferably accelerated in the state of the resist film before patterning in the development process, because volume contraction phenomenon is reduced due to evacuation solvent at the post-bake baking only the resist pattern. Specifically, for the process with PEB process, the bake condition is restricted so that PEB temperature is equal to or greater than the post-bake temperature. On the other hand, for the process without the PEB process, the bake condition is restricted so that pre-bake temperature is equal to or within ±10° C. relative to the post bake temperature.
Accordingly, in accordance with the present invention, a solution is provided which can solve a problem of the area dependence of the photo resist pattern side wall taper angle inducing the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake.
In the photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist without the PEB process, the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake is solved by restricting the pre-bake temperature within ±10° C. relative to the post-bake temperature.
In the photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist with the PEB process, the deformation phenomenon due to volume contraction occurred by evacuation of solvent from the photo resist pattern at the post-bake is solved by restricting the PEB temperature so as to be equal to or higher than the post-bake temperature.
(Method of Manufacturing a Semiconductor Device)
In a method of manufacturing a semiconductor device having inverted stagger type TFTs, reduction of patterning steps is considered to reduce the overall process steps, and the present invention relates to a method of manufacturing the semiconductor device using three photo masks. In the method of manufacturing the semiconductor device, means solution for solving the area dependence of photo resist pattern side wall taper angle which is a problem of a photolithography step is described below.
A method of manufacturing a semiconductor device in accordance with the present invention includes a first step of forming a first conductive film on an insulating surface, a second step of forming a resist pattern on the first conductive film, a third step of dry-etching the first conductive film to form a first pattern, a fourth step of forming a first insulating film on the first pattern, a fifth step of forming a first semiconductor film on the first insulating film, a sixth step of forming a one conductivity type second semiconductor film on the first semiconductor film, a seventh step of forming a second conductive film on the one conductivity type second semiconductor film, an eighth step of forming a resist pattern on the second conductive film, a ninth step of dry-etching the first semiconductor film, the one conductivity type second semiconductor film, and the second conductive film to form a second pattern, a tenth step of forming a third conductive film on the second pattern, an eleventh step of forming a resist pattern on the third conductive film, and a twelfth step of etching the third conductive film to form a third pattern,
It is to be noted that the third pattern formed by the twelfth step is patterned by etching not only the third conductive film but also the second pattern (formed by the ninth step).
Alternatively, a method of manufacturing a semiconductor device in accordance with the present invention comprises a first step of forming a first conductive film on an insulating film, a second step of forming a resist pattern on the first conductive film, a third step of dry-etching the first conductive film to form a gate electrode, a fourth step of forming a first insulating film on the gate electrode, a fifth step of forming a first semiconductor film on the first insulating film, a sixth step of forming a one conductivity type second semiconductor film on the first semiconductor film, a seventh step of forming a second conductive film on the one conductivity type second semiconductor film, an eighth step of forming a resist pattern on the second conductive film, a ninth step of dry-etching the first semiconductor film, the one conductivity type second semiconductor film, and the second conductive film to form a source wiring and an active layer, a tenth step of forming a third conductive film on the source wiring and the active layer, an eleventh step of forming a resist pattern on the third conductive film, and a twelfth step of etching the third conductive film to form a pixel electrode.
It is to be noted that the first insulating film formed by the fourth step is a gate insulating film. It is also to be noted that the source wiring and the active layer formed by the ninth step are formed of a laminated pattern consisting of the first semiconductor film and the one conductivity type second semiconductor film. According to a pattern forming by the twelfth step, while the pixel electrode is formed of the third conductive film, in addition, a channel region is formed of the first semiconductor film, a source region and a drain region are formed of the one conductivity type second semiconductor film, and a source electrode and a drain electrode are formed of the second conductive film.
In such a method of manufacturing a semiconductor device, each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, developing, and post-baking, characterized in that difference between the pre-bake temperature and the post-bake temperature is within ±10° C.
More specifically, each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, developing, and post-baking, characterized in that the pre-bake temperature is within ±10° C. relative to the post-bake temperature.
Alternatively, each of the second, the eighth and the eleventh steps includes the steps of resist coating, pre-baking, exposing, post-exposure baking, developing, and post-baking, characterized in that difference between the post-exposure bake temperature and the post-bake temperature is within ±10° C.
DESCRIPTION OF THE DRAWINGS
FIG. 1 An SEM photograph illustrating deformation of a resist shape in a conventional large area resist pattern.
FIG. 2A A graph illustrating PEB temperature dependence of the dimension of a large area resist pattern edge in accordance with the present invention.
FIG. 2B An SEM photograph specifically illustrating measurement position shown in FIG. 2A.
FIGS. 3A-3C SEM photographs of the resist pattern shapes in an equivalent projection exposure apparatus (MPA) in accordance with the present invention.
FIGS. 4A-4D Cross-sectional views illustrating the structure of an inverted stagger type TFT and a method of manufacturing the same in accordance with the present invention.
FIGS. 5A and 5B Cross-sectional views illustrating the structure of an inverted stagger type TFT and a method of manufacturing the same in accordance with the present invention.
FIG. 6 A top view illustrating the structure of a pixel region in an active matrix liquid crystal display device having the inverted stagger type TFTs.
 EMBODIMENT
The present invention relates to a structure of an inverted stagger type TFThaving a bottom gate structure and a method of manufacturing the same, characterized in that, by restricting a bake condition between a pre-bake temperature or PEB temperature and a post-bake temperature in a photolithographystep, taper angles of various dimensions of resist patterns are accurately controlled, as a result, accurately controlling shapes of various dimensions of etching patterns. Specific embodiment mode of the structure of the inverted stagger type TFT and the method of manufacturing the same in accordance with the present invention are described below with reference to FIGS. 4A-4D, FIGS. 5A-5B and FIG. 6.
It is to be noted that FIGS. 4A-4D and FIGS. 5A-5B are cross-sectional views illustrating a manufacturing steps of an active matrix liquid crystal display device, and FIG. 6 is a top view illustrating configuration of a pixel region in the active matrix liquid crystal display device. The cross-sectional views of FIGS. 4A-4D and FIGS. 5A-5B are taken along a line A-A′ and a line B-B′ in FIG. 6, respectively. In FIGS. 4A-4D and FIGS. 5A-5B, a terminal portion, a pixel TFT portion and a capacitor portion are shown from the left side.
At first, a first conductive film (not shown) used as a (gate electrode material is deposited on the overall surface of an insulating transparent substrate 101such as a glass substrate by sputtering or the like (a first step). The first conductive film (not shown) is used as a material for forming a gate wiring (including a gate electrode), a capacitor wiring (including a capacitor electrode) and the others, and preferably made from a low-resistance metal, such as Al (aluminum). However, since Al alone has problems such as less heat-resistance and susceptibility to corrosion, the first conductive film is generally made of a laminate film consisting of a low-resistance metal and a heat-resistant material. Included in the laminated film are a two-layer structure of a low-resistance material (e.g., Al) and a heat-resistant material, and a three-layer structure in which a low-resistance material is sandwiched between two heat-resistant material, i.e., a three-layer structure consisting of a heat-resistant material (e.g., Al)/ a low resistance material/a heat-resistant material (see FIG. 4A).
Generally used as a low resistance material is a material including Al as its principal component added with Sc (scandium), Ti (titanium), Cu (copper), Si (silicon) or the like at about 0.01-5%. On the other hand, used as a heat-resistant material is a high-melting metal such as Ti (titanium), Ta (tantalum), W (tungsten), Mo (molybdenum), Cr (chromium), or the like; a metal silicide which is a compound of the high-melting metal and silicon; or a metal nitride which is a compound of the high-melting metal and nitrogen. In this embodiment mode, the first conductive film (not shown) consisting of Ti (50 μm thick)/Al (200 nm thick)/Ti (50 nm thick) was deposited by sputtering (see FIG. 4A).
After forming the conductive layer on the overall surface of the transparent substrate 101, a resist mask is formed by a first photolithography step (a second step) In the photolithography step with PEB process, the bake condition is restricted so that PEB temperature is equal to or higher than the post-bake temperature, on the other hand, in the photolithography step without PEB process, the bake condition is restricted so that the pre-bake temperature is equal to the post-bake temperature or difference between the pre-bake temperature and the post-bake temperature is within about 10° C. Thus a resist mask (not shown) is formed having a taper angle accurately controlled (see FIG. 4A).
In this embodiment mode, the photolithography step without PEB process is applied and the bake condition is restricted so that the pre-bake temperature is within ±10° C. relative to the post-bake temperature. Therefore, the problem of the area dependency of the photo resist pattern side wall taper angle is solved which is deformation phenomenon due to the volume contraction occurred by evacuation of solvent at the post-bake.
Next, wiring and electrodes (a gate wiring 102 including a gate electrode, a capacitor wiring 103, and a terminal 104) are formed by etching out and then removing the resist mask (not shown) (a third step). In this case, the etching is performed so that a forward taper portion is formed at the end of the grate wiring 102 (see FIG. 4A).
Since little variation of the photo resist pattern side wall taper angle occurs in the taper etching shape of each wiring such as the gate wiring 102, a stable taper etching shape without variation is obtained (see FIG. 4A).
Next, a gate insulating film 105a which is formed of a silicon oxide film, a silicon oxide nitride film or a silicon nitride film having a thickness of 50-200 nm is deposited by plasma CVD or sputtering (a fourth step). In this embodiment, the gate insulating film 105a formed of a silicon nitride film having a thickness of 150 nm was deposited by plasma CVD (see FIG. 4A).
Next, a first amorphous semiconductor film 106 having a thickness of 50-200 nm is deposited on the gate insulating film 105a by plasma CVD or sputtering (a fifth step). In the embodiment mode, the first amorphous semiconductor film 106 formed of an amorphous silicon film and having the thickness of 100 nm was deposited by sputtering (see FIG. 4A).
Next, a second amorphous semiconductor film 107 having a thickness of 20-80 nm, containing one conductivity type (n-type or p-type) impurity element, is deposited by plasma CVD or sputtering (a sixth step). In this embodiment mode, the second amorphous semiconductor film 107 formed of all amorphous silicon film and having a thickness of 50 nm was deposited by sputtering, using a silicon target containing P (phosphorus) element as n-type impurity (see FIG. 4A).
Next, a second conductive film 108 made from metal material is deposited by sputtering (a seventh step). Any metal material having ohmic contact characteristics to the underlying second amorphous semiconductor film 107 is non-limited used as material of the second conductive film 108. For example, used may be a single-layer film formed of a single element or any alloys made from a plurality of elements, such as Al (aluminum), Cr (chromium), Ta (tantalum), and Ti (titanium), and a laminated layer consisting of the single layer film. In the embodiment mode, the second conductive film 108 having a three-layer structure consisting of Ti (100 nm thick),/Al (350 nm thick)/Ti (100 nm thick) was deposited by sputtering (see FIG. 4A).
In this way, the gate insulating film 105a having 50-200 nm thickness, the first amorphous semiconductor film 106 having 50-200 nm thickness, the second amorphous semiconductor film 107 having 20-80 nm thickness containing one conductivity type (n-type or p-type) impurity element, and the second conductive film 108 made from metal material are sequentially deposited. As described above, any metal material having ohmic contact characteristics to the second amorphous semiconductor film 107 is non-limitedly used as material of the second conductive film 108 (see FIG. 4A).
Next, a resist mask 109 with a taper angle being accurately controlled is formed by a second photolithography step (an eighth step), and then a wiring 112 (in the subsequent step, becoming a source wiring and a drain electrode) is formed by etching (a ninth step). At this point, the second conductive film 108, the second amorphous semiconductor film 107 containing an impurity element imparting n-type, and the first amorphous semiconductor film 106 are sequentially etched by using the resist mask 109 as a mask, and in a pixel TFT portion, the wiring 112 consisting of the second conductive film 108, the second amorphous semiconductor film 111 containing the impurity element imparting n-type, and the first amorphous semiconductor film 110 are sequentially formed (see FIG. 4B).
In the embodiment, the second conductive film 108 having a three-layer structure consisting of Ti (100 nm thick)/Al (350 nm thick)/Ti (100 nm thick) is dry-etched by using the mixed gas of SiCl4, Cl2, and BCl3 as dry etching gas, and the second amorphous semiconductor film 107 and the first amorphous semiconductor film 106 are dry-etched by using the mixed gas of CF4 and O2. In this case, the gate insulating film 105a in the capacitor portion and the terminal portion remains without being dry-etched.
In the dry etching step, since a laminated pattern consisting of the wiring 112 for forming a source and a drain electrodes, the second amorphous semiconductor film 111 for forming a source and a drain regions, and the first amorphous semiconductor film 110 for forming a channel region is dry-etched by using the photo resist mask 109 with little variation of the side wall taper angle as a mask, a stable etching shape can be obtained.
Next, after removing the resist mask 109, a resist mask (not shown) is formed using a shadow mask, and an insulating film 105b is formed by selectively removing a portion of the insulating film 105a, which covers a pad portion of the terminal portion. Thereafter, the resist mask (not shown) is removed (see FIG. 4C).
Next, a third conductive film 113 formed of a transparent conductive film is deposited overall thereon (a tenth step). Material of the third conductive film 113 includes indium oxide (In2O3), indium oxide-tin oxide alloy (In2O3—SnO2: hereafter referred to as ITO) and the others (see FIG. 4D).
In the embodiment mode, the third conductive film 113 made of ITO film having a thickness of 100 nm was deposited by sputtering.
Next, photo resist masks 114a-114c with taper angle being accurately controlled are formed by a third photolithography step (an eleventh step) (see FIG. 5A).
In the embodiment, the photolithography without PEB process is applied as well as in the second step and the eighth step, and the bake condition is restricted so that the pre-bake temperature is within ±10° C. relative to the post-bake temperature. Therefore, the problem of the area dependency of the photo resist pattern side wall taper angle is solved which is deformation phenomenon due to the volume contraction occurred by evacuation of solvent at the post-bake.
Moreover, a first amorphous semiconductor film 115; a source region 116 and a drain region 117; a source electrode 118 and a drain electrode 119; and a pixel electrode 120 are formed by etching. In the third photolithography step, the third conductive film 113 is patterned, while an opening is formed by etching out a portion of the wiring 112, a portion of the second amorphous semiconductor film 111 containing an impurity element imparting n-type, and a portion of the first amorphous semiconductor film 110. The bottom of the opening reaches the first amorphous semiconductor film 110, so that the first amorphous semiconductor film 115 having a concave portion is formed. The opening divides the wiring 112 into the source electrode (source wiring) 118 and the drain electrode 119, and the second amorphous semiconductor film 111 containing an impurity element imparting n-type is separated into the source region 116 and the drain region 117 (see FIG. 5A).
In the above etching step, wet-etching is used to etch the third conductive film 113. In the wet-etching, generally, an organic acid (about 3.4% solution: ITO-04 etchant), a mixture of nitric acid and hydrochloric acid, and ferric chloride solution are used as etchant. In the embodiment, the third conductive film (ITO film) 113 is selectively wet-etched by using the organic acid (about 3.4% solution: ITO-04N etchant). On the other hand, dry-etching is applied for the laminated film consisting of the wiring 112/ the second amorphous semiconductor film 111/ the first amorphous semiconductor film 110. In the embodiment, the wiring 112 for forming(y the source and, the drain electrodes having a three-layer structure consisting of Ti (100 nm thick)/Al (350 nm thick)/Ti (100 nm thick) was dry-etched using chlorine-based mixed gas (SiCl4, Cl2, and BCl3), while the second amorphous semiconductor film 111 for forming the source and drain regions consisting of an amorphous silicon film having 50 nm thickness containing P (phosphorus) element, and the first amorphous semiconductor film 110 for forming a channel region consisting of an amorphous silicon film having 100 nm thickness were dry-etched using fluorine-based gas (CF4 and O2.).
The etching shapes of the source electrode 118, the drain electrode 119, the source region 116, the drain region 117 and the others formed by the dry-etching step (except for wet-etching) are stable because of little variation of the photo resist pattern side wall taper angle.
A third conductive film 121 in contact with the source electrode (source wiring) 118 plays a role to cover the source electrode (source wiring) 118 and prevent electro statics from occurring by rubbing in the subsequent manufacturing steps. Also, in the third photolithography step, a storage capacitor 202 is formed with the capacitor wiring 103 and the pixel electrode 120using the insulating film 105b in the capacitor portion as dielectric. In the third photolithography step, a third conductive film remains which is formed of a transparent conductive film covered with a resist mask 114c and formed on the terminal portion. Next, the resist masks 114a-114c are removed (see FIG. 5B).
A plane configuration of a pixel region in the active matrix liquid crystal display device formed on the basis of the above manufacturing steps is shown in FIG. 6. The above manufacturing steps of the active matrix liquid crystal display device (FIGS. 4A-4D and FIGS. 5A-5B) is shown in cross-sectional views taken along the line of A-A′ (corresponding to the pixel TFT portion) and B-B′ (corresponding to the capacitor portion) in FIG. 6.
In the pixel region shown in FIG. 6, a plurality of gate wirings 102 positioned in parallel with each other and a plurality of source electrodes (source wirings) 118 each orthogonal to each of the gate wirings 102 are formed, and the pixel electrode 120 is provided in a region surrounded with the gate wiring 102 and the source electrode (source wiring) 118. The third conductive film 121, which is a transparent electrode wiring formed simultaneously with the pixel electrode 120, is provided so as to overlap the source electrode (source wiring) 118, and plays a role to prevent electro statics from occurring by rubbing in the subsequent step. In the embodiment, while the third conductive film 121 overlaps the source electrode (source wiring,) 118, the third conductive film 121 may not be formed.
Moreover, the capacitor wiring 103 is provided adjacent to and in parallel with the gate wiring 102. The capacitor wiring (including the capacitor electrode) 103 is provided in each of all pixels, the storage capacitor 202 is formed using a gate insulating film 104b between the capacitor wiring 103 and the pixel electrode 120 as dielectric. In the intersection of the gate wiring 102 and the source electrode (source wiring) 118, an inverted stagger type n-channel TFT 201 is formed which functions as a switching element (see FIG. 6).
In the embodiment, in the manufacturing process of the active matrix liquid crystal display device having inverted stagger type TFTs, a photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist without PEB process is applied, and the bake condition is restricted so that the pre-bake temperature is within ±10° C. relative to the post-bake temperature. Therefore, an excellent photo resist pattern is formed without deformation phenomenon due to volume contraction occurred by evacuation of solvent at the post-bake. Since no deformation phenomenon occurs due to volume contraction, it is characterized in that the photo resist pattern has no problem of the area dependency of the photo resist pattern side wall taper angle.
As described above, the inverted stagger type TFT having the bottom gate structure of the present invention is manufactured using photo masks three times, and thus, it is characterized in that low-cost and improvement of yield are achieved. In the photolithography step using the photo mask with the PEB process, the bake condition is restricted so that the PEB temperature is equal to or higher than the post-bake temperature, while without the PEB process, the bake condition is restricted so that the pre-bake temperature is equal to or within ±10° C. relative to the post-bake temperature, so that the resist pattern can be formed with the taper angle being accurately controlled, thereby obtaining the etching pattern accurately controlled. Advantages of the present invention having characteristics described above arc recited below.
(Advantage 1)
In the manufacturing process of the semiconductor device having inverted stagger type TFTs, for the case of applying a photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist without the PEB process, the bake condition is restricted so that the pre-bake temperature is within ±10° C. relative to the post-bake temperature, while for a photolithography step with the PEB process, the bake condition is restricted so that the PEB temperature is equal to or higher than the post-bake temperature. By such a bake condition restriction, a problem of the area dependency of the photo resist pattern side wall taper angle can be solved which is deformation phenomenon due to the volume contraction occurred by evacuation of solvent at the post-bake.
(Advantage 2)
In the photolithography step which is a manufacturing process of the semiconductor device having inverted stagger type TFTs, since the problem of the area dependency of the photo resist pattern side wall taper angle can be solved which is deformation phenomenon due to the volume contraction occurred by evacuation of solvent at the post-bake, a stable etching shape independent on the pattern area can be achieved in the subsequent dry-etching step. Especially, since in the production process of the semiconductor device, a plurality of laminated layer films are dry-etched in a batch, variation of the photo resist pattern side wall taper angle might sensitively influence the dry-etching shape. Accordingly, stabilization of the photo resist pattern side wall taper angle may advantageously affect stabilization of the etching shape.
(Advantage 3)
In the dry-etching step of the manufacturing process of the semiconductor device having inverted stagger type TFTs, since a stable etching shape independent on the pattern area can be achieved, improvements of both quality and yield of the semiconductor device are advantageously achieved.
(Advantage 4)
In the manufacturing process of the semiconductor device having inverted stagger type TFTs, since it is intended to reduce the manufacturing steps by reducing the number of photo masks, both yield and productivity are also improved.

Claims (18)

1. A method of manufacturing a semiconductor device, said method comprises the steps of:
forming a first conductive film on an insulating surface;
forming a first photo resist pattern on the first conductive film;
dry-etching the first conductive film to form a first pattern;
depositing a first insulating film on the first pattern;
depositing a first semiconductor film on the first insulating film;
depositing a one conductivity type second semiconductor film on the first semiconductor film;
depositing a second conductive film on the one conductivity type second semiconductor film;
forming a second photo resist pattern on the second conductive film;
dry-etching the first semiconductor film, the one conductivity type second semiconductor film, and the second conductive film to form a second pattern;
depositing a third conductive film on the second pattern;
forming a third photo resist pattern on the third conductive film; and
etching the third conductive film and the second pattern to form a third pattern,
each of the steps of forming the first, the second and the third photo resist patterns comprising the steps of.:
coating a photo resist;
performing a pre-bake after coating the photo resist;
performing an exposure after performing the pre-bake;
performing a development after the exposure; and
performing a post-bake after the development,
wherein a pre-bake temperature is within ±10° C., relative to a post-bake temperature.
2. A method of manufacturing a semiconductor device having inverted stagger type thin-film transistors, said method comprises the steps of:
depositing a first conductive film on an insulating surface;
forming a first photo resist pattern on the first conductive film;
dry-etching the first conductive film to form a gate electrode;
depositing a gate insulating film on the gate electrode;
depositing a first semiconductor film on the gate insulating film;
depositing a one conductivity type second semiconductor film on the first semiconductor film;
depositing a second conductive film on the one conductivity-type second semiconductor film;
forming a second photo resist pattern on the second conductive film;
dry-etching the first semiconductor film, the one conductivity type second semiconductor film and the second conductive film to form a laminated film comprising the first semiconductor film, the one conductivity type second semiconductor film and the second conductive film;
depositing a third conductive film on the laminated film pattern;
forming a third photo resist pattern on the third conductive film;
etching the third conductive film to form a pixel electrode; and
dry-etching the laminated film to form a channel region from the first semiconductor film, to form a source region and a drain region from the one conductivity type second semiconductor film and to form a source electrode and a drain electrode from the second conductive film,
each of the steps of forming the first, the second and the third photo resist patterns comprising the steps of.:
coating a photo resist;
performing a pre-bake after coating the photo resist;
performing an exposure after performing the pre-bake;
performing a development after performing the exposure; and
performing a post-bake after performing the development,
wherein a pre-bake temperature is within ±10° C. relative to a post-bake temperature.
3. A method of manufacturing, a semiconductor device according, to claim 1, wherein the step of performing, the exposure comprises performing an exposure using a multi-wavelength light.
4. A method of manufacturing a semiconductor device according to claim 1, wherein the step of performing the exposure comprises performing an exposure using an equivalent projection exposure apparatus.
5. A method of manufacturing a semiconductor device, said method comprises the steps of:
depositing a first conductive film on an insulating surface;
forming a first photo resist pattern on the first conductive film;
dry-etching the first conductive film to form a first pattern;
depositing a first insulating film on the first pattern;
depositing a first semiconductor film on the insulating the insulating film;
depositing a one conductivity type second semiconductor film on the first semiconductor film;
depositing a second conductive film on the one conductivity type second semiconductor film;
forming a second photo resist pattern on the second conductive film;
dry-etching the first semiconductor film, the one conductivity type second semiconductor film, and the second conductive film to form a second pattern;
depositing a third conductive film on the second pattern;
forming a third photo resist pattern on the third conductive film; and
etching the third conductive film and the second pattern to form a third pattern,
each of the steps of forming the first, the second and the third photo resist patterns comprising the steps of:
coating a photo resist;
performing a pre-bake after coating the photo resist;
performing an exposure after performing the pre-bake;
performing a post-exposure bake after performing the exposure;
performing a development after performing the post-exposure bake; and
performing a post-bake after performing the development,
wherein a post-exposure bake temperature is equal to or greater than a post-bake temperature.
6. A method of manufacturing a semiconductor device having inverted stagger type thin-film transistors,
said method comprises the steps of:
depositing a first conductive film on an insulating surface;
forming a first photo resist pattern on the first conductive film;
dry-etching the first conductive film to form a gate electrode;
depositing a gate insulating film on the gate electrode;
depositing a first semiconductor film on the gate insulating film;
depositing a one conductivity type second semiconductor film on the first semiconductor film;
depositing a second conductive film on the one conductivity type second semiconductor film;
forming a second photo resist pattern on the second conductive film;
dry-etching the first semiconductor film, the one conductivity type second semiconductor film and the second conductive film to form a laminated film comprising the first semiconductor film, the one conductivity type second semiconductor film and the second conductive film;
depositing a third conductive film on the laminated film;
forming a third photo resist pattern on the third conductive film;
etching the third conductive film to form a pixel electrode; and
dry-etching the laminated film to form a channel region from the first semiconductor film, to form a source region and a drain region from the one conductivity type second semiconductor film and to form a source electrode and a drain electrode from the second conductive film,
each of the steps of forming the first, the second and the third photo resist patterns comprising the steps of;:
coating a photo resist;
performing a pre-bake after coating the photo resist;
performing an exposure after performing the pre-bake;
performing a post-exposure bake after performing the exposure;
performing a development after performing the post-exposure; and
performing a post-bake after performing the development,
wherein a post-exposure bake temperature is equal to or higher than a post-bake temperature.
7. A method of manufacturing a semiconductor device according to claim 5, wherein the step of performing the exposure comprises performing an exposure using a single-wavelength light.
8. A method of manufacturing a semiconductor device according to claim 5, wherein the step of performing the exposure comprises performing an exposure using a reduction projection exposure apparatus.
9. A method of manufacturing a semiconductor device according to claim 2, wherein the step of performing the exposure comprises performing an exposure using a multi-wavelength light.
10. A method of manufacturing a semiconductor device according to claim 2, wherein the step of performing the exposure comprises performing an exposure using an equivalent projection exposure apparatus.
11. A method of manufacturing a semiconductor device according to claim 6, wherein the step of performing the exposure comprises performing an exposure using a single-wavelength light.
12. A method of manufacturing a semiconductor device according to claim 6, wherein the step of performing the exposure comprises performing an exposure using a reduction projection exposure apparatus.
13. A method of manufacturing a semiconductor device, said method comprising the steps of:
forming a conductive film on an insulating surface;
forming a photo resist on the conductive film;
pre-baking the photo resist at a first temperature;
performing an exposure to the photo resist after pre-baking the photo resist;
performing a development after the exposure;
post-baking the photo resist at a second temperature after the development; and
etching the conductive film by using the post-baked photo resist to form a wiring having a taper portion,
wherein the first temperature is within ±10° C. relative to the second temperature.
14. A method of manufacturing a semiconductor device according to claim 13, wherein the step of performing the exposure comprises performing an exposure using a multi-wavelength light.
15. A method of manufacturing a semiconductor device according to claim 13, wherein the step of performing the exposure comprises performing an exposure using an equivalent projection exposure apparatus.
16. A method of manufacturing a semiconductor device, said method comprising the steps of:
forming a conductive film on an insulating surface;
coating a photo resist on the conductive film;
pre-baking the photo resist at a first temperature;
performing an exposure to the pre-baked photo resist;
performing a post-exposure bake to the photo resist at a second temperature;
performing a development to the post-exposure baked photo resist;
post-baking the developed photo resist at a third temperature; and
etching the conductive film by using the post-baked photo resist to form a wiring having a taper portion,
wherein the second temperature is equal to or greater than the third temperature.
17. A method of manufacturing a semiconductor device according to claim 16, wherein the step of performing the exposure comprises performing an exposure using a single-wavelength light.
18. A method of manufacturing a semiconductor device according to claim 16, wherein the step of performing the exposure comprises performing an exposure using a reduction projection exposure apparatus.
US10/960,898 2000-05-13 2004-10-08 Method of manufacturing a semiconductor device Expired - Lifetime USRE43471E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/960,898 USRE43471E1 (en) 2000-05-13 2004-10-08 Method of manufacturing a semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000180549 2000-05-13
JP2000-180549 2000-05-13
US09/852,916 US6461886B1 (en) 2000-05-13 2001-05-11 Method of manufacturing a semiconductor device
US10/960,898 USRE43471E1 (en) 2000-05-13 2004-10-08 Method of manufacturing a semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/852,916 Reissue US6461886B1 (en) 2000-05-13 2001-05-11 Method of manufacturing a semiconductor device

Publications (1)

Publication Number Publication Date
USRE43471E1 true USRE43471E1 (en) 2012-06-12

Family

ID=18681613

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/852,916 Ceased US6461886B1 (en) 2000-05-13 2001-05-11 Method of manufacturing a semiconductor device
US10/960,898 Expired - Lifetime USRE43471E1 (en) 2000-05-13 2004-10-08 Method of manufacturing a semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/852,916 Ceased US6461886B1 (en) 2000-05-13 2001-05-11 Method of manufacturing a semiconductor device

Country Status (3)

Country Link
US (2) US6461886B1 (en)
KR (1) KR100825907B1 (en)
TW (1) TW497269B (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100825907B1 (en) * 2000-05-13 2008-04-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 A method of manufacturing a semiconductor device
US7102168B2 (en) * 2001-12-24 2006-09-05 Samsung Electronics Co., Ltd. Thin film transistor array panel for display and manufacturing method thereof
US6716681B2 (en) * 2002-03-27 2004-04-06 Chi Mei Optoelectronics Corp. Method for manufacturing thin film transistor panel
US7344825B2 (en) 2002-04-04 2008-03-18 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating semiconductor device, and developing apparatus using the method
KR100820842B1 (en) * 2002-07-15 2008-04-10 삼성전자주식회사 Pattern mask assembly for exposure and liquid crystal display substrate using the same
US7875419B2 (en) * 2002-10-29 2011-01-25 Semiconductor Energy Laboratory Co., Ltd. Method for removing resist pattern and method for manufacturing semiconductor device
TW589663B (en) * 2003-05-12 2004-06-01 Au Optronics Corp Flat panel display and manufacturing method thereof
JP2004347682A (en) * 2003-05-20 2004-12-09 Tokyo Ohka Kogyo Co Ltd Positive photoresist composition for manufacturing system liquid crystal display and method for forming resist pattern
US7115488B2 (en) * 2003-08-29 2006-10-03 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
KR101028662B1 (en) * 2004-05-31 2011-04-12 엘지디스플레이 주식회사 Manufacturing method of thin film transistor and semiconductor film pattern for liquid crystal display device
TWI234288B (en) * 2004-07-27 2005-06-11 Au Optronics Corp Method for fabricating a thin film transistor and related circuits
KR101240643B1 (en) 2005-07-08 2013-03-08 삼성디스플레이 주식회사 Photoresist composition, a method for forming a pattern using the same, and a method for manufacturing thin film transistor array panel using the same
US20070287209A1 (en) * 2006-04-28 2007-12-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing light-emitting device
US7910929B2 (en) * 2007-12-18 2011-03-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20110287593A1 (en) * 2010-05-20 2011-11-24 Semiconductor Energy Laboratory Co., Ltd. Method for forming semiconductor film and method for manufacturing semiconductor device
CN104576523A (en) * 2013-10-16 2015-04-29 北京京东方光电科技有限公司 Array substrate, production method of array substrate and display device
KR102525586B1 (en) * 2017-11-15 2023-04-26 삼성디스플레이 주식회사 Photo mask and method of manufacturing semiconductor element using photo mask

Citations (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03232274A (en) 1989-08-14 1991-10-16 Hitachi Ltd Thin film transistor, manufacture thereof, liquid crystal display panel, and liquid display device
US5078771A (en) 1989-02-07 1992-01-07 Canyon Materials, Inc. Method of making high energy beam sensitive glasses
US5174857A (en) * 1990-10-29 1992-12-29 Gold Star Co., Ltd. Slope etching process
EP0530834A1 (en) 1991-09-05 1993-03-10 Casio Computer Company Limited Thin-film transistor and method of manufacturing the same
EP0544069A1 (en) 1991-11-26 1993-06-02 Casio Computer Company Limited Thin-film transistor panel and method of manufacturing the same
JPH05152327A (en) 1991-11-27 1993-06-18 Casio Comput Co Ltd Manufacturing method of thin film transistor panel
JPH05206086A (en) 1992-01-27 1993-08-13 Fujitsu Ltd Method of etching thin film
US5242543A (en) * 1991-02-06 1993-09-07 Mitsubishi Denki Kabushiki Kaisha Wet etching method for forming metal film pattern having tapered edges
US5248576A (en) * 1989-09-18 1993-09-28 Idemitsu Kosan Co., Ltd. Method of producing color filter using a micellar disruption method
US5334859A (en) 1991-09-05 1994-08-02 Casio Computer Co., Ltd. Thin-film transistor having source and drain electrodes insulated by an anodically oxidized film
JPH06222370A (en) 1993-01-25 1994-08-12 Sony Corp Production of liquid crystal panel
JPH06244155A (en) 1993-02-19 1994-09-02 Sumitomo Metal Ind Ltd Formation of metallic wiring pattern of semiconductor device
JPH07153965A (en) 1993-11-30 1995-06-16 Sanyo Electric Co Ltd Manufacture of thin-film transistor
JPH0887033A (en) 1994-09-16 1996-04-02 Toshiba Corp Production of active matrix display
US5518860A (en) 1994-06-08 1996-05-21 Tokyo Ohka Kogyo Co., Ltd. Positive-working quinonediazide photoresist composition containing hydroxyalkyl substituted pyridine compound
US5589962A (en) 1992-06-08 1996-12-31 Hitachi, Ltd. Active matrix display device using aluminum alloy in scanning signal line or video signal line
US5604138A (en) 1993-12-16 1997-02-18 Goldstar Electron Co., Ltd. Process for making a semiconductor MOS transistor
JPH0954438A (en) 1995-08-17 1997-02-25 Mitsubishi Electric Corp Photoresist pattern and its forming method
US5607900A (en) 1991-03-28 1997-03-04 Sumitomo Electric Industries, Ltd. Process for cleaning a surface of thin film of oxide superconductor
KR970051899A (en) 1995-12-27 1997-07-29 김광호 Pattern formation method of semiconductor device
JPH09197436A (en) 1996-01-23 1997-07-31 Toshiba Corp Active matrix substrate
JPH09274313A (en) 1996-04-03 1997-10-21 Toshiba Corp Formation of resist pattern
JPH09279367A (en) 1996-04-17 1997-10-28 Mitsubishi Electric Corp Al taper dry etching method
JPH09288347A (en) 1996-02-20 1997-11-04 Ricoh Co Ltd Reticle with dummy pattern and semiconductor device produced by using the same
JPH1026829A (en) 1996-07-10 1998-01-27 Japan Synthetic Rubber Co Ltd Radiation sensitive resin composition
JPH1056179A (en) 1996-08-08 1998-02-24 Hoshiden Philips Display Kk Manufacture of thin film device
KR19990004786A (en) 1997-06-30 1999-01-25 배순훈 Manufacturing method of thin film type optical path control device
KR19990070241A (en) 1998-02-18 1999-09-15 구본준 Manufacturing Method of Semiconductor Device
JP2000047263A (en) 1998-07-31 2000-02-18 Fujitsu Ltd Etching method, thin film transistor matrix substrate and its production
JP2000089477A (en) 1998-09-11 2000-03-31 Nec Corp Resist pattern forming method
US6051484A (en) 1996-03-08 2000-04-18 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing thereof
US6156583A (en) 1998-06-13 2000-12-05 Lg Philips Lcd Co., Ltd. Method for manufacturing a liquid crystal display device
US6221787B1 (en) 1998-04-20 2001-04-24 Tokyo Electron Limited Apparatus and method of forming resist film
US6304309B1 (en) * 1998-03-19 2001-10-16 Matsushita Electric Industrial Co., Ltd. Liquid crystal display device and method of manufacturing the same
JP2001339072A (en) 2000-03-15 2001-12-07 Advanced Display Inc Liquid crystal display device
US20020016028A1 (en) * 2000-06-07 2002-02-07 Tatsuya Arao Method of manufacturing semiconductor device
US20020022364A1 (en) * 2000-08-16 2002-02-21 Yoshihisa Hatta Method for producing a metal film, a thin film device having such metal film and a liquid crystal display device having such thin film device
US20020122285A1 (en) * 2000-12-21 2002-09-05 Alps Electric Co., Ltd. Temperature-compensating thin-film capacitor and electronic device
US20020125427A1 (en) * 2001-03-09 2002-09-12 Veeco Instruments Inc. Method and apparatus for manipulating a sample
US20020127887A1 (en) * 2000-05-13 2002-09-12 Ichiro Uehara Method of manufacturing a semiconductor device
US20030160236A1 (en) * 2000-03-13 2003-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
US20030186478A1 (en) * 2002-04-02 2003-10-02 Advanced Display Inc. Thin film transistor array, fabrication method thereof, and liquid crystal display device employing the same
US6716681B2 (en) * 2002-03-27 2004-04-06 Chi Mei Optoelectronics Corp. Method for manufacturing thin film transistor panel
US6746965B2 (en) * 2001-08-01 2004-06-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US6838696B2 (en) 2000-03-15 2005-01-04 Advanced Display Inc. Liquid crystal display
US20050011752A1 (en) * 2003-02-05 2005-01-20 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for wiring
US20050024549A1 (en) * 2003-07-28 2005-02-03 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing thin film transistor array
US6855957B1 (en) * 2000-03-13 2005-02-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20050112889A1 (en) * 1999-04-16 2005-05-26 Junichi Inoue Semiconductor device manufacturing method and manufacturing line thereof
US6900084B1 (en) * 2000-05-09 2005-05-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a display device
US7102718B1 (en) * 2000-03-16 2006-09-05 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device with particular TFT structure and method of manufacturing the same

Patent Citations (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5078771A (en) 1989-02-07 1992-01-07 Canyon Materials, Inc. Method of making high energy beam sensitive glasses
US5585290A (en) 1989-08-14 1996-12-17 Hitachi, Ltd. Method of manufacturing a thin film transistor substrate
JPH03232274A (en) 1989-08-14 1991-10-16 Hitachi Ltd Thin film transistor, manufacture thereof, liquid crystal display panel, and liquid display device
US5889573A (en) 1989-08-14 1999-03-30 Hitachi, Ltd. Thin film transistor substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal display equipment
US5672523A (en) 1989-08-14 1997-09-30 Hitachi, Ltd. Thin film transistor substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal display equipment
US5719408A (en) 1989-08-14 1998-02-17 Hitachi, Ltd. Thin film transistor substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal display equipment
US5359206A (en) 1989-08-14 1994-10-25 Hitachi, Ltd. Thin film transistor substrate, liquid crystal display panel and liquid crystal display equipment
US5248576A (en) * 1989-09-18 1993-09-28 Idemitsu Kosan Co., Ltd. Method of producing color filter using a micellar disruption method
US5174857A (en) * 1990-10-29 1992-12-29 Gold Star Co., Ltd. Slope etching process
US5242543A (en) * 1991-02-06 1993-09-07 Mitsubishi Denki Kabushiki Kaisha Wet etching method for forming metal film pattern having tapered edges
US5607900A (en) 1991-03-28 1997-03-04 Sumitomo Electric Industries, Ltd. Process for cleaning a surface of thin film of oxide superconductor
EP0530834A1 (en) 1991-09-05 1993-03-10 Casio Computer Company Limited Thin-film transistor and method of manufacturing the same
US5334859A (en) 1991-09-05 1994-08-02 Casio Computer Co., Ltd. Thin-film transistor having source and drain electrodes insulated by an anodically oxidized film
EP0544069A1 (en) 1991-11-26 1993-06-02 Casio Computer Company Limited Thin-film transistor panel and method of manufacturing the same
JPH05152327A (en) 1991-11-27 1993-06-18 Casio Comput Co Ltd Manufacturing method of thin film transistor panel
JPH05206086A (en) 1992-01-27 1993-08-13 Fujitsu Ltd Method of etching thin film
US5589962A (en) 1992-06-08 1996-12-31 Hitachi, Ltd. Active matrix display device using aluminum alloy in scanning signal line or video signal line
US6226059B1 (en) 1992-06-08 2001-05-01 Hitachi, Ltd. Active matrix display device using aluminum alloy in scanning signal line or video signal line
US5781255A (en) 1992-06-08 1998-07-14 Hitachi, Ltd. Active matrix display device using aluminum alloy in scanning signal line or video signal line
JPH06222370A (en) 1993-01-25 1994-08-12 Sony Corp Production of liquid crystal panel
JPH06244155A (en) 1993-02-19 1994-09-02 Sumitomo Metal Ind Ltd Formation of metallic wiring pattern of semiconductor device
JPH07153965A (en) 1993-11-30 1995-06-16 Sanyo Electric Co Ltd Manufacture of thin-film transistor
US5604138A (en) 1993-12-16 1997-02-18 Goldstar Electron Co., Ltd. Process for making a semiconductor MOS transistor
US5518860A (en) 1994-06-08 1996-05-21 Tokyo Ohka Kogyo Co., Ltd. Positive-working quinonediazide photoresist composition containing hydroxyalkyl substituted pyridine compound
JPH0887033A (en) 1994-09-16 1996-04-02 Toshiba Corp Production of active matrix display
JPH0954438A (en) 1995-08-17 1997-02-25 Mitsubishi Electric Corp Photoresist pattern and its forming method
KR970051899A (en) 1995-12-27 1997-07-29 김광호 Pattern formation method of semiconductor device
JPH09197436A (en) 1996-01-23 1997-07-31 Toshiba Corp Active matrix substrate
JPH09288347A (en) 1996-02-20 1997-11-04 Ricoh Co Ltd Reticle with dummy pattern and semiconductor device produced by using the same
US6051484A (en) 1996-03-08 2000-04-18 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing thereof
JPH09274313A (en) 1996-04-03 1997-10-21 Toshiba Corp Formation of resist pattern
JPH09279367A (en) 1996-04-17 1997-10-28 Mitsubishi Electric Corp Al taper dry etching method
JPH1026829A (en) 1996-07-10 1998-01-27 Japan Synthetic Rubber Co Ltd Radiation sensitive resin composition
JPH1056179A (en) 1996-08-08 1998-02-24 Hoshiden Philips Display Kk Manufacture of thin film device
KR19990004786A (en) 1997-06-30 1999-01-25 배순훈 Manufacturing method of thin film type optical path control device
KR19990070241A (en) 1998-02-18 1999-09-15 구본준 Manufacturing Method of Semiconductor Device
US20020135720A1 (en) * 1998-03-19 2002-09-26 Matsushita Electric Industrial Co., Ltd. Liquid crystal display device and method for fabricating the same
US6563557B2 (en) * 1998-03-19 2003-05-13 Matsushita Electric Industrial Co., Ltd. Liquid crystal display device including a stack of plurality of resin film and method for fabricating the same
US6304309B1 (en) * 1998-03-19 2001-10-16 Matsushita Electric Industrial Co., Ltd. Liquid crystal display device and method of manufacturing the same
US6221787B1 (en) 1998-04-20 2001-04-24 Tokyo Electron Limited Apparatus and method of forming resist film
US6156583A (en) 1998-06-13 2000-12-05 Lg Philips Lcd Co., Ltd. Method for manufacturing a liquid crystal display device
US6335290B1 (en) 1998-07-31 2002-01-01 Fujitsu Limited Etching method, thin film transistor matrix substrate, and its manufacture
JP2000047263A (en) 1998-07-31 2000-02-18 Fujitsu Ltd Etching method, thin film transistor matrix substrate and its production
US6534789B2 (en) 1998-07-31 2003-03-18 Fujitsu Limited Thin film transistor matrix having TFT with LDD regions
JP2000089477A (en) 1998-09-11 2000-03-31 Nec Corp Resist pattern forming method
US20050112889A1 (en) * 1999-04-16 2005-05-26 Junichi Inoue Semiconductor device manufacturing method and manufacturing line thereof
US20050221542A1 (en) * 2000-03-13 2005-10-06 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and manufacturing method thereof
US20030160236A1 (en) * 2000-03-13 2003-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
US6806499B2 (en) * 2000-03-13 2004-10-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
US20050041166A1 (en) * 2000-03-13 2005-02-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
US6709901B1 (en) * 2000-03-13 2004-03-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having stick drivers and a method of manufacturing the same
US6855957B1 (en) * 2000-03-13 2005-02-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP2001339072A (en) 2000-03-15 2001-12-07 Advanced Display Inc Liquid crystal display device
US7084017B2 (en) 2000-03-15 2006-08-01 Advanced Display Inc. Liquid crystal display
US7755088B2 (en) 2000-03-15 2010-07-13 Mitsubishi Electric Corporation Liquid crystal display
US7645648B2 (en) 2000-03-15 2010-01-12 Mitsubishi Electric Corporation Liquid crystal display
US7394097B2 (en) 2000-03-15 2008-07-01 Mitsubishi Electric Corporation Liquid crystal display
US6838696B2 (en) 2000-03-15 2005-01-04 Advanced Display Inc. Liquid crystal display
US7102718B1 (en) * 2000-03-16 2006-09-05 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device with particular TFT structure and method of manufacturing the same
US7102165B2 (en) * 2000-05-09 2006-09-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20050205870A1 (en) * 2000-05-09 2005-09-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6900084B1 (en) * 2000-05-09 2005-05-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a display device
US20070001171A1 (en) * 2000-05-09 2007-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6461886B1 (en) * 2000-05-13 2002-10-08 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US20020127887A1 (en) * 2000-05-13 2002-09-12 Ichiro Uehara Method of manufacturing a semiconductor device
US20040018670A1 (en) * 2000-06-07 2004-01-29 Semiconductor Energy Laboratory Co., Ltd., A Japan Corporation Method of manufacturing semiconductor device
US20020016028A1 (en) * 2000-06-07 2002-02-07 Tatsuya Arao Method of manufacturing semiconductor device
US6596571B2 (en) * 2000-06-07 2003-07-22 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US6933184B2 (en) * 2000-06-07 2005-08-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US20020022364A1 (en) * 2000-08-16 2002-02-21 Yoshihisa Hatta Method for producing a metal film, a thin film device having such metal film and a liquid crystal display device having such thin film device
US6556421B2 (en) * 2000-12-21 2003-04-29 Alps Electric Co., Ltd. Temperature-compensating thin-film capacitor and electronic device
US20020122285A1 (en) * 2000-12-21 2002-09-05 Alps Electric Co., Ltd. Temperature-compensating thin-film capacitor and electronic device
US20020125427A1 (en) * 2001-03-09 2002-09-12 Veeco Instruments Inc. Method and apparatus for manipulating a sample
US6746965B2 (en) * 2001-08-01 2004-06-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US6716681B2 (en) * 2002-03-27 2004-04-06 Chi Mei Optoelectronics Corp. Method for manufacturing thin film transistor panel
US20030186478A1 (en) * 2002-04-02 2003-10-02 Advanced Display Inc. Thin film transistor array, fabrication method thereof, and liquid crystal display device employing the same
US6750087B2 (en) * 2002-04-02 2004-06-15 Advanced Display Inc. Thin film transistor array, fabrication method thereof, and liquid crystal display device employing the same
US20050011752A1 (en) * 2003-02-05 2005-01-20 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for wiring
US20050024549A1 (en) * 2003-07-28 2005-02-03 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing thin film transistor array

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Office Action (Korean Application No. 2001-0025719) mailed Jul. 25, 2007 with English language translation.
Office Action, Japanese Application No. 2001-144035, dated Aug. 2, 2011, 14 pages with English translation.

Also Published As

Publication number Publication date
US20020127887A1 (en) 2002-09-12
KR100825907B1 (en) 2008-04-28
US6461886B1 (en) 2002-10-08
KR20010104263A (en) 2001-11-24
TW497269B (en) 2002-08-01

Similar Documents

Publication Publication Date Title
USRE41632E1 (en) Liquid crystal display device and method of manufacturing the same
US8563980B2 (en) Array substrate and manufacturing method
USRE43471E1 (en) Method of manufacturing a semiconductor device
US6927105B2 (en) Thin film transistor array substrate and manufacturing method thereof
US7553711B2 (en) Method for fabricating a thin film transistor for use with a flat panel display device
US8896794B2 (en) Liquid crystal display device and method for fabricating the same
US7649581B2 (en) Array substrate of an LCD comprising first and second gate insulating layers and method of fabricating the same
US7718994B2 (en) Array substrates for use in liquid crystal displays and fabrication methods thereof
US20070102770A1 (en) Thin film transistor array panel and manufacturing method thereof
US7422916B2 (en) Method of manufacturing thin film transistor panel
US7381597B2 (en) Method for fabricating a thin-film transistor
US8093110B2 (en) Method for manufacturing thin film transistor
KR100881819B1 (en) Method for manufacturing a bottom substrate of a liquid crystal display
JP2002098995A (en) Method of manufacturing matrix substrate for liquid crystal
JP3706043B2 (en) Manufacturing method of matrix substrate for liquid crystal
TW201322340A (en) Pixel structure and method of fabricating the same
KR20070045751A (en) Mask for photo lithography
JP2002098994A (en) Matrix substrate for liquid crystal, and method for manufacturing the same and method of forming the contact hole
JP3706033B2 (en) Manufacturing method of matrix substrate for liquid crystal
JP5276758B2 (en) Method for manufacturing liquid crystal display device
KR0183757B1 (en) Method of manufacturing thin-film transistor liquid crystal display device
KR101586860B1 (en) Array Substrate for Liquid Crystal Display Device and Manufacturing Method of the same
KR20020056705A (en) Method for manufacturing the thin film transistor liquid crystal display device
US20050101071A1 (en) Thin film transistor structure and method of manufacturing the same

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 12