JPH06244155A - Formation of metallic wiring pattern of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a metallic wiring pattern forming method by which line widths can be excellently controlled and reproduced by performing anisotropic reactive ion etching by using a mixed gas of Cl2 and BCl3 on a metallic layer after successively forming an SiO2 film, the metallic layer, and a resist pattern on a substrate. CONSTITUTION:After an SiO2 film 12 and Al-Si-Cu metallic layer 13 are successively formed on an Si substrate 11, a resist 14 composed of a photosensitive high polymer is applied to the surface of the layer 13. After subjecting the resist 14 to entire-surface exposure and heat treatment, a resist pattern 14a having taper angles is formed by developing the resist 14 after exposing the resist 10 to light by using a mask pattern 15. Then the adhesiveness of the pattern 14a to the metallic layer 13 is improved by evaporating the moisture from the resist and hardening the resist by heat treatment. Thereafter, a metallic wiring pattern 13a having taper angles is formed by performing anisotropic reactive ion etching on the layer 13 with a mixed gas of Cl2 and BCl3 by using the pattern 14a as a mask. Finally, the unnecessary pattern 14a is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring pattern in a semiconductor device, and more particularly to a method for forming a metal wiring pattern in a semiconductor device in which a metal layer is formed by etching a metal layer in a semiconductor integrated circuit manufacturing process. Regarding

[0002]

2. Description of the Related Art Conventionally, in the manufacture of a semiconductor device (semiconductor integrated circuit), a photolithography technique for transferring a mask pattern onto a resist and a patterned resist for forming a metal wiring pattern on a semiconductor substrate. A process combined with an etching technique for processing the metal layer using the as a mask is adopted.

A general photolithography and etching process for forming a metal wiring pattern will be described with reference to FIG. First, a metal layer 43 is formed on the Si substrate 41 or the insulating film 42 (FIG. 5A), and then a resist 44 made of a photosensitive polymer is applied, and then prebaking is performed so that the resist 44 is contained. The organic solvent generated is removed (FIG. 5 (b)). Next, a mask pattern (not shown) is transferred onto the resist 44 by exposure, and then the resist 44 is developed to form a pattern corresponding to the mask pattern on the resist 44. Next, post-baking is performed to remove water contained in the resist 44 to cure the resist 44 and enhance the adhesiveness with the metal layer 43 (FIG. 5C). Further, the metal layer 43 is etched using the resist 44 as a mask to form a metal wiring pattern 43a (FIG. 5D). Next, the unnecessary resist 44 is melted and removed (FIG. 5).
(E)). As described above, the general photolithography and etching process is composed of the five main processes as shown in FIGS.

The cross-sectional shape of the metal wiring pattern 43a formed by the above-mentioned photolithography and etching process is rectangular. However, due to the application of the device, a cross-sectional shape with a taper angle is formed after the metal layer 43 is etched. It may be desirable to obtain. For example, by making the cross-sectional shape of the metal wiring pattern 43a tapered,
This is a case where the burying property of the upper insulating film is improved, the stress of the insulating film is relieved, and the conduction failure of the metal wiring pattern formed on the upper layer of the insulating film is prevented. As a method of obtaining a metal wiring pattern having such a taper angle, there is a method of performing dry etching while depositing a polymer on the sidewall of the resist pattern.

A method of forming a metal wiring pattern by dry etching using a polymer film will be described with reference to FIG. First, the metal layer 53 is formed on the Si substrate 51 or the insulating film 52, and then the resist 54 is applied. After that, prebaking is performed to remove the organic solvent contained in the resist 54, and a mask pattern (not shown) is transferred onto the resist 54 by exposure and then developed to form a pattern of the resist 54 on the metal layer 53. Form (Fig. 6
(A)). Further, using the resist 54 as a mask, CHC
Dry etching having anisotropy is performed using a mixed gas system of l ₃ and Cl ₂ . In this case, at the same time when the metal layer 53 is etched, a polymer is deposited on the pattern side wall of the resist 54 to form a polymer film 56 (FIG. 6B).
(C)), metal wiring pattern 53a having a taper angle
Is formed. Next, the unnecessary resist 54 is melted and removed (FIG. 6D).

[0006]

In the case of the dry etching method using the polymer film 56, the polymer film 56 formed on the side wall of the resist 54 is used to form a taper angle on the side wall of the metal wiring pattern 53a. Therefore, resist 5
4 and the bottom line width B of the metal wiring pattern 53a formed by etching (B-
A) (hereinafter, (B-A) is referred to as a line width conversion difference) is large, and as the number of etching-processed sheets increases, the etching rate decreases due to the influence of the polymerized film 56. Therefore, there is a problem that the controllability and reproducibility of the line width are poor.

The present invention has been made in view of the above problems, and is capable of forming a metal wiring pattern having a taper angle which is excellent in controllability and reproducibility of line width, and a metal wiring pattern of a semiconductor device. It is intended to provide a forming method.

[0008]

In order to solve the above-mentioned problems, a method for forming a metal wiring pattern of a semiconductor device according to the present invention comprises a step of sequentially forming a SiO ₂ film and a metal layer on a substrate, and then forming the metal layer on the metal layer. After a resist is applied, the resist is subjected to overall exposure and mask exposure, developed to form a resist pattern, and then reactive ion etching having anisotropy is performed on the metal layer by using a mixed gas of Cl ₂ and BCl _3. It is characterized in that it is processed.

Further, in the above-described method for forming a metal wiring pattern of a semiconductor device, a PEB (Post Exposure Bake) process is performed after the whole surface exposure or the mask exposure.

[0010]

According to the above-described method for forming a metal wiring pattern of a semiconductor device, in the photolithography step, when a resist-coated wafer is subjected to exposure / development processing to form a resist pattern, whole surface exposure and mask exposure are combined. After that, development processing is performed.

Since the inhibitor (development inhibitor) in the resist is decomposed by exposing the resist, if the intensity of the whole surface exposure is adjusted, only the surface of the resist is exposed strongly and the inhibitor concentration becomes small, so that It becomes possible. Further, as the depth becomes deeper, the intensity of the exposed light becomes weaker, the inhibitor concentration becomes higher, and the developing becomes impossible. That is, the inhibitor concentration after the whole surface exposure shows a concentration distribution that increases as the depth from the surface of the resist increases.

When mask exposure is performed using a mask pattern from this state, the resist is irradiated with light only from the opening in the mask exposure, and the light intensity distribution in the opening can be dissolved by development as it is closer to the surface. It will be in a state in which the large state is greatly expanded. When development is performed thereafter, a resist pattern having a taper angle is formed.

After that, by performing anisotropic reactive ion etching treatment using a mixed gas of Cl ₂ and BCl ₃ , the metal layer is etched at the same time as the resist is etched, and the shape and line of the resist pattern are formed. The width is accurately transferred to the metal layer. As a result, a metal wiring pattern having a taper angle is formed. Since the polymerized film is not used in this etching process, the conversion difference of the line width becomes small, and the controllability and reproducibility of the line width can be improved.

In the metal wiring pattern forming method for a semiconductor device described above, when the exposure wavelength is a single wavelength, λ / 4n is perpendicular to the base film due to the influence of standing waves.
A wavy pattern may appear on the side wall of the resist due to the change of the light intensity in the cycle of (λ; wavelength, n: refractive index) (FIG. 1A). However, the wavy pattern is also smoothed by performing PEB processing after the whole surface exposure or the mask exposure (FIG. 1B), and the influence of the standing wave can be mitigated. Further, the inhibitor concentration distribution in the resist after the whole surface exposure and the mask exposure becomes gentle, and the line width can be easily controlled. For this reason,
A resist pattern having a smooth taper angle will be formed.

When the PEB process is performed before the mask exposure, the light in the mask exposure is likely to enter, so that the mask exposure amount can be estimated to be small, and the light standing during the mask exposure can be fixed. The influence of waves will be mitigated, and the controllability and reproducibility of the line width will be further improved.

[0016]

EXAMPLES AND COMPARATIVE EXAMPLES Examples and comparative examples of a method for forming a metal wiring pattern of a semiconductor device according to the present invention will be described below with reference to the drawings. 2A to 2G are schematic cross-sectional views showing each step for explaining the metal wiring pattern forming method of the semiconductor device according to the example.

First, the SiO ₂ film 12 is formed on the Si substrate 11, then the metal layer 13 made of Al--Si--Cu is formed on the SiO ₂ film 12 (FIG. 2A), and then the metal layer. A resist 14 made of a photosensitive polymer is applied onto 13. After that, prebaking is performed to remove the organic solvent contained in the resist 14 (FIG. 2B). Next, the entire surface of the resist 14 is exposed ((FIG. 2C)), followed by PEB treatment (heat treatment), and then mask exposure using a stepper using the mask pattern 15 (FIG. 2C).
(D)). Next, the resist 14 is developed to have a taper angle corresponding to the mask pattern 15.
a is formed (FIG. 2E). After that, post-baking is performed to remove water contained in the resist 14 to cure the resist pattern 14a and enhance the adhesiveness with the metal layer 13. Further, using the resist pattern 14a having the taper angle as a mask, the metal layer 13 is subjected to anisotropic reactive ion etching treatment using a mixed gas of Cl ₂ and BCl ₃ to form the metal wiring pattern 13a having the taper angle. Formed (FIG. 2 (f)). After that, the resist pattern 14a which is no longer needed is removed (see FIG. 2).
(G)).

For the above etching treatment, E shown in FIG. 3 is used.
Using a CR plasma processing apparatus, using a mixed gas of Cl ₂ (72 sccm) and BCl ₃ (101 sccm), microwave: 1000 W, pressure: 5 mTorr, RF: 200 W
Was performed under the conditions of

Reference numeral 21 in the drawing denotes a plasma generation chamber,
The peripheral wall of the plasma generation chamber 21 is doubled. A cooling chamber 25 for allowing cooling water to flow therethrough is provided, and the microwave introduction window 21 is provided at a substantially central portion of the upper wall of the plasma generation chamber 21.
a is formed, a microwave introduction quartz plate 21b is disposed above the microwave introduction window 21a, and a microwave waveguide 22 is connected above the microwave introduction quartz plate 21b. A plasma extraction window 21d is formed in the lower part of the plasma generation chamber 21, and an etching chamber 23 is provided so as to face the plasma extraction window 21d. Below the etching chamber 23 is the etching chamber 2.
Turbo molecular pump 3 for setting the pressure inside 3
2. The rotary pump 33 is connected. further,
Exciting coils 24 are arranged concentrically with the plasma generation chamber 21 and the microwave waveguide 22 connected to the plasma generation chamber 21 so as to surround the plasma generation chamber 21 and one end thereof. On the other hand, in the etching chamber 23, a sample table 27 is arranged at a position facing the plasma extraction window 21d, and a sample 28 such as a wafer is placed on the sample table 27. Sample table 2
7 has an electrode plate 34 embedded therein.
Is connected to an RF power source 37 via an RF matching box 36 by an RF application line 35. The sample cooling mechanism 26 is arranged so as to surround the RF application line 35 in the sample table 27.
A sub-coil 27a is arranged so as to surround 6 further. Further, in the figure, 21c indicates a reaction gas introduction line communicating with the plasma generation chamber 21, 23b indicates an etching chamber purge line communicating with the etching chamber 23, and 25a and 25b indicate cooling water supply pipes and discharges. 26a and 26b are pipes for supplying cooling water for the sample table,
The discharge pipe is shown. Further, a cassette chamber 29 is provided on one side of the etching chamber 23.
A wafer cassette 29a, on which the sample 28 is placed, is arranged in the. The inside of the cassette chamber 29 is the etching chamber 23.
A turbo molecular pump 30 and a rotary pump 31 are connected to the cassette chamber 29 in order to maintain the same pressure as the inside.

In order to perform the etching process on the sample 28 placed on the sample table 27 using the ECR plasma processing apparatus having the above-described structure, first, the turbo molecular pump 32 is placed in the plasma generation chamber 21 and the etching chamber 23. Then, the rotary pump 33 is operated to set a predetermined degree of vacuum, and then the RF power source 37 is applied to the electrode plate 34 in the sample stand 27, an electric current is passed through the auxiliary coil 27a, and cooling water is supplied into the sample cooling mechanism 26. The cooling water also flows through the cooling chamber 25. Then, a mixed gas of Cl ₂ and BCl ₃ is supplied as a reaction gas into the plasma generation chamber 21 through the reaction gas introduction line 21c. Then, a current is passed through the exciting coil 24 to form a magnetic field, a microwave is introduced into the plasma generation chamber 21, and the gas is resonantly excited by using the plasma generation chamber 21 as a cavity resonator to generate plasma. The generated plasma is projected around the sample 28 in the etching chamber 23 by a divergent magnetic field whose magnetic flux density decreases toward the etching chamber 23 side formed by the excitation coil 24, and the surface of the sample 28 in the etching chamber 23 is etched. Is applied. The etched sample 28 is carried into the cassette chamber 29 and stored in the wafer cassette 29a.
The unprocessed sample 28 is carried to the sample table 27.

FIG. 4 is a schematic sectional view showing a metal wiring pattern 13a formed by the method for forming a metal wiring pattern of a semiconductor device according to the above-mentioned embodiment.

The formation conditions at this time are as follows: PFX15C-D2 (manufactured by Sumitomo Chemical Co., Ltd.) is used as the resist 13.
Prebaking was performed at 100 ° C. for 120 seconds. After exposing the entire surface without a mask under the exposure condition of an exposure amount of 105 mJ / cm ² , PEB treatment was performed at 120 ° C. for 120 seconds. Then, the mask exposure is performed at an exposure amount of 155 mJ / cm.
² and then developed at 22 ° C for 65 seconds,
Post-baking was performed at 120 ° C. for 120 seconds.

As is clear from FIG. 4, the surface of the formed metal wiring pattern 13a has a smooth taper angle.

Table 1 below shows a metal wiring pattern 13a formed by the method for forming a metal wiring pattern of a semiconductor device according to the embodiment, and a conventional example in which a taper angle is formed by dry etching using a polymer film as a comparative example. This is a comparison with the metal wiring pattern 53a.

[0025]

[Table 1]

As is apparent from Table 1, the comparative example has a large line width conversion difference of 0.3 μm to 0.5 μm and the controllability and reproducibility of the line width are poor, but the example has a line width. The conversion difference is as small as 0.01 μm, and the line width controllability and reproducibility are also improved.

As described above, in the method for forming a metal wiring pattern of a semiconductor device according to the embodiment, the resist pattern 14a is tapered with a smooth surface by performing overall exposure and mask exposure in the photolithography process. Leave the corners. After that, reactive ion etching having anisotropy is performed, so that the conversion difference in line width can be reduced. Further, since the resist 14 is strongly exposed only at the surface portion and becomes weaker as it becomes deeper by adjusting the exposure amount at the time of the whole surface exposure, the inhibitor concentration after the whole surface exposure becomes deeper from the surface of the resist 14. It shows a concentration distribution of increasing, and as the inhibitor concentration increases, dissolution by development becomes impossible. By performing PEB processing in this state,
The distribution of the inhibitor concentration in the resist 14 can be made smooth. Further, the light transmittance in the resist 14 also changes, and the light in the mask exposure is likely to enter, so that the mask exposure amount can be underestimated, and further, the influence of the standing wave of the light in the mask exposure is also exerted. Can be relaxed. Therefore, the pattern controllability during etching can be improved, and the metal wiring pattern 13a having a taper angle excellent in the controllability and reproducibility of the line width can be formed.

The PEB process may be performed after the whole surface exposure and the mask exposure, but a smoother tapered shape can be obtained by performing the PEB process after the whole surface exposure.

In the method of forming a metal wiring pattern of a semiconductor device according to the above-mentioned embodiment, PE is exposed after the whole surface is exposed.
Although the B process is performed, the PEB process may not be particularly performed in the metal wiring pattern forming method for a semiconductor device according to another embodiment. In this case, by performing the whole surface exposure and the mask exposure, it is possible to form the metal wiring pattern 13a having a taper angle excellent in the controllability and reproducibility of the line width.

In the above embodiment, the metal layer 13 is made of Al.
Although description has been made by taking the case of -Si-Cu as an example, the other metal layer 13 is Al-Cu, Al-Si, or Al-.
The present invention can be similarly applied to the case of Cu-Ti or the like.

As described above, in the method for forming a metal wiring pattern of a semiconductor device according to the present invention, the entire surface exposure and the mask exposure are performed, and the mixture gas having Cl ₂ and BCl ₃ has anisotropy. By performing the reactive ion etching, it is possible to form the metal wiring pattern 13a having a taper angle excellent in controllability of line width and reproducibility.

[0032]

As described above in detail, in the method for forming a metal wiring pattern of a semiconductor device according to the present invention, the exposure of the entire surface and the exposure of the mask are combined in the photolithography process, so that the resist pattern has a taper angle. Can be attached. Also, Cl ₂ and B
Since the resist pattern is transferred to the metal layer by performing anisotropic reactive ion etching using a mixed gas of Cl ₃ , the line width conversion difference can be reduced. Therefore, it is possible to form a metal wiring pattern having a taper angle which is excellent in controllability and reproducibility of line width.

Therefore, it is possible to improve the burying property of the insulating film on the metal wiring pattern, relieve the stress of the insulating film, and prevent the conduction failure of the metal wiring pattern formed on the upper layer of the insulating film. it can.

In the metal wiring pattern forming method for a semiconductor device described above, when PEB processing is performed after the whole surface exposure or the mask exposure, the controllability of the line width can be further improved, so that the fineness can be further reduced. It becomes easy to form a simple metal wiring pattern.

[Brief description of drawings]

FIG. 1A is a schematic sectional view showing a resist pattern without PEB treatment, and FIG. 1B is a schematic sectional view showing a resist pattern with PEB treatment.

2A to 2G are schematic cross-sectional views showing an embodiment of a method for forming a metal wiring pattern of a semiconductor device according to the present invention in the order of each step.

FIG. 3 is an EC used in an etching process in the method for forming a metal wiring pattern of a semiconductor device according to the present invention.
It is a schematic sectional drawing which showed the R plasma processing apparatus.

FIG. 4 is a schematic cross-sectional view showing a metal wiring pattern formed by a method for forming a metal wiring pattern of a semiconductor device according to an example.

5A to 5E are schematic cross-sectional views showing a conventional metal wiring pattern forming method in the order of steps.

6A to 6D are schematic cross-sectional views showing another conventional method of forming a metal wiring pattern in the order of steps.

[Explanation of symbols]

11 substrate (Si substrate) 12 SiO ₂ film 13 metal layer 13a metal wiring pattern 14 resist 14a resist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 21/3205

Claims (2)

[Claims] 1. An SiO ₂ film and a metal layer are sequentially formed on a substrate, a resist is applied on the metal layer, and the resist is subjected to overall exposure and mask exposure, followed by development to form a resist pattern. A method for forming a metal wiring pattern of a semiconductor device, wherein the metal layer is subjected to anisotropic reactive ion etching treatment using a mixed gas of Cl ₂ and BCl ₃ . 2. PEB after whole surface exposure or mask exposure
The method for forming a metal wiring pattern of a semiconductor device according to claim 1, wherein a (Post Exposure Bake) process is performed.