KR20020056705A - Method for manufacturing the thin film transistor liquid crystal display device - Google Patents
Method for manufacturing the thin film transistor liquid crystal display device Download PDFInfo
- Publication number
- KR20020056705A KR20020056705A KR1020000086110A KR20000086110A KR20020056705A KR 20020056705 A KR20020056705 A KR 20020056705A KR 1020000086110 A KR1020000086110 A KR 1020000086110A KR 20000086110 A KR20000086110 A KR 20000086110A KR 20020056705 A KR20020056705 A KR 20020056705A
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- film transistor
- liquid crystal
- crystal display
- mask
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 22
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000010408 film Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000002161 passivation Methods 0.000 abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- DYRBFMPPJATHRF-UHFFFAOYSA-N chromium silicon Chemical compound [Si].[Cr] DYRBFMPPJATHRF-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 150000003377 silicon compounds Chemical class 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- GALOTNBSUVEISR-UHFFFAOYSA-N molybdenum;silicon Chemical compound [Mo]#[Si] GALOTNBSUVEISR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005575 poly(amic acid) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
Landscapes
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
Description
본 발명은 박막트랜지스터 액정표시장치에 관한 것으로, 보다 상세하게는 그레이톤(Graytone)을 사용하여 2 마스크 공정을 이용한 박막트랜지스터 액정표시장치의 제조방법에 관한 것이다.The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to a method of manufacturing a thin film transistor liquid crystal display device using a two-mask process using graytone.
일반적으로 액정표시장치에 있어서, 액티브매트릭스형 액정표시장치는 고속응답을 갖고 많은 수의 화소를 갖는다. 이에 따라, 디스플레이 화면의 고화질화,대형화 및 컬러화면 등을 실현하는 특성을 지니며 휴대형 텔레비전, 노트북 컴퓨터, 개인용 컴퓨터 및 자동차 항법장치등에 이용된다.In general, in a liquid crystal display device, an active matrix liquid crystal display device has a high speed response and has a large number of pixels. As a result, the display screen has high quality, large size, color screen, and the like, and is used in portable televisions, notebook computers, personal computers, automobile navigation systems, and the like.
이러한 액티브매트릭스형 액정표시장치에서는 화소전극을 선택적으로 온/오프시키기 위하여 게이트라인과 데이터라인이 교차하는 부위에 다이오드 또는 박막트랜지스터와 같은 스위칭소자가 배치설계된다.In such an active matrix type liquid crystal display device, a switching element such as a diode or a thin film transistor is disposed at a portion where a gate line and a data line cross each other to selectively turn on / off a pixel electrode.
이러한 박막트랜지스터를 포함하는 종래의 액정표시장치의 제조방법은 먼저, 도면에는 도시하지 않았지만 절연기판상에 게이트전극 및 스토리지전극용 금속층을 소정 두께로 증착한 후, 제 1 마스크공정을 통하여 상기 금속막을 소정부분 패터닝하여 게이트전극 및 스토리지전극을 형성한다.In the conventional method of manufacturing a liquid crystal display including the thin film transistor, a metal layer for a gate electrode and a storage electrode is deposited to a predetermined thickness on an insulating substrate, although not shown in the drawing, and then the metal film is formed through a first mask process. A predetermined portion is patterned to form a gate electrode and a storage electrode.
이어서, 도면에는 도시하지 않았지만, 상기 게이트전극 및 스토리지전극이 형성된 절연기판 상부에 게이트 절연막을 소정두께로 증착한 다음, 박막트랜지스터의 채널역할을 하는 비정질실리콘층과 도핑된 반도체층을 순차적으로 증착한다. 그 후, 제 2 마스크공정으로 상기 비정질실리콘층과 도핑된 반도체층을 박막트랜지스터 예정영역에 존재하도록 패터닝한다.Subsequently, although not shown in the drawing, a gate insulating film is deposited on the insulating substrate on which the gate electrode and the storage electrode are formed to a predetermined thickness, and then an amorphous silicon layer and a doped semiconductor layer, which serve as a channel of the thin film transistor, are sequentially deposited. . Thereafter, the amorphous silicon layer and the doped semiconductor layer are patterned to exist in the planar region of the thin film transistor by a second mask process.
그 다음, 도면에는 도시하지 않았지만, 절연기판 결과물 상부에 소오스 및 드레인용 금속막을 증착한 후, 상기 금속막을 비정질실리콘층 양측에 존재하도록 제 3 마스크공정을 통하여 소오스 및 드레인전극을 형성한다.Next, although not shown in the drawings, a source and drain metal film is deposited on the resultant insulating substrate, and then the source and drain electrodes are formed through a third mask process so that the metal film is present on both sides of the amorphous silicon layer.
이어서, 도면에는 도시하지 않았지만, 상기 소오스 및 드레인전극이 형성된 절연기판 상부에 보호막을 형성한 후, 소오스전극의 소정부분이 노출되도록 제 4 마스크공정을 통하여 상기 보호막을 식각하여 비아홀(Via hole)을 형성한다.Subsequently, although not shown in the drawing, after forming a passivation layer on the insulating substrate on which the source and drain electrodes are formed, the passivation layer is etched through a fourth mask process so that a predetermined portion of the source electrode is exposed to form a via hole. Form.
이어서, 도면에는 도시하지 않았지만, 상기 비아홀을 통하여 노출된 소오스전극과 콘택트되도록 보호막 상부에 ITO(Indium Tin Oxide)막을 증착한 후, 제 5 마스크공정을 통하여 상기 ITO막을 소정부분 식각하여 화소전극을 형성한다.Subsequently, although not shown in the drawing, an ITO (Indium Tin Oxide) film is deposited on the passivation layer so as to contact the source electrode exposed through the via hole, and the pixel electrode is formed by etching a predetermined portion of the ITO film through a fifth mask process. do.
그러나, 상기한 종래의 박막트랜지스터 액정표시장치의 하부기판을 형성하느데는 상술한 바와 같이 적어도 5번의 마스크공정이 요구된다.However, as described above, at least five mask processes are required to form the lower substrate of the conventional thin film transistor liquid crystal display.
이때, 상기 식각공정이라 함은 공지된 바와 같이 포토리소그라피공정으로서, 그 자체 공정만으로도 레지스트도포공정, 노광공정, 현상공정, 식각공정 및 레지스트 제거공정을 포함한다. 이에 따라, 한 번의 마스크공정을 진행하는데에도 장시간이 소요된다.In this case, the etching process is a photolithography process, as is known, and includes a resist coating process, an exposure process, a developing process, an etching process, and a resist removing process only by its own process. As a result, it takes a long time to perform one mask process.
이로 인하여, 적어도 5번의 마스크공정을 포함하는 박막트랜지스터 액정표시장치를 제조하는데 매우 긴 시간이 요구되고, 제조비용의 상승 및 수율저하등의 문제점이 있다.For this reason, a very long time is required to manufacture a thin film transistor liquid crystal display including at least five mask processes, and there are problems such as an increase in manufacturing cost and a decrease in yield.
따라서, 본 발명은 종래기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 마스크공정을 줄여 제조단가를 낮출 수 있는 박막트랜지스터 액정표시장치의 제조방법을 제공함에 있다.Accordingly, the present invention has been made to solve the problems of the prior art, an object of the present invention is to provide a method for manufacturing a thin film transistor liquid crystal display device that can reduce the manufacturing cost by reducing the mask process.
도 1내지 5는 본 발명에 따른 박막트랜지스터 액정표시장치의 제조방법을 설명하기 위한 각 공정별 단면도.1 to 5 are cross-sectional views for each process for explaining a method of manufacturing a thin film transistor liquid crystal display device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11: 유리기판13: 게이트전극11: glass substrate 13: gate electrode
15: 액티브층17: 소오스 및 드레인전극용 금속층15: active layer 17: metal layer for source and drain electrodes
17a: 드레인전극17b: 소오스전극17a: drain electrode 17b: source electrode
19: 보호막19: shield
상기 본 발명의 목적을 달성하기 위한 본 발명에 따른 박막트랜지스터 액정표시장치의 제조방법은, 투명성 절연기판상에 금속막을 증착하고, 제 1 마스크공정으로 상기 금속막을 선택적으로 패터닝하여 게이트전극을 형성하는 단계; 상기 게이트전극이 형성된 상기 투명성 절연기판 전면상에 액티브층, 데이터 및 화소전극용 금속층을 순차적으로 형성하고, 제 2 마스크공정으로 상기 액티브층, 데이터 및 화소전극용 금속층을 패터닝하여 데이터전극과 화소전극을 동시에 형성하는 단계; 상기 데이터전극을 마스크로 하여 액티브층을 선택적으로 제거하는 단계; 및 상기 박막트랜지스터의 전면상에 배향막기능을 갖는 보호막을 형성하는 단계를 포함하여 구성되는 것을 특징으로 한다.A method of manufacturing a thin film transistor liquid crystal display device according to the present invention for achieving the object of the present invention, by depositing a metal film on a transparent insulating substrate, and selectively patterning the metal film in a first mask process to form a gate electrode step; The metal layer for the active layer, the data, and the pixel electrode is sequentially formed on the entire surface of the transparent insulating substrate on which the gate electrode is formed, and the metal layer for the active layer, the data, and the pixel electrode is patterned by a second mask process. Simultaneously forming; Selectively removing the active layer using the data electrode as a mask; And forming a protective film having an alignment film function on the entire surface of the thin film transistor.
이하, 본 발명에 따른 박막트랜지스터 액정표시장치를 첨부한 도면에 의거하여 상세히 설명한다.Hereinafter, a thin film transistor liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1내지 5는 본 발명에 따른 박막트랜지스터 액정표시장치를 설명하기 위한 각 공정별 단면도이다.1 to 5 are cross-sectional views of respective processes for explaining the thin film transistor liquid crystal display according to the present invention.
본 발명에 따른 박막트랜지스터 액정표시장치는, 도 1에 도시된 바와 같이, 먼저 투명성 절연기판, 예를 들어, 유리기판(11)을 준비한 다음 전기전도성이 높은 금속을 이용하여 게이트금속층(도시되어 있지않음)을 스퍼터링방식 등으로 소정의 두께로 증착한다. 그런다음, 상기 형성된 게이트금속층을 원하는 형태의 마스크(도시되지 않음), 본 발명에 있어서의 제 1마스크를 사용하여 일련의 마스크공정을 행하여 게이트전극(13)을 형성한다.(제 1마스크공정)In the thin film transistor liquid crystal display device according to the present invention, as shown in FIG. 1, a transparent insulating substrate, for example, a glass substrate 11 is prepared first, and then a gate metal layer (not illustrated) is formed using a highly conductive metal. Is deposited to a predetermined thickness by sputtering or the like. Then, the formed gate metal layer is subjected to a series of mask processes using a mask of a desired shape (not shown) and the first mask in the present invention to form a gate electrode 13. (First mask process)
그 다음, 도 2에 도시된 바와 같이, 상기 게이트전극(13)이 형성된 유리기판(11) 전면상에 게이트절연막, 반도체층으로 이용되는 비정질실리콘층, 오믹층으로 이용되는 도핑된 비정질실리콘층으로 구성되는 액티브층(15)을 증착하고, 상기 ??티브층(15)상에 소옷스 및 드레인용 금속층(17)을 연속하여 증착한다.Next, as shown in FIG. 2, a gate insulating film, an amorphous silicon layer used as a semiconductor layer, and a doped amorphous silicon layer used as an ohmic layer are formed on the entire surface of the glass substrate 11 on which the gate electrode 13 is formed. The active layer 15 constituted is deposited, and the soot and drain metal layers 17 are successively deposited on the active layer 15.
이때, 상기 소오스 및 드레인전극용 금속층(17)에 있어서, 본 발명의 적용예를 달리하면 소형의 투과형 액정표시장치에 적용되는 ITO 또는 저저항 투명전극과, 대형의 반사형 액정표시장치에 적용되는 알루미늄과 같은 반사형 금속으로 나눌수가 있다.In this case, in the source and drain electrode metal layers 17, different application examples of the present invention may be applied to ITO or low resistance transparent electrodes applied to a small transmissive liquid crystal display device, and to a large reflective liquid crystal display device. It can be divided into reflective metals such as aluminum.
여기서, 전자의 예를 들 때, 즉 상기 소오스 및 드레인(데이터 버스라인)전극용 금속층(17)으로 ITO를 사용하는 경우, 디스플레이의 크기에 따라 데이터라인의 저항으로 데이터신호가 왜곡될 수 있지만 4내지 5인치이하의 디스플레이이면 실제적으로 가능하다.Here, in the case of the former, that is, when ITO is used as the metal layer 17 for the source and drain (data bus line) electrodes, the data signal may be distorted due to the resistance of the data line depending on the size of the display. It is practically possible if the display is less than 5 inches.
또한, 박막트랜지스터의 전기적 특성과 상기 4내지 5인치이하의 디스플레이보다 더 큰 디스플레이를 고려하면, 상기 오믹층으로 이용되는 도핑된 비정질실리콘층을 미세결정체로 형성하거나 또는 규소화합물로 구성하여 ITO 증착을 행하므로써 어느정도 저저항을 달성하면 ITO를 상기 소오스 및 드레인(데이터 버스라인)전극용 금속층으로 적용할 수 있다. 여기서, 상기 규소화합물로는 몰리브덴규소(MoSi), 탄탈륨규소(TaSi), 크롬규소(CrSi) 또는 텅스텐규소(WSi) 화합물등이 그 예이다In addition, considering the electrical characteristics of the thin film transistor and a display larger than the display of 4 to 5 inches or less, ITO deposition is performed by forming a doped amorphous silicon layer used as the ohmic layer as a microcrystal or a silicon compound. In this way, if the resistance to some extent is achieved, ITO can be applied to the metal layer for the source and drain (data busline) electrodes. Here, examples of the silicon compound include molybdenum silicon (MoSi), tantalum silicon (TaSi), chromium silicon (CrSi) or tungsten silicon (WSi) compounds.
이와 달리, 후자의 예처럼, 반사형 액정표시장치의 경우는 ITO 투명전극대신 알루미늄 또는 규소가 수 % 포함되거나 기타 반사형 금속을 사용하여 소오스 및 드레인전극(17)을 형성한다. 이런경우는 배선저항의 제약을 받지 않으므로 중형이상의 디스플레이에서도 상기 기타 반사형금속을 데이터전극으로 사용가능하다.Alternatively, as in the latter example, in the case of the reflective liquid crystal display device, the source and drain electrodes 17 are formed using aluminum or silicon instead of ITO transparent electrodes by several% or other reflective metals. In this case, since the wiring resistance is not limited, the other reflective metal can be used as the data electrode even in a medium size or larger display.
이어서, 도 3에 도시된 바와 같이, 상기 액티브층(15), 소오스 및 드레인전극용 금속층(17)상에 제 2마스크공정을 행한다. 여기서, 소오스(17a) 및 드레인전극(17b)과 화소전극(도시되지 않음)을 동시에 형성하기 위하여 먼저, 패턴 노광시 제 2마스크로서 그레이톤 마스크를 이용한다.(제 2마스크공정)Next, as shown in FIG. 3, a second mask process is performed on the active layer 15, the source and drain electrode metal layers 17. Here, in order to simultaneously form the source 17a, the drain electrode 17b, and the pixel electrode (not shown), a gray tone mask is used as the second mask during pattern exposure. (Second mask process)
즉, 상기 소오스 및 드레인용 금속층(17) 영역을 그레이톤 마스크를 이용하여 부분노광 및 현상을 실시한 후, 소오스 및 드레인용 금속층(17)중 박막트랜지스터 채널부로 예정된 영역을 포함한 일부분을 식각한다. 이때, 상기 그레이톤 마스크로 노광된 소오스 및 드레인영역은 포토레지스트가 적당한 양만큼 잔류하여 후술하는 액티브층(15)의 식각공정시 충분한 커버리지를 갖게한다.That is, after partial exposure and development are performed on the source and drain metal layer 17 using a gray mask, a portion of the source and drain metal layer 17 including a region defined as the thin film transistor channel portion is etched. In this case, the source and drain regions exposed by the gray tone mask may have sufficient coverage during the etching process of the active layer 15, which will be described later, by remaining the photoresist by an appropriate amount.
그 다음, 도 4에 도시된 바와 같이, 상기 일부식각된 소오스 및 드레인전극용 금속층(17)상에 남겨진 포토레지스트를 제거하기 위해 애싱처리하여 소오스 및 드레인전극(17a)(17b)을 형성한 후, 상기 소오스(17a) 및 드레인전극(17b)을 재식각하고, 상기 액티브층(15)내의 오믹층을 제거하여 박막트랜지스터의 채널부를 완성한다Next, as shown in FIG. 4, the source and drain electrodes 17a and 17b are formed by ashing to remove the photoresist remaining on the partially etched source and drain electrode metal layers 17. The channel 17a and the drain electrode 17b are etched again, and the ohmic layer in the active layer 15 is removed to complete the channel portion of the thin film transistor.
이때, 상기 액티브층(15) 식각공정시 게이트패드(Gate pad)부분(도시되지 않음)의 절연막 개방을 위해 상기 액티브층까지 식각한다. 이 경우, 상기 소오스 및 드레인전극용 금속층(17)을 마스크로 사용하므로 별도의 마스크를 필요로 하지 않는다.At this time, during the etching process of the active layer 15, the active layer 15 is etched up to the active layer to open an insulating layer of a gate pad portion (not shown). In this case, since the source and drain electrode metal layers 17 are used as masks, a separate mask is not required.
이어서, 상기 형성된 소오스(17a) 및 드레인전극(17b)상을 포함하여 상기 유리기판(11) 전면상에 보호막(19)을 형성한다. 이때, 상기 보호막(19)의 물질로서 유기계 오버코팅제, 또는 폴리이미드나 폴리아미드산과 같은 배향막을 이용하여 배향막 형성에 필요한 공정단계를 줄인다.Subsequently, the passivation layer 19 is formed on the entire surface of the glass substrate 11 including the formed source 17a and the drain electrode 17b. At this time, by using an organic overcoat agent or an alignment film such as polyimide or polyamic acid as the material of the protective film 19, process steps required for forming the alignment film are reduced.
이상과 같은 그레이톤 마스크를 사용하면 2번의 마스크공정으로 박막트랜지스터 액정표시장치의 하부 어레이기판을 제조할 수 있게 된다.When the gray tone mask as described above is used, the lower array substrate of the thin film transistor liquid crystal display device can be manufactured by two mask processes.
상기한 실시예는 본 발명을 이에 한정하려는 의도는 아니고, 본 발명의 일실시예를 나타내는 것이다. 기타, 본 발명의 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시할 수 있다.The above embodiments are not intended to limit the present invention thereto, but rather represent one embodiment of the present invention. In addition, it can implement in various changes within the range which does not deviate from the summary of this invention.
이상에서 설명한 바와 같이 본 발명에 따른 박막트랜지스터 액정표시장치에 있어서는 다음과 같은 효과가 있다.As described above, the thin film transistor liquid crystal display according to the present invention has the following effects.
종래의 박막트랜지스터 제조기술은 크게 백채널에치(BCE)구조/에치스토퍼(ES)구조에 관계없이 5마스크공정이 주류를 이루고 있지만 본 발명은 이를 2마스크 공정으로 감소시켰다, 이는 박막트랜지스터 액정표시장치 제조에 있어서, 설비투자, 개발비용, 공정시간, 제조수율, 생산성 등을 고려해볼 때 마스크공정의 감소는 상당한 제조단가를 낮출 수 있다.Conventional thin film transistor manufacturing technology is mainly 5 mask process regardless of the back channel etch (BCE) structure / etch stopper (ES) structure, but the present invention reduced it to 2 mask process, which is a thin film transistor liquid crystal display In device manufacturing, the reduction of the mask process can considerably lower the manufacturing cost in consideration of equipment investment, development cost, processing time, manufacturing yield, productivity, and the like.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000086110A KR20020056705A (en) | 2000-12-29 | 2000-12-29 | Method for manufacturing the thin film transistor liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000086110A KR20020056705A (en) | 2000-12-29 | 2000-12-29 | Method for manufacturing the thin film transistor liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20020056705A true KR20020056705A (en) | 2002-07-10 |
Family
ID=27689205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000086110A KR20020056705A (en) | 2000-12-29 | 2000-12-29 | Method for manufacturing the thin film transistor liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20020056705A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100578090B1 (en) * | 2004-10-07 | 2006-05-10 | (주)컴버스테크 | Board having multi-functional structure |
KR100875187B1 (en) * | 2002-11-28 | 2008-12-22 | 엘지디스플레이 주식회사 | LCD display device |
-
2000
- 2000-12-29 KR KR1020000086110A patent/KR20020056705A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100875187B1 (en) * | 2002-11-28 | 2008-12-22 | 엘지디스플레이 주식회사 | LCD display device |
KR100578090B1 (en) * | 2004-10-07 | 2006-05-10 | (주)컴버스테크 | Board having multi-functional structure |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7537977B2 (en) | Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films | |
US9523895B2 (en) | TFT-LCD array substrate and manufacturing method thereof | |
KR100190023B1 (en) | Tft-lcd and fabrication method thereof | |
USRE41632E1 (en) | Liquid crystal display device and method of manufacturing the same | |
US7553711B2 (en) | Method for fabricating a thin film transistor for use with a flat panel display device | |
US7666697B2 (en) | Thin film transistor substrate and method of manufacturing the same | |
JP2002141512A (en) | Patterning method of thin film, tft array substrate using the patterning method, and manufacturing method of the tft array substrate | |
JP2003140189A (en) | Array substrate for liquid crystal display device and its manufacturing method | |
KR100886241B1 (en) | Method Of Fabricating Liquid Crystal Display Device | |
US20040125248A1 (en) | Liquid crystal display and fabrication method thereof | |
JPH11133455A (en) | Production of liquid crystal display device | |
US6461886B1 (en) | Method of manufacturing a semiconductor device | |
KR100325072B1 (en) | Manufacturing method of high opening rate and high transmittance liquid crystal display device | |
KR20010058159A (en) | Method for manufacturing tft-lcd | |
US7439088B2 (en) | Liquid crystal display device and fabricating method thereof | |
KR20070045751A (en) | Mask for photo lithography | |
KR100764273B1 (en) | Method for maunufacturing thin film transistor | |
JP4152396B2 (en) | Method for manufacturing thin film transistor array | |
KR100705616B1 (en) | Method for manufacturing thin film transistor liquid crystal display device | |
KR20020056705A (en) | Method for manufacturing the thin film transistor liquid crystal display device | |
KR100476047B1 (en) | method for manufacturing of FFS mode LCD | |
KR20020071233A (en) | Liquid Crystal Display Device And Method For Fabricating The Same | |
KR100417915B1 (en) | Array Panel for Liquid Crystal Display Device and Method for Fabricating the same | |
KR20040046384A (en) | Liquid Crystal Display and fabrication method of thereof | |
US6842201B2 (en) | Active matrix substrate for a liquid crystal display and method of forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |