JP2574837B2 - Thin film transistor matrix and manufacturing method thereof - Google Patents
Thin film transistor matrix and manufacturing method thereofInfo
- Publication number
- JP2574837B2 JP2574837B2 JP370788A JP370788A JP2574837B2 JP 2574837 B2 JP2574837 B2 JP 2574837B2 JP 370788 A JP370788 A JP 370788A JP 370788 A JP370788 A JP 370788A JP 2574837 B2 JP2574837 B2 JP 2574837B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- electrode
- gate
- transparent conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 78
- 239000011159 matrix material Substances 0.000 title claims description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000010408 film Substances 0.000 claims description 182
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 28
- 238000002844 melting Methods 0.000 claims description 26
- 230000008018 melting Effects 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 10
- 239000003870 refractory metal Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 230000003068 static effect Effects 0.000 claims 1
- 229910052723 transition metal Inorganic materials 0.000 claims 1
- 150000003624 transition metals Chemical class 0.000 claims 1
- 238000001259 photo etching Methods 0.000 description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000519695 Ilex integra Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- LFYJSSARVMHQJB-QIXNEVBVSA-N bakuchiol Chemical compound CC(C)=CCC[C@@](C)(C=C)\C=C\C1=CC=C(O)C=C1 LFYJSSARVMHQJB-QIXNEVBVSA-N 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、薄膜トランジスタマトリクスに係り、特に
液晶等を用いた平面ディスプレイに好適な薄膜トランジ
スタマトリクスとその製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor matrix, and more particularly, to a thin film transistor matrix suitable for a flat panel display using liquid crystal and the like, and a method for manufacturing the same.
非晶質シリコン、CdSe等の半導体薄膜を用いた薄膜ト
ランジスタは、アケティブマトリクス型の多素子表示装
置のスイッチング素子として注目されている。2. Description of the Related Art A thin film transistor using a semiconductor thin film such as amorphous silicon or CdSe has been attracting attention as a switching element of an AK matrix multi-element display device.
第４図は従来の薄膜トランジスタマトリクスに用いら
れている薄膜トランジスタの断面構造の例である。すな
わち、絶縁性基板１上にゲート電極２、ゲート絶縁膜
３、半導体膜４、ドレイン電極５、ソース電極６が順次
積層されている。ソース電極６は液晶セルに対する一方
の電極となる画素電極７と接続される。そして、ゲート
電極２は走査線８（ゲート線とも呼ぶ）に、ドレイン電
極は信号線９（ドレイン線とも呼ぶ）に接続され、薄膜
トランジスタマトリクスが構成される。FIG. 4 shows an example of a sectional structure of a thin film transistor used in a conventional thin film transistor matrix. That is, the gate electrode 2, the gate insulating film 3, the semiconductor film 4, the drain electrode 5, and the source electrode 6 are sequentially laminated on the insulating substrate 1. The source electrode 6 is connected to a pixel electrode 7 which is one electrode for the liquid crystal cell. The gate electrode 2 is connected to a scanning line 8 (also called a gate line), and the drain electrode is connected to a signal line 9 (also called a drain line) to form a thin film transistor matrix.
現在、上記薄膜トランジスタマトリクス製造プロセス
における課題は、歩留り向上とホトエッチング工程数削
減による製造コスト低減と配線抵抗低減である。信号線
と走査線の断線防止、配線抵抗低減に対しては第５図に
示すように選択エッチングの可能な金属膜による２層配
線81と82,91と92（たとえば、CrとMoやCrとAl）が提案
されている。これに関するものとしては、たとえば特開
昭61−93488が挙げられる。しかし、上記効果を上げる
ためには、ホトエッチング工程数が増大してしまう。一
方、ホトエッチング工程数削減のためには、第６図に示
すようなプロセスが特開昭61−276374で提案されてい
る。この場合には、信号線や走査線の歩留り低下が考慮
されていない。また、配線の低抵抗化も基板サイズが大
きくなると不十分である。At present, the problems in the above-described thin film transistor matrix manufacturing process are reduction in manufacturing cost and wiring resistance by improving the yield and reducing the number of photoetching steps. In order to prevent disconnection of signal lines and scanning lines and to reduce wiring resistance, as shown in FIG. 5, two-layer wirings 81, 82, 91 and 92 (for example, Cr and Mo or Cr and Al) has been proposed. For example, Japanese Patent Application Laid-Open No. 61-93488 relates to this. However, in order to enhance the above effects, the number of photoetching steps increases. On the other hand, in order to reduce the number of photoetching steps, a process as shown in FIG. 6 has been proposed in Japanese Patent Application Laid-Open No. 61-276374. In this case, the reduction in the yield of signal lines and scanning lines is not considered. Further, the reduction in the resistance of the wiring is insufficient when the substrate size is increased.
上記従来技術は、製造歩留り向上とホトエッチング工
程数削減の双方に対する配慮がされておらず、製造コス
トの低い薄膜トランジスタマトリクスを得られないとい
う課題があった。The prior art described above has a problem in that neither consideration is given to improving the production yield and reducing the number of photoetching steps, and a thin-film transistor matrix having a low production cost cannot be obtained.
本発明の目的は、製造時のホトエッチング工程数が少
なく、製造歩留りが高く、配線抵抗も低い薄膜トランジ
スタマトリクスと製造プロセスを提供することにある。An object of the present invention is to provide a thin film transistor matrix and a manufacturing process in which the number of photo-etching steps during manufacturing is small, the manufacturing yield is high, and the wiring resistance is low.
本発明における薄膜トランジスタマトリクスは、基板
と、該基板上にゲート電極と、前記ゲート電極上に形成
したゲート絶縁膜、半導体膜と、前記半導体薄膜上に設
けたドレイン電極とソース電極とから少なくともなる薄
膜トランジスタをスイッチング素子としている。The thin film transistor matrix according to the present invention includes a substrate, a gate electrode on the substrate, a gate insulating film formed on the gate electrode, a semiconductor film, and a thin film transistor including at least a drain electrode and a source electrode provided on the semiconductor thin film. Is a switching element.
上記目的は、走査線を少なくとも３種類の導電膜で構
成することにより達成される。特に、走査線を基板側か
ら、少なくとも透明導電膜、透明導電膜をエッチングし
にくい薬液によりエッチングできる高融点金属、Alを主
成分とする金属膜を順次積層した構成にすると効果的で
ある。The above object is achieved by forming a scanning line with at least three types of conductive films. In particular, it is effective to form a structure in which at least a transparent conductive film, a high-melting-point metal that can be etched with a chemical solution that is difficult to etch the transparent conductive film, and a metal film containing Al as a main component are sequentially stacked on the scanning line from the substrate side.
具体的には以下の通りである。 Specifically, it is as follows.
基板と、該基板上に形成したゲート電極と、該ゲート
電極上に形成したゲート絶縁膜と、該ゲート絶縁膜上に
形成した半導体薄膜と、該半導体薄膜上に形成したドレ
イン電極およびソース電極とから成る薄膜トランジスタ
マトリクスにおいて、該ゲート電極と接続したゲート線
が、透明導電膜と、該透明導電膜上に形成された高融点
金属膜と、該高融点金属膜上に形成された低抵抗金属膜
とからなる薄膜トランジスタマトリクスとしている。A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, a drain electrode and a source electrode formed on the semiconductor thin film, A thin film transistor matrix comprising: a gate line connected to the gate electrode; a transparent conductive film; a high melting point metal film formed on the transparent conductive film; and a low resistance metal film formed on the high melting point metal film. And a thin film transistor matrix composed of
さらには、基板と、該基板上に形成したゲート電極
と、該ゲート電極上に形成したゲート絶縁膜と、該ゲー
ト絶縁膜上に形成した半導体薄膜と、該半導体薄膜上に
形成したドレイン電極およびソース電極とから成る薄膜
トランジスタマトリクスにおいて、該ゲート電極が、透
明導電膜と、該透明導電膜上に形成された高融点金属膜
とからなり、 該ゲート電極と接続したゲート線が、該透明導電膜
と、該透明導電膜上に形成された該高融点金属膜と、該
高融点金属膜上に形成された低抵抗金属膜とからなる薄
膜トランジスタタマトリクスとすることが好ましい。Further, a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, a drain electrode formed on the semiconductor thin film, In a thin film transistor matrix including a source electrode, the gate electrode is formed of a transparent conductive film and a refractory metal film formed on the transparent conductive film, and a gate line connected to the gate electrode is formed of the transparent conductive film. And a thin film transistor matrix including the high melting point metal film formed on the transparent conductive film and the low resistance metal film formed on the high melting point metal film.
さらには、基板と、該基板上に形成したゲート電極
と、該ゲート電極上に形成したゲート絶縁膜と、該ゲー
ト絶縁膜上に形成した半導体薄膜と、該半導体薄膜上に
形成したドレイン電極およびソース電極とから成る薄膜
トランジスタマトリクスにおいて、該ソース電極と接続
した画素電極が、透明導電膜からなり、該ゲート電極
が、該透明導電膜と、該透明導電膜上に形成された高融
点金属膜とからなり、該ゲート電極と接続したゲート線
が、該透明導電膜と、該透明導電膜上に形成された該高
融点金属膜と、該高融点金属膜上に形成された低抵抗金
属膜とからなる薄膜トランジスタマトリクスとすること
が好ましい。Further, a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, a drain electrode formed on the semiconductor thin film, In a thin film transistor matrix including a source electrode, a pixel electrode connected to the source electrode is formed of a transparent conductive film, the gate electrode is formed of the transparent conductive film, and a high melting point metal film formed on the transparent conductive film. A gate line connected to the gate electrode, the transparent conductive film, the high melting point metal film formed on the transparent conductive film, and a low resistance metal film formed on the high melting point metal film. Preferably, the thin film transistor matrix is made of
一方、その製造方法としては以下の通りである。 On the other hand, the manufacturing method is as follows.
基板上に形成したゲート電極と、該ゲート電極上に形
成したゲート絶縁膜と、該ゲート絶縁膜上に形成した半
導体薄膜と、該半導体薄膜上に形成したドレイン電極お
よびソース電極、該ソース電極と接続した画素電極と、
該ゲート電極と接続したゲート線とを含む薄膜トランジ
スタマトリクスの製造方法であって、該基板に透明導電
膜、高融点金属膜および低抵抗金属膜を順次成膜し、該
低抵抗金属膜をエッチング加工して該ゲート線の一部を
形成する第一のエッチング工程と、該高融点金属膜をエ
ッチング加工して該ゲート線の一部および該ゲート電極
の一部を形成する第二のエッチング工程と、該透明導電
膜をエッチング加工して該表示電極、該ゲート電極およ
び該ゲート線を形成する第三のエッチング工程とを含む
ことことで薄膜トラジスタマトリクスの製造することが
好ましい。A gate electrode formed over the substrate, a gate insulating film formed over the gate electrode, a semiconductor thin film formed over the gate insulating film, a drain electrode and a source electrode formed over the semiconductor thin film, A connected pixel electrode;
A method for manufacturing a thin film transistor matrix including a gate line connected to a gate electrode, wherein a transparent conductive film, a high melting point metal film, and a low resistance metal film are sequentially formed on the substrate, and the low resistance metal film is etched. A first etching step of forming a part of the gate line and a second etching step of etching the refractory metal film to form a part of the gate line and a part of the gate electrode. It is preferable to manufacture a thin film transistor matrix by including a third etching step of etching the transparent conductive film to form the display electrode, the gate electrode, and the gate line.
さらには、基板上に形成したゲート電極と、該ゲート
電極上に形成したゲート絶縁膜と、該ゲート絶縁膜上に
形成した半導体薄膜と、該半導体薄膜上に形成したドレ
イン電極およびソース電極と、該ゲート電極と接続した
ゲート線とを含む薄膜トランジスタマトリクスの製造方
法であって、該基板に透明導電膜、高融点金属膜および
低抵抗金属膜を順次成膜し、該低抵抗金属膜をエッチン
グ加工して該ゲート線の一部を形成する第一のエッチン
グ工程と、該高融点金属膜をエッチング加工して該ゲー
ト線の一部および該ゲート電極の一部を形成する第二の
エッチング工程と、該透明導電膜をエッチング加工して
該ゲート電極および該ゲート線を形成する第三のエッチ
ング工程とを含むことを特徴とする薄膜トランジスタマ
トリクスを製造することが好ましい。Further, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, a drain electrode and a source electrode formed on the semiconductor thin film, A method for manufacturing a thin film transistor matrix including a gate line connected to a gate electrode, wherein a transparent conductive film, a high melting point metal film, and a low resistance metal film are sequentially formed on the substrate, and the low resistance metal film is etched. A first etching step of forming a part of the gate line and a second etching step of etching the refractory metal film to form a part of the gate line and a part of the gate electrode. A third etching step of etching the transparent conductive film to form the gate electrode and the gate line. Door is preferable.
薄膜トランジスタマトリクスの本発明を適用すること
により下記事項が可能になるため、ホトエッチング工程
数の著しい増大なしで、走査線の配線抵抗が低く、製造
歩留りの高い薄膜トランジスタマトリクスを得ることが
できる。By applying the present invention to a thin film transistor matrix, the following can be achieved. Therefore, a thin film transistor matrix with low wiring resistance of a scanning line and a high production yield can be obtained without a remarkable increase in the number of photoetching steps.
（１） 透明導電膜を最初に形成できると、原理的にホ
トエッチング工程数を少く抑えることができる。本発明
の適用によりこれが可能になる。(1) If a transparent conductive film can be formed first, the number of photoetching steps can be reduced in principle. This is made possible by the application of the present invention.
（２） 透明導電膜が第一層膜であるためにエッチング
に対する制約が少く、エッチング加工による不良を極め
て少なくできる。また、高融点金属膜で保護されている
ため、プロセス中透明導電膜に基づく欠陥が発生しにく
い。(2) Since the transparent conductive film is the first layer film, there are few restrictions on etching, and defects due to etching can be extremely reduced. Further, since the protective film is protected by the high melting point metal film, defects due to the transparent conductive film hardly occur during the process.
（３） 走査線が少なくとも透明導電膜と高融点金属、
低抵抗Al膜の多層配線にでき、少なくとも２工程以上の
ホトエッチングにできるため、走査線の断線防止、低抵
抗化ができる。(3) The scanning line is at least a transparent conductive film and a high melting point metal,
Since a multilayer wiring of a low-resistance Al film can be formed and photo-etching can be performed in at least two steps, disconnection of a scanning line can be prevented and resistance can be reduced.
以下、本発明の一実施例を第１図〜第３図により説明
する。An embodiment of the present invention will be described below with reference to FIGS.
第１図（ａ）は本発明を適用した薄膜トランジスタマ
トリスの一部の平面図を、第１図（ｂ）は本発明の特徴
がでる走査線の断面構造を、第２図は本発明を適用した
場合の薄膜トランジスタの断面構造例を、第３図は製造
プロセスの一例をフローチャートで示す。1 (a) is a plan view of a part of a thin film transistor matrix to which the present invention is applied, FIG. 1 (b) is a cross-sectional structure of a scanning line showing characteristics of the present invention, and FIG. 2 is an application of the present invention. FIG. 3 is a flow chart showing an example of a cross-sectional structure of the thin film transistor in this case.
走査線８を絶縁性基板１側から、ITO膜（酸化インジ
ウム＋酸化スズ）81、Cr膜82、Al膜83からなる多層配線
としている。この例では断線防止のために、信号線９も
Cr膜91とAl膜92からなる多層配線としている。ゲート電
極２は透明導電膜であるITO膜21とCr膜22からなる多層
構造となっている。ソース電極６と画素電極７の接続
は、画素電極となるITO膜の保護に用いたCr膜71を介し
て行っている。以下、第３図のフローチャートに従って
製造方法を説明する。The scanning line 8 is a multilayer wiring composed of an ITO film (indium oxide + tin oxide) 81, a Cr film 82, and an Al film 83 from the insulating substrate 1 side. In this example, the signal line 9 is also
It is a multilayer wiring composed of a Cr film 91 and an Al film 92. The gate electrode 2 has a multilayer structure including an ITO film 21 and a Cr film 22 which are transparent conductive films. The connection between the source electrode 6 and the pixel electrode 7 is made via the Cr film 71 used for protecting the ITO film serving as the pixel electrode. Hereinafter, the manufacturing method will be described with reference to the flowchart of FIG.
まず、ガラス板等の絶縁性基板１上にITO膜と、Cr
膜、Al膜を順次スパッタリング法等により成膜する。次
いで、ホトエッチングによりAl膜を加工し、走査線８の
Al配線83を形成する更に、ホトエッチングにより加工
し、走査線８のITO配線81とCr配線82を形成する。この
時、ITO膜のアンダーカッタを防ぐため、同一ホトレジ
ストを用い、Crエッチ→ITOエッチ→Crエッチとしてい
る。Al膜のエッチングには、H3PO4＋HNO3＋CH3COOH＋H2
からなるエッチング液を用いることが多い。そのため、
ITO膜の膜質によっては、このエッチング液により損傷
を受けることがある。しかし、この場合には、Cr膜で保
護されているのでその心配はない。また、ITO膜のエッ
チングでは、その膜質のバラつきのため、エッチング残
り等の不良が発生しやすい。しかし、上層のAl膜とCr膜
がレジストで保護されており、最下層に存在するために
選択エッチングのむずかしさがないことから、エッチン
グ液選択の自由度が大きく、エッチング不良を防ぎやす
い。First, an ITO film and a Cr film are placed on an insulating substrate 1 such as a glass plate.
A film and an Al film are sequentially formed by a sputtering method or the like. Next, the Al film is processed by photoetching,
The Al wiring 83 is formed, and further processed by photoetching to form the ITO wiring 81 and the Cr wiring 82 of the scanning line 8. At this time, in order to prevent the undercut of the ITO film, the same photoresist is used, and Cr etching → ITO etching → Cr etching. H 3 PO 4 + HNO 3 + CH 3 COOH + H 2
Often, an etching solution consisting of for that reason,
Depending on the film quality of the ITO film, the etching solution may cause damage. However, in this case, there is no need to worry because it is protected by the Cr film. In addition, in the etching of the ITO film, defects such as residual etching are likely to occur due to variation in the film quality. However, since the upper Al film and the Cr film are protected by the resist and are present in the lowermost layer, there is no difficulty in selective etching. Therefore, the degree of freedom in selecting an etching solution is large, and it is easy to prevent poor etching.
次に、ゲート絶縁膜として用いるシリコン窒化膜と、
半導体膜として用いる非晶質シリコン膜と電極のコンタ
クトに用いるリンをドーブしたｎ型の非晶質シリコン質
をプラズマCVD法（Ｃhemical Ｖapor Ｄeposition）に
より連続成膜する。この場合にも、画素電極として用い
るITO膜７をCr膜71で保護しているため、還元雰囲気に
さらされることによる膜質劣化を防げる。Next, a silicon nitride film used as a gate insulating film,
Amorphous silicon substance of n-type that dove phosphorus for use in contact with the amorphous silicon film and the electrode are continuously formed by plasma CVD (C hemical V apor D eposition) used as the semiconductor film. Also in this case, since the ITO film 7 used as the pixel electrode is protected by the Cr film 71, deterioration of the film quality due to exposure to the reducing atmosphere can be prevented.
次いで、薄膜トランジスタ領域をホトエッチングによ
り形成する。エッチングはCF4＋O2ガスをエッチングガ
スとして、ドライエッチングにより行う。エッチング条
件を、非晶質シリコン膜の方がシリコン窒化膜より大き
なエッチング速度になるようにし、非晶質シリコン膜領
域４とシリコン窒化膜領域３を形成する。Next, a thin film transistor region is formed by photoetching. Etching is performed by dry etching using CF 4 + O 2 gas as an etching gas. The etching conditions are such that the amorphous silicon film has a higher etching rate than the silicon nitride film, and the amorphous silicon film region 4 and the silicon nitride film region 3 are formed.
次に、Cr膜とAl膜を順次スパッタリグ法で成膜する。
この後に、ホトエッチングによりAl膜を加工し、信号線
９のAl配線92、ドレイン電極５のAl部分53、ソース電極
６のAl部分と画素電極と接続する配線のAl部分63を形成
する。更に、ホトエッチングによりCr膜を加工し、ドレ
イン電極５（Cr部分は52）とソース電極６（Cr部分は6
1）を分離するとともに、画素電極７上のCr膜を除去す
る。この時、薄膜トランジスタのソース電極６と画素電
極７はソース電極に用いたCr膜62、Al膜63、ITO膜の保
護に用いたCr膜71により接続される。更に、リンをドー
プした非晶質シリコン膜を薄膜トランジスタのチャネル
部分から除去し、ドレインコンタクト51のソースコンタ
クト61を分離する。ドレインコンタクトとソースコンタ
クトはリンをドーブしたｎ型の非晶質シリコン膜より構
成される。同一レジストを用いて更にCr膜をエッチング
すると、ドレイン電極５とソース電極６のCr膜52、62が
後退して、ｎ型非晶質シリコン膜のアンダーカットを防
ぐことができる。以上の工程により第１図〜第２図のア
クティブマトリクス基板が完成する。Next, a Cr film and an Al film are sequentially formed by a sputter rig method.
Thereafter, the Al film is processed by photoetching to form the Al wiring 92 of the signal line 9, the Al part 53 of the drain electrode 5, the Al part of the source electrode 6, and the Al part 63 of the wiring connected to the pixel electrode. Further, the Cr film is processed by photoetching, and the drain electrode 5 (Cr portion is 52) and the source electrode 6 (Cr portion is 6
1) is separated and the Cr film on the pixel electrode 7 is removed. At this time, the source electrode 6 and the pixel electrode 7 of the thin film transistor are connected by the Cr film 62, the Al film 63 used for the source electrode, and the Cr film 71 used for protecting the ITO film. Further, the amorphous silicon film doped with phosphorus is removed from the channel portion of the thin film transistor, and the source contact 61 of the drain contact 51 is separated. The drain contact and the source contact are composed of an n-type amorphous silicon film doped with phosphorus. If the Cr film is further etched using the same resist, the Cr films 52 and 62 of the drain electrode 5 and the source electrode 6 recede, so that the undercut of the n-type amorphous silicon film can be prevented. Through the above steps, the active matrix substrate shown in FIGS. 1 and 2 is completed.
走査線と信号線は選択エッチングの可能な２種類以上
の導電膜で構成され、ホトエッチング工程数が２回とな
っているため、断線を著しく低減できる。すなわち、歩
留り向上に効果的な第５図の場合と同等の製造歩留りが
得られる。また配線の構成要素としてAl膜を使用してい
るため、配線の低抵抗化が達成される。走査線に対する
この効果は、本発明の適用によって達成される。すなわ
ち、走査線の構成膜の中の低抵抗なAlを含むことが本発
明の１つのポイントである。Al膜はヒロックス成長防止
のために、SiやTi,Cu,Sb,Pdを含んでいてもさしつかえ
ない。Since the scanning line and the signal line are formed of two or more types of conductive films that can be selectively etched, and the number of photo-etching steps is two, disconnection can be significantly reduced. That is, a manufacturing yield equivalent to that of FIG. 5 which is effective for improving the yield can be obtained. Further, since the Al film is used as a component of the wiring, the resistance of the wiring is reduced. This effect on scan lines is achieved by applying the present invention. That is, one point of the present invention is to include low-resistance Al in the constituent film of the scanning line. The Al film may contain Si, Ti, Cu, Sb, or Pd to prevent hillock growth.
第３図では、ホトエッチング工程を２重わくで囲んで
いる。本実施例ではホトエッチング工程数は５である。In FIG. 3, the photoetching step is surrounded by a double frame. In this embodiment, the number of photo-etching steps is five.
薄膜トランジスタマトリクスの製造歩留り向上を目的
に考えられた第５図の場合には、接続端子部の端子出し
を含むと、７回のホトエッチング工程数を必要としてい
る。端子出しと薄膜トランジスタ領域の限定を同一ホト
エッチングで行っても、６回のホトエッチング工程数を
必要とする。従って、本発明の適用により、第５図に示
したような高歩留りの薄膜トランジスタマトリクスを少
ないホトエッチング工程数で得ることができる。むし
ろ、ホトエッチング工程数を少なくできる分、第５図の
場合より高歩留りとなる。この効果は、走査線８の透明
導電膜と高融点金属膜を順次積層することによって生ず
る。この場合、透明導電膜上の高融点金属膜は選択エッ
チングができなければならない。また、走査線８の配線
抵抗を低減するためには、前述したように高融点金属上
にAl膜を配置する必要がある。従って、前記高融点金属
はAl膜のエッチング液に対し、画素電極を保護できなけ
ればならない。薄膜トランジスタマトリクスの透明導電
膜には、酸化スズと酸化インジウムからなる膜が適す
る。よって、上記条件を満たす高融点金属としてCrやT
i,Ta,Nb,Zrが有効である。In the case of FIG. 5 which is considered for the purpose of improving the production yield of the thin film transistor matrix, seven photo-etching steps are required including the connection of the connection terminal portion. Even if the terminal connection and the limitation of the thin film transistor area are performed by the same photo etching, six photo etching steps are required. Therefore, by applying the present invention, a thin film transistor matrix having a high yield as shown in FIG. 5 can be obtained with a small number of photo-etching steps. Rather, the yield is higher than in the case of FIG. 5 because the number of photoetching steps can be reduced. This effect is caused by sequentially laminating the transparent conductive film of the scanning line 8 and the refractory metal film. In this case, the high melting point metal film on the transparent conductive film must be able to be selectively etched. Further, in order to reduce the wiring resistance of the scanning line 8, it is necessary to arrange the Al film on the high melting point metal as described above. Therefore, the refractory metal must be able to protect the pixel electrode against the etchant for the Al film. A film made of tin oxide and indium oxide is suitable for the transparent conductive film of the thin film transistor matrix. Therefore, Cr and T
i, Ta, Nb, Zr are effective.
本実施例では、信号線９やドレイン電極５、ソース電
極６を構成する薄膜を成膜するまでに、３回のホトエッ
チング工程数となる。これは、第６図の場合のホトエッ
チング工程数２より、ホトエッチングが１回多い。しか
し、走査線の高い製造歩留り、配線抵抗の低減等、補っ
て余りある利点がある。In this embodiment, three photo-etching steps are required until the thin film forming the signal line 9, the drain electrode 5, and the source electrode 6 is formed. This is because the number of photo-etching steps is one more than the number of photo-etching steps 2 in the case of FIG. However, there are advantages that can be compensated for, such as a high production yield of the scanning lines and a reduction in wiring resistance.
本実施例では走査線を、透明導電膜と高融点金属膜、
Al膜を順次積層した３層構造としているがAl膜の保護等
を目的にして、更に金属膜を重ねてもさしつかえない。
ただし、走査線の膜厚を必要以上に厚くすることは好ま
しくない。In this embodiment, the scanning line is a transparent conductive film and a high melting point metal film,
Although it has a three-layer structure in which Al films are sequentially laminated, a metal film may be further laminated for the purpose of protecting the Al film or the like.
However, it is not preferable to increase the thickness of the scanning line more than necessary.
本実施例ではゲート絶縁膜としてシリコン窒化膜を、
半導体膜として非晶質シリコン膜を用いた薄膜トランジ
スタをスイッチング素子とした場合を説明した。しか
し、酸化シリコン膜等他の絶縁膜をゲート絶縁膜とした
り、多結晶シリコン膜等他の半導体膜よりなる薄膜トラ
ンジスタをスイッチング素子とした薄膜トランジスタマ
トリクスに対しても、本発明を適用できる。In this embodiment, a silicon nitride film is used as a gate insulating film,
The case where a thin film transistor using an amorphous silicon film as a semiconductor film is used as a switching element has been described. However, the present invention can also be applied to a thin film transistor matrix in which another insulating film such as a silicon oxide film is used as a gate insulating film or a thin film transistor formed of another semiconductor film such as a polycrystalline silicon film is used as a switching element.
本発明によれば、製造歩留りの高い薄膜トランジスタ
マトリクスを少ないホトエッチング工程数で製造できる
ので、従来より安価な薄膜トランジスタマトリクスが得
られる効果がある。According to the present invention, a thin film transistor matrix having a high production yield can be manufactured with a small number of photo-etching steps, so that there is an effect that a thin film transistor matrix which is less expensive than the conventional one can be obtained.
第１図（ａ）は本発明を適用した薄膜トランジスタマト
リクスの一部の平面図、第１図（ｂ）は本発明の特徴を
示す走査線の断面図、第２図は本発明を適用した薄膜ト
ランジスタマトリクスにおける薄膜トランジスタの断面
図、第３図は本発明を適用した薄膜トランジスタマトリ
クスの製造手順を示すフローチャート、第４図は従来の
薄膜トランジスタの断面図の例、第５図は薄膜トランジ
スタマトリクスの一例を示す平面図、第６図は薄膜トラ
ンジスタマトリクス製造プロセスの一例を示す図であ
る。 １……絶縁性基板、２……ゲート電極 ３……ゲート絶縁膜、４……半導体膜 ５……ドレイン電極、６……ソース電極 ７……画素電極、８……走査線（ゲート線） ９……信号線（ドレイン線）1A is a plan view of a part of a thin film transistor matrix to which the present invention is applied, FIG. 1B is a cross-sectional view of a scanning line showing characteristics of the present invention, and FIG. 2 is a thin film transistor to which the present invention is applied FIG. 3 is a cross-sectional view of a thin film transistor in a matrix, FIG. 3 is a flowchart showing a manufacturing procedure of a thin film transistor matrix to which the present invention is applied, FIG. 4 is an example of a cross-sectional view of a conventional thin film transistor, and FIG. FIG. 6 is a diagram showing an example of a thin film transistor matrix manufacturing process. DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Gate electrode 3 ... Gate insulating film, 4 ... Semiconductor film 5 ... Drain electrode, 6 ... Source electrode 7 ... Pixel electrode, 8 ... Scanning line (gate line) 9 Signal line (drain line)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 釼持 秋広 神奈川県横浜市戸塚区吉田町292番地 株式会社日立製作所生産技術研究所内 (72)発明者 小下 敏之 神奈川県横浜市戸塚区吉田町292番地 株式会社日立製作所生産技術研究所内 (72)発明者 渡辺 邦彦 神奈川県横浜市戸塚区吉田町292番地 株式会社日立製作所生産技術研究所内 (72)発明者 中谷 光雄 神奈川県横浜市戸塚区吉田町292番地 株式会社日立製作所生産技術研究所内 (72)発明者 砂原 和雄 千葉県茂原市早野3300番地 株式会社日 立製作所茂原工場内 (56)参考文献 特開 昭62−28546（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihiro Kusunoki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Production Technology Laboratory (72) Inventor Toshiyuki Koshita 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd., Production Technology Laboratory Co., Ltd. (72) Kunihiko Watanabe, Inventor 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Hitachi, Ltd. Production Technology Laboratories (72) Mitsuo Nakatani 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Hitachi, Ltd. Production Technology Laboratory Co., Ltd. (72) Inventor Kazuo Sunahara 3300 Hayano, Mobara-shi, Chiba Pref. Mochi Plant, Hitachi, Ltd. (56) References JP-A-62-28546 (JP, A)
Claims (9)
と、該ゲート電極上に形成したゲート絶縁膜と、該ゲー
ト絶縁膜上に形成した半導体薄膜と、該半導体薄膜上に
形成したドレイン電極およびソース電極とから成る薄膜
トランジスタマトリクスにおいて、 該ゲート電極と接続したゲート線が、透明導電膜と、該
透明導電膜上に形成された高融点金属膜と、該高融点金
属膜上に形成された低抵抗金属膜とからなることを特徴
とする薄膜トランジスタマトリクス。1. A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, and a drain formed on the semiconductor thin film In a thin film transistor matrix including an electrode and a source electrode, a gate line connected to the gate electrode is formed on a transparent conductive film, a high melting point metal film formed on the transparent conductive film, and the high melting point metal film. And a low-resistance metal film.
と、該ゲート電極上に形成したゲート絶縁膜と、該ゲー
ト絶縁膜上に形成した半導体薄膜と、該半導体薄膜上に
形成したドレイン電極およびソース電極とから成る薄膜
トランジスタマトリクスにおいて、 該ゲート電極が、透明導電膜と、該透明導電膜上に形成
された高融点金属膜とからなり、 該ゲート電極と接続したゲート線が、該透明導電膜と、
該透明導電膜上に形成された該高融点金属膜と、該高融
点金属膜上に形成された低抵抗金属膜とからなることを
特徴とする薄膜トランジスタタマトリクス。2. A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, and a drain formed on the semiconductor thin film. In a thin film transistor matrix including an electrode and a source electrode, the gate electrode includes a transparent conductive film and a high-melting point metal film formed on the transparent conductive film, and the gate line connected to the gate electrode includes the transparent conductive film. A conductive film,
A thin film transistor matrix comprising: the high melting point metal film formed on the transparent conductive film; and a low resistance metal film formed on the high melting point metal film.
と、該ゲート電極上に形成したゲート絶縁膜と、該ゲー
ト絶縁膜上に形成した半導体薄膜と、該半導体薄膜上に
形成したドレイン電極およびソース電極とから成る薄膜
トランジスタマトリクスにおいて、 該ソース電極と接続した画素電極が、透明導電膜からな
り、 該ゲート電極が、該透明導電膜と、該透明導電膜上に形
成された高融点金属膜とからなり、 該ゲート電極と接続したゲート線が、該透明導電膜と、
該透明導電膜上に形成された該高融点金属膜と、該高融
点金属膜上に形成された低抵抗金属膜とからなることを
特徴とする薄膜トランジスタマトリクス。3. A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, and a drain formed on the semiconductor thin film. In a thin film transistor matrix including an electrode and a source electrode, a pixel electrode connected to the source electrode is formed of a transparent conductive film, and the gate electrode is formed of the transparent conductive film and a high melting point metal formed on the transparent conductive film. A gate line connected to the gate electrode, the transparent conductive film,
A thin film transistor matrix comprising the high melting point metal film formed on the transparent conductive film and a low resistance metal film formed on the high melting point metal film.
酸化スズを含むことを特徴とする請求項１から３のいず
れかに記載の薄膜トランジスタマトリクス。4. The thin film transistor matrix according to claim 1, wherein said transparent conductive film contains indium oxide or tin oxide.
いずれかであることを特徴とする請求項１から４のいず
れかに記載の薄膜トランジスタマトリクス。5. The thin film transistor matrix according to claim 1, wherein said high melting point metal film is made of any one of Cr, Ti, Ta, Nb, and Zr.
含むAlであることを特徴とする請求項１から５のいずれ
かに記載の薄膜トランジスタマトリクス。6. The thin film transistor matrix according to claim 1, wherein said low resistance metal film is made of Al or Al containing a transition metal.
電極上に形成したゲート絶縁膜と、該ゲート絶縁膜上に
形成した半導体薄膜と、該半導体薄膜上に形成したドレ
イン電極およびソース電極と、該ソース電極と接続した
画素電極と、該ゲート電極と接続したゲート線とを含む
薄膜トランジスタマトリクスの製造方法であって、 該基板に透明導電膜、高融点金属膜および低抵抗金属膜
を順次成膜し、 該低抵抗金属膜をエッチング加工して該ゲート線の一部
を形成する第一のエッチング工程と、 該高融点金属膜をエッチング加工して該ゲート線の一部
および該ゲート電極の一部を形成する第二のエッチング
工程と、 該透明導電膜をエッチング加工して該表示電極、該ゲー
ト電極および該ゲート線を形成する第三のエッチング工
程と を含むことを特徴とする薄膜トラジスタマトリクスの製
造方法。7. A gate electrode formed on a substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, and a drain electrode and a source electrode formed on the semiconductor thin film And a pixel electrode connected to the source electrode and a gate line connected to the gate electrode. A method for manufacturing a thin film transistor matrix, comprising: forming a transparent conductive film, a high melting point metal film, and a low resistance metal film on the substrate sequentially. A first etching step of forming a part of the gate line by etching the low-resistance metal film; and forming a part of the gate line and the gate electrode by etching the high-melting metal film. And a third etching step of etching the transparent conductive film to form the display electrode, the gate electrode, and the gate line. Method of manufacturing a thin film Toraji static matrix characterized and.
電極上に形成したゲート絶縁膜と、該ゲート絶縁膜上に
形成した半導体薄膜と、該半導体薄膜上に形成したドレ
イン電極およびソース電極と、該ゲート電極と接続した
ゲート線とを含む薄膜トランジスタマトリクスの製造方
法であって、 該基板に透明導電膜、高融点金属膜および低抵抗金属膜
を順次成膜し、 該低抵抗金属膜をエッチング加工して該ゲート線の一部
を形成する第一のエッチング工程と、 該高融点金属膜をエッチング加工して該ゲート線の一部
および該ゲート電極の一部を形成する第二のエッチング
工程と、 該透明導電膜をエッチング加工して該ゲート電極および
該ゲート線を形成する第三のエッチング工程と を含むことを特徴とする薄膜トランジスタマトリクスの
製造方法。8. A gate electrode formed on a substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, a drain electrode and a source electrode formed on the semiconductor thin film. And a method of manufacturing a thin film transistor matrix including a gate line connected to the gate electrode, wherein a transparent conductive film, a high melting point metal film and a low resistance metal film are sequentially formed on the substrate, A first etching step of etching to form a part of the gate line; and a second etching step of etching the refractory metal film to form a part of the gate line and a part of the gate electrode. And a third etching step of etching the transparent conductive film to form the gate electrode and the gate line. Method.
クによりエッチングされ、 前記第二、第三のエッチング工程は、第二のマスクによ
りエッチングされることを特徴とする請求項８又は９記
載の薄膜トランジスタの製造方法。9. The method according to claim 8, wherein the first etching step is performed by using a first mask, and the second and third etching steps are performed by using a second mask. A method for manufacturing the thin film transistor according to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP370788A JP2574837B2 (en) | 1988-01-13 | 1988-01-13 | Thin film transistor matrix and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP370788A JP2574837B2 (en) | 1988-01-13 | 1988-01-13 | Thin film transistor matrix and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01180523A JPH01180523A (en) | 1989-07-18 |
| JP2574837B2 true JP2574837B2 (en) | 1997-01-22 |
Family
ID=11564821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP370788A Expired - Lifetime JP2574837B2 (en) | 1988-01-13 | 1988-01-13 | Thin film transistor matrix and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2574837B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5132745A (en) * | 1990-10-05 | 1992-07-21 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| US5502583A (en) * | 1993-05-15 | 1996-03-26 | Nec Corporation | Liquid crystal display device capable of compensating for a positioning error between a drain line and a display electrode |
| JP2000275663A (en) * | 1999-03-26 | 2000-10-06 | Hitachi Ltd | Liquid crystal display device and its production |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62285464A (en) * | 1986-06-03 | 1987-12-11 | Matsushita Electric Ind Co Ltd | Thin-film transistor array substrate and manufacture thereof |
-
1988
- 1988-01-13 JP JP370788A patent/JP2574837B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01180523A (en) | 1989-07-18 |
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