JPH01180523A - Thin-film transistor matrix and its production - Google Patents
Thin-film transistor matrix and its productionInfo
- Publication number
- JPH01180523A JPH01180523A JP63003707A JP370788A JPH01180523A JP H01180523 A JPH01180523 A JP H01180523A JP 63003707 A JP63003707 A JP 63003707A JP 370788 A JP370788 A JP 370788A JP H01180523 A JPH01180523 A JP H01180523A
- Authority
- JP
- Japan
- Prior art keywords
- film
- transparent conductive
- thin film
- conductive film
- transistor matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 48
- 239000011159 matrix material Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010408 film Substances 0.000 claims abstract description 92
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002844 melting Methods 0.000 claims abstract description 13
- 230000008018 melting Effects 0.000 claims abstract description 13
- 229910003437 indium oxide Inorganic materials 0.000 claims abstract description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910001887 tin oxide Inorganic materials 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- 229910052723 transition metal Inorganic materials 0.000 claims 2
- 150000003624 transition metals Chemical class 0.000 claims 2
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- 238000010030 laminating Methods 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 description 24
- 238000005530 etching Methods 0.000 description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000007547 defect Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 235000013399 edible fruits Nutrition 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241000218691 Cupressaceae Species 0.000 description 1
- 241001092070 Eriobotrya Species 0.000 description 1
- 235000009008 Eriobotrya japonica Nutrition 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001467 acupuncture Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 235000012054 meals Nutrition 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜トランジスタマトリクスに係り、特に液
晶等を用いた平面デイスプレィに好適な薄膜トランジス
タマトリクスとその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor matrix, and more particularly to a thin film transistor matrix suitable for flat displays using liquid crystals and the like, and a method for manufacturing the same.
非晶賀シリコン、Ｃｄ５ａ等の半導体薄膜を用いた薄膜
トランジスタは、アクティブマトリクス型の多素子表示
装置のスイッチング素子として注目されている。Thin film transistors using semiconductor thin films such as amorphous silicon and Cd5a are attracting attention as switching elements for active matrix multi-element display devices.
第４図は従来の薄膜トランジスタマトリクスに用いられ
ている薄膜トランジスタの断面構造の例である。すなわ
ち、絶縁性基板１上にゲート電極２、ゲート絶縁膜３、
半導体ｇ、ａ、ドレイン電極５、ソース電極６が順次積
層され℃いる。ソース電極６は液晶セルに対する一方の
電極となる画素電極７と接続される。そして、ゲート電
極２は走査＃８（ゲート巌とも呼ぶ）Ｋ、 ドレイン
電極は信号線９（ドレイン−とも呼ぶ）に接続され、薄
膜トランジスタマトリクスが構成される。FIG. 4 is an example of a cross-sectional structure of a thin film transistor used in a conventional thin film transistor matrix. That is, on an insulating substrate 1, a gate electrode 2, a gate insulating film 3,
Semiconductors g and a, a drain electrode 5, and a source electrode 6 are sequentially laminated at a temperature of .degree. The source electrode 6 is connected to a pixel electrode 7 serving as one electrode for the liquid crystal cell. Then, the gate electrode 2 is connected to a scan #8 (also called a gate gate) K, and the drain electrode is connected to a signal line 9 (also called a drain-), thereby forming a thin film transistor matrix.
現在、上記薄膜トランジスタマ） ＩＪクス裏造プロセ
スにおける課題は、歩留り向上とホトエツチング工程数
削減による製造コスト低減と配線抵抗低減である。信号
線と走査縁の断線防止、配線抵抗低減に対しては第５図
に示すように選択エツチングの可能な金属層による２層
配祿８１と８２．９１と９２（たとえば、Ｃｒとｌｄｏ
やＣｒと、４１）が提案されている。これに関するもの
としては、たとえば時開［６１−９５４８８が挙げられ
る。しかし、上記幼果を上げるためには、ホトエツチン
グ工程数が増大し℃しまう。一方、ホトエツチング工程
数削減のためには、第６図に示すようなプロセスが特開
昭６１−２７６３７４で提案されている。この場合ＶＣ
，は、信号線や走査線の歩留り低下が考慮されていない
。Currently, the challenges in the above-mentioned thin film transistor (IJ) backing process are to improve yield, reduce manufacturing costs by reducing the number of photo-etching steps, and reduce wiring resistance. To prevent disconnection of signal lines and scanning edges and to reduce wiring resistance, two-layer wiring 81 and 82, 91 and 92 (for example, Cr and
and Cr,41) have been proposed. Regarding this, for example, Jikai [61-95488] can be mentioned. However, in order to raise the above-mentioned young fruits, the number of photo-etching steps increases and the temperature increases. On the other hand, in order to reduce the number of photo-etching steps, a process as shown in FIG. 6 has been proposed in Japanese Patent Laid-Open No. 61-276374. In this case VC
, does not take into account the reduction in yield of signal lines and scanning lines.
また、配線の低抵抗化も基板サイズが太き（なると不十
分である。Furthermore, lowering the resistance of wiring is insufficient if the substrate size is large.
上記従来技術は、製造歩留り向上とホトエツチング工程
数削減の双方に対する配慮がされておらス、製造コスト
の低い薄膜トランジスタマトリクスを得られないという
ｎ、題があった。The above-mentioned conventional technology has the problem that it is not possible to obtain a thin film transistor matrix with low manufacturing cost because it does not take into account both the improvement in manufacturing yield and the reduction in the number of photo-etching steps.
本発明の目的は、製造時のホトエツチング工程数が少な
く、製造歩留りが高（、配線抵抗も低い薄膜トランジス
タマトリクスと製造プロセスを提供することにある。An object of the present invention is to provide a thin film transistor matrix and manufacturing process that requires fewer photoetching steps during manufacturing, has a high manufacturing yield (and has low wiring resistance).
本発明における薄膜トランジスタマトリクスは、基板と
、該基板上にゲート電極と、前記ゲート電極上に形成し
たゲート絶縁膜、半導体膜と、前記半導体薄膜上に設け
たドレイン電極とソース電極とから少なくともなる薄膜
トランジスタをスイッチング素子としている。A thin film transistor matrix in the present invention includes at least a substrate, a gate electrode on the substrate, a gate insulating film formed on the gate electrode, a semiconductor film, and a drain electrode and a source electrode provided on the semiconductor thin film. is used as a switching element.
上記目的は、走査縁を少なくとも３檀類の導電膜で構成
することにより達成される。特に、走査縁な基板側から
、少なくとも透明４を膜、透明導電膜をエツチングしに
くい薬液によりエツチングできる扁融点金楓、Ａｌを主
成分とする金属層を順次積層した構成にすると効果的で
ある。The above object is achieved by forming the scanning edge with at least three kinds of conductive films. In particular, it is effective to have a structure in which at least a transparent 4 film, a low melting point metal layer that can be etched with a chemical solution that does not easily etch the transparent conductive film, and a metal layer containing Al as a main component are sequentially laminated from the substrate side that is the scanning edge. .
薄膜トランジスタマトリクスに本発明を適用することに
より下記事項が可能になるため、ホトエツチング工程数
の著しい増大なしで、走査縁の記載抵抗が低（、製造歩
留りの高い薄膜トランジスタマトリクスを得ろことかで
きる。By applying the present invention to a thin film transistor matrix, the following items can be achieved. Therefore, it is possible to obtain a thin film transistor matrix with low writing resistance at the scanning edge (and high manufacturing yield) without significantly increasing the number of photoetching steps.
（１）透明導電膜を最初に形成できると、原理的にホト
エツチング工程数を少く抑えろことかできる。本発明の
適用九よりこれが可能になる。(1) If a transparent conductive film can be formed first, it is possible in principle to reduce the number of photoetching steps. This is made possible by application 9 of the present invention.
（２１透明４を膜が第−鳩膜であるためにエツチングに
対する制約が少（、エツチング加工による不良を極めて
少なくできる。また、高融点象属膜で保護されているた
め、プロセス中透明導電膜に基づく欠陥が発生しに（い
。(21 Transparent 4 is a transparent film, so there are few restrictions on etching.) Defects caused by etching can be extremely reduced.Also, since it is protected by a high melting point metal film, the transparent conductive film is removed during the process. Defects based on this may occur.
（３）走査縁が少なくとも透明導電膜と高融点金属、低
抵抗Ａｌ族の多層配線にでき、少なくとも２工程以上の
ホトエツチングにできるため、走査線の断線防止、低抵
抗化ができる。(3) Since the scanning edge can be made of multilayer wiring made of at least a transparent conductive film, a high melting point metal, and a low resistance Al group, and can be photo-etched in at least two or more steps, it is possible to prevent disconnection of the scanning line and reduce the resistance.
以下、本発明の一実施例を第１図〜第５図により説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.
第１図（α）は本発明を適用した薄膜トランジスタマ）
ＩＪクスの一部の平面因を、第１図（ｂｌは本発明の
特徴がでる走査線の断面構造を、第２図は本発明を適用
した場合の薄膜トランジスタの断面構造例を、第３図は
製造プロセスの一例を７ｏ−チャートで示す。Figure 1 (α) is a thin film transistor to which the present invention is applied)
The plane factors of a part of the IJ are shown in Figure 1 (bl is the cross-sectional structure of the scanning line where the features of the present invention appear, Figure 2 is an example of the cross-sectional structure of a thin film transistor when the present invention is applied, and Figure 3 is An example of the manufacturing process is shown in a 7o-chart.
走査線８を絶縁性基板１側から、ＩＴＯ膜（酸化インジ
ウム＋酸化スズ） ８１ 、 Ｃｒ膜８２、Ａｌ膜８３
からなる多層配線としている。この例では［ｊ［防止の
ために、信号線９もＣｒ膜９１とＡｌ換９２からなる多
層配線としている。ゲート電極２は透明導電膜であるＩ
ＴＯ換２１とＣｒｇ２２からなる多層構造となっている
。ソース電極６と画素′−極７の接続は、画素電極とな
るＩＴＯ展の保ｉに用いたＣｒ ｇ ７１を介して行っ
ている。以下、ＷＪ６図の）ａ−チャートに従って製造
方法を説明する。The scanning line 8 is connected from the insulating substrate 1 side to an ITO film (indium oxide + tin oxide) 81 , a Cr film 82 , an Al film 83
It is a multilayer wiring consisting of. In this example, in order to prevent [j], the signal line 9 is also a multilayer wiring consisting of a Cr film 91 and an Al film 92. The gate electrode 2 is a transparent conductive film I
It has a multilayer structure consisting of TO exchanger 21 and Crg22. The source electrode 6 and the pixel electrode 7 are connected through a Cr g 71 used to hold the ITO layer which becomes the pixel electrode. Hereinafter, the manufacturing method will be explained according to the a-chart in Figure WJ6.
まず、ガラス板等の絶縁性基板１上にＩＴＯ展と、Ｃｒ
％１，４１膜を順次スパッタリング法等により成膜す
る。次いで、ホトエツチングによりＡｌＨｇを加工し、
走査源８の、４１配線８５を形成する更に、ホトエツチ
ングにより加工し、走査源８のＩＴＯ配緘８１とＣｒ配
線８２を形成する。この時、ＩＴＯ展のアンダーカット
を防ぐため、同一ホトレジストを用い、Ｃｒエッチ→Ｉ
ＴＯエッチ→Ｃｒエッチとシテイル。Ａｌ ）Ｊ１４１
７） 工ｙ ｙ−ｙ ｆ Ｋ ハ、Ｈ，ｐＯ，−４−ｍ
ｉｄ。First, ITO and Cr were placed on an insulating substrate 1 such as a glass plate.
%1,41 films are sequentially formed by a sputtering method or the like. Next, process AlHg by photoetching,
The 41 wiring 85 of the scanning source 8 is formed.Furthermore, the ITO wiring 81 and the Cr wiring 82 of the scanning source 8 are formed by photoetching. At this time, in order to prevent undercutting of ITO, use the same photoresist and etch Cr → I
TO sex → Cr sex and shiteil. Al ) J141
7) Engineering y y-y f K Ha, H, pO, -4-m
id.
−）−ＣＨ３ＣＯＯ＆ −）−Ｈ，０からなるエツチン
グ液を用いることが多い。そのため、ＩＴＯ膜の膜質に
よっては、このエツチング液圧より損傷を受けることが
ある。しかし、この場合には、Ｃｒ膜で保護されている
のでその心配はない。また、ＩＴＯ膜のエツチングでは
、その良質のバラつきのため、エツチング残り等の不良
が発生しゃすい。しかし、上層ＯＡｌ膜とＣｒ膜がレジ
ストで保護されており、最下層に存在するために選択エ
ツチングのむすかしさかないことから、エツチング液選
択の自由度が大きく、エツチング不良を防ぎゃすい。An etching solution consisting of -)-CH3COO & -)-H,0 is often used. Therefore, depending on the quality of the ITO film, it may be damaged by this etching liquid pressure. However, in this case, there is no need to worry about this because it is protected by the Cr film. Furthermore, when etching an ITO film, defects such as etching residue are likely to occur due to variations in quality. However, since the upper OAl film and the Cr film are protected by a resist and exist in the bottom layer, selective etching is difficult, so there is a large degree of freedom in selecting the etching solution and it is easy to prevent etching defects.
次に、ゲート絶＃Ｒ膜として用いるシリコン窒化膜と、
半導体膜として用いる非晶質シリコン族と電極のコンタ
クトに用いるリンをドープしたル型の非晶質シリコン族
をプラズマＣＶＤ法（ＣｈｅｍｉｃａｌＶａｐｏｒ Ｄ
ｅｐｏｓｉｔｉｏｎ ）により連続成膜する。この場
合にも、画素電極として用いるＩＴＯ膜７をＣｒ膜膜種
１保護しているため、還元雰囲気にさらされることによ
る膜質劣化を防げる。Next, a silicon nitride film used as a gate isolation #R film,
The amorphous silicon group used as the semiconductor film and the phosphorus-doped amorphous silicon group used for the electrode contact are processed using the plasma CVD method (Chemical Vapor D).
Continuous film formation is performed by eposition). In this case as well, since the ITO film 7 used as the pixel electrode is protected by the Cr film type 1, deterioration in film quality due to exposure to a reducing atmosphere can be prevented.
次いで、薄膜トランジスタ領域をホトエツチングにより
形成する。エツチングはＣＦ４十〇、ガスをエツチング
カスとして、ドライエツチングにより行う。エツチング
条件を、非晶質シリコン族の方がシリコン窒化膜より大
きなエツチング速度になるようにし、非晶質シリコン膜
領域４とシリコン窒化層領域５を形成する。Next, a thin film transistor region is formed by photoetching. Etching is performed by dry etching using CF400 gas as an etching gas. Etching conditions are set such that the etching rate of the amorphous silicon group is higher than that of the silicon nitride film, and an amorphous silicon film region 4 and a silicon nitride layer region 5 are formed.
次に、Ｃｒ膜とＡｌ膜を１１０次スパッタリング法で成
膜する。この後に、ホトエツチングによりＡｌ膜を加工
し、信号線９のＡｌ配線９２、ドレイン電極５のＡｌ部
分５３、ソース電極６のＡｌ部分と画素電極と接続する
配線のＡｌ部分６６を形成する。更に、ホトエツチング
によりＣｒ膜を加工し、ドレイン電極５ （Ｃｒ部分は
５２）とンースｔ 極６ （Ｃ” ８分は６１）を分離
するとともに、画素電極７上のＣｒ膜を除去する。この
時、薄膜トランジスタのソース電極６と画素電極７はソ
ース電極に用いたＣｒ膜６２、Ａｌ ｐ ６５．１７”
０膜の保護に用いた（：ｒ ｐｄ ７１ Ｋより接続さ
れる。更に、リンをドープした非晶質シリコン膜を薄膜
トランジスタのチャネル部分から除去し、ドレインコン
タクト５１とソースコンタクト６１を分離する。ドレイ
ンコンタクトとソースコンタクトはリンをドーグしたル
型の非晶質シリコン族より構成される。同一レジストを
用いて更にＣｒ膜をエツチングすると、ドレイン電極５
とソース電極６のＣτ膜５２．６２が後退して、３型非
晶質シリコン換のアンダーカットを防ぐことができる。Next, a Cr film and an Al film are formed by the 110th order sputtering method. Thereafter, the Al film is processed by photoetching to form an Al wiring 92 of the signal line 9, an Al portion 53 of the drain electrode 5, an Al portion 66 of the wiring connecting the Al portion of the source electrode 6 and the pixel electrode. Furthermore, the Cr film is processed by photo-etching to separate the drain electrode 5 (52 for the Cr portion) and the ground electrode 6 (61 for the C''8 portion), and the Cr film on the pixel electrode 7 is removed. , the source electrode 6 and pixel electrode 7 of the thin film transistor are a Cr film 62 used for the source electrode, and an Al p 65.17"
The amorphous silicon film doped with phosphorus is removed from the channel portion of the thin film transistor to separate the drain contact 51 and the source contact 61. The contact and source contact are made of amorphous silicon group doped with phosphorus.When the Cr film is further etched using the same resist, the drain electrode 5
Then, the Cτ film 52, 62 of the source electrode 6 recedes, and undercut of type 3 amorphous silicon can be prevented.
以上の工程により第１逸〜第２図のアクティブマトリク
ス基板が完成する。Through the above steps, the active matrix substrates shown in FIGS. 1 to 2 are completed.
走査源と信号線は選択エツチングの可能な２徨挙以上の
導を膜で構成され、ホトエツチング工程数が２回となっ
ているため、断線を著しく低減できる。すなわち、歩留
り向上に効果的な第５図の場合と同等のｍ造か首りか侍
られる。また配−のｍ成畳索とし”’ＣＡＩ換を使用し
ているため、配線の低抵抗化が達成される。走査線に対
するこの幼来は、本発明の通用によって達成される。す
なわち、走査線の構成膜の中に低抵抗なＡｌを含むこと
が不発明の１つのポイントである。Ａ１％はヒロックス
成長防止のために、５ｉや１番、ｃｔｂ、ｓｂ、ｐｉを
官んでいてもさしつかえない。Since the scanning source and the signal line are made of a conductive film with two or more conductors that can be selectively etched, and the number of photoetching steps is two, disconnections can be significantly reduced. In other words, it is possible to use m-structure or necking, which is the same as in the case of FIG. 5, which is effective in improving the yield. In addition, since the wiring is an m-complex cable and a CAI conversion is used, a low resistance of the wiring is achieved. One of the points of non-invention is to include low-resistance Al in the constituent film of the wire.A1% may contain 5i, No. 1, ctb, sb, and pi to prevent hillox growth. do not have.
第３図では、ホトエツチング工程を２重わ（で囲んでい
る。不実り例ではホトエツチング工程数は５である。In FIG. 3, the photo-etching process is surrounded by a double box. In the unproductive example, the number of photo-etching processes is 5.
薄膜トランジスタマトリクスの製造歩留り同上を目的に
考えられた第５図の場合には、接ｄ喝子部の端子出しを
含むと、７回のホトエツチング工程数を必要としている
。瑚子出しと薄膜トランジスタ填城の限定を同一ホトエ
ツチングで行り又も。In the case of FIG. 5, which was designed for the purpose of improving the manufacturing yield of the thin film transistor matrix, seven photoetching steps are required, including the terminal extraction of the contact portion. The same photo-etching was used to remove the fibers and limit the thickness of the thin film transistor.
６回のホトエツチング工程数を必要とする。従って、本
発明の適用により、第５図に示したような高歩留りの薄
膜トランジスタマトリクスを少ないホトエツチング工程
数で得ることができる。むしろ、ホトエツチング工程数
を少な（できる分、第５図の場合より高歩留りとなる。Six photo-etching steps are required. Therefore, by applying the present invention, a high-yield thin film transistor matrix as shown in FIG. 5 can be obtained with a reduced number of photoetching steps. On the contrary, since the number of photo-etching steps can be reduced, the yield is higher than in the case of FIG.
この効果は、足ｆ麿８の透明導を膜と筒融点金Ｍ膜を順
次積層することによって生ずる。この場合、透明尋ｔｍ
上の尚融点金属膜は選択エツチングができなげれはなら
ない。また、走査載８の配線抵抗を低減するためには、
前述したように高融点金属上にＡｌ膜を配置する必要か
ある。従って、前記烏−点金一はＡｌ族のエツチング液
に対し、画素−極を保護できなければならない。薄膜ト
ランジスタマトリクスノ透明４１ｉＬ膜には、酸化スズ
と酸化インジウムからなる膜が適する。よって、上記条
件を満たす尚融点金属としてＣｒ ’ｆ’Ｔｉ 、 Ｔ
ａ 、 Ｎｂ 、Ｚｒが有効である。This effect is produced by sequentially laminating the transparent conductive film of the foot frame 8 and the tube melting point gold M film. In this case, transparent tm
The upper melting point metal film must not be selectively etched. In addition, in order to reduce the wiring resistance of the scanning mount 8,
As mentioned above, it is necessary to place an Al film on the high melting point metal. Therefore, the pixel electrode must be able to protect the pixel electrode from the Al group etching solution. A film made of tin oxide and indium oxide is suitable for the thin film transistor matrix transparent 41iL film. Therefore, as melting point metals that satisfy the above conditions, Cr'f'Ti, T
a, Nb, and Zr are effective.
本実施例では、信号源９やドレイン電極５、ソース′を
極６を構成する薄膜を＆族するまでに、３回のホトエツ
チング工程数となる。これは、第６図の場合のホトエツ
チング工程数２より、ホトエツチングか１回多い。しか
し、走査線の尚い製造歩留り、配線抵抗の低減等、補っ
て余りある利点 １がある。In this embodiment, three photo-etching steps are required to remove the signal source 9, the drain electrode 5, and the thin film forming the source electrode 6. This is one more photo-etching process than the two photo-etching steps in the case of FIG. However, there are advantages 1 that more than compensate for this, such as higher manufacturing yields for scanning lines and reduced wiring resistance.
本実施例では走査線を、透明２４電課と詞融点金Ｊ！！
４膜、Ａｌ族を順次積層した３層構造としているがＡｌ
膜の保Ｍ等を目的にして、更に金Ｊｆ％農を菖ねてもさ
しつかえない。ただし、定食−の膜厚を心安以上に厚（
することは好ましくない。In this embodiment, the scanning line is connected to the transparent 24-electronic section and the melting point J! !
It has a three-layer structure in which four films and Al group are sequentially laminated, but Al
For the purpose of maintaining the membrane, etc., it is okay to further add gold Jf%. However, the film thickness of the set meal is thicker than safe (
It is not desirable to do so.
本実施例ではゲート絶縁膜としてシリコン璧化膜な、半
導体族として非晶質シリコン族を用いた博展トランジス
タをスイッチング素子とした場合を説明した。しかし、
酸化シリコン展寺他の杷猷襄をゲート絶縁膜としたり、
多結晶シリコン展号他の半４坏展よりなる薄膜トランジ
スタをスイッチング素子とした薄膜トランジスタマトリ
ク／１ｍ対しても、本発明を適用できる。In this embodiment, a case has been described in which a Hiroten transistor using a silicon dielectric film as a gate insulating film and an amorphous silicon group as a semiconductor group is used as a switching element. but,
Using silicon oxide and other forms of loquat as the gate insulating film,
The present invention can also be applied to a thin film transistor matrix/1m in which the switching element is a thin film transistor made of polycrystalline silicon.
本発明によれは、裏通歩留りの尚い薄膜トランジスタマ
トリクスを少ないホトエツチング工程数で製造できるの
で、従来より安価な薄膜トランジスタマトリクスが得ら
れる効果がある。According to the present invention, a thin film transistor matrix with a high throughput yield can be manufactured with a reduced number of photoetching steps, so that a thin film transistor matrix that is cheaper than the conventional method can be obtained.
第１図（α）は本発明を適用した薄膜トランジスタマト
リクスの一部の平面図、第１１ａ＋Ａ＋は本発明の特徴
を示す走査線の断面図、第２図は本発明を通用した薄膜
トランジスタマトリクスにおける薄膜トランジスタの断
面図、第３図は本発明を適用した薄膜トランジスタマト
リクスの製造手順を示すフローチャート、第４図は従来
の′１４膜トランジスタの断面図の例、第５図は薄膜ト
ランジスタマトリクスの一例を示す平面図、第６図は薄
膜トランジスタマトリクス装造プロセスの一例を示す図
である。
１・・・絶縁性基板 ２・・・ゲート電極３・・・
ゲート絶縁膜 ４・・・半導体族５・・・ドレイン電
極 ６・・・ソース電極７・・・画素電極
８・・・走査＃ｌ（ゲー）１ｍ）９・・・信号源（ド
レイン鍼）
５、”ＹしＡンを檜
１２ 目
ｆｆｌ、Ｂ ７Ｌ［誹トｒ＠層１シリコン川鯨冠 ３
図FIG. 1 (α) is a plan view of a part of a thin film transistor matrix to which the present invention is applied, No. 11a+A+ is a cross-sectional view of a scanning line showing the features of the present invention, and FIG. 2 is a plan view of a part of a thin film transistor matrix to which the present invention is applied. 3 is a flowchart showing the manufacturing procedure of a thin film transistor matrix to which the present invention is applied, FIG. 4 is an example of a sectional view of a conventional '14 film transistor, and FIG. 5 is a plan view showing an example of a thin film transistor matrix. FIG. 6 is a diagram showing an example of a thin film transistor matrix fabrication process. 1... Insulating substrate 2... Gate electrode 3...
Gate insulating film 4... Semiconductor group 5... Drain electrode 6... Source electrode 7... Pixel electrode
8...Scanning #l (game) 1m) 9...Signal source (drain acupuncture) 5,"Y and A cypress 12th ffl, B 7L [Review r@layer 1 silicon river crest 3
figure
Claims (1)
ト電極上に形成したゲート絶縁膜と、該ゲート絶縁膜上
に形成した半導体薄膜と、該半導体薄膜上に形成したド
レイン電極とソース電極とからなる薄膜トランジスタマ
トリクスにおいて、該ゲート電極と接続したゲート線が
、透明導電膜と該透明導電膜上に形成した少なくとも２
種類からなる金属膜とからなることを特徴とする薄膜ト
ランジスタマトリクス。 ２、請求項１記載において、該透明導電膜を酸化インジ
ウムと酸化スズの少なくとも１つを含む薄膜とし、該透
明導電膜に接する該金属膜を該透明導電膜に対して腐食
性の少ない薬品でエッチングできる高融点金属膜とする
ことを特徴とした薄膜トランジスタマトリクス。 ３、請求項２記載において、該高融点金属膜をＣｒＴｉ
、Ｔａ、Ｎｂ、Ｚｒの中から選んだことを特徴とする薄
膜トランジスタマトリクス。 ４、請求項２若しくは３記載において、該高融点金属膜
と接する該透明導電膜と反対側の金属膜をＡｌあるいは
遷移金属を含むＡｌにより構成したことを特徴とした薄
膜トランジスタマトリクス。 ５、請求項４において、該遷移金属がＳｉ、Ｔｉ、Ｃμ
、Ｓｂ、Ｐｄであることを特徴とした薄膜トランジスタ
マトリクス。 ６、請求項１〜５のいずれか記載において、該透明導電
膜と同時に形成した透明導電膜により画素電極を構成す
ることを特徴とする薄膜トランジスタマトリクス。 ７、請求項１において、画素電極を該透明導電膜と同時
に形成した透明導電膜で形成することを特徴とする薄膜
トランジスタマトリクスの製造方法。 ８、請求項７において、該画素電極に用いる透明導電膜
を該ゲート線の透明導電膜と接する該金属膜で保護しな
がら加工し、該半導体薄膜と該画素電極とを接続し、該
画素電極上の該金属膜を除去することを特徴とする薄膜
トランジスタマトリクスの製造方法。[Claims] 1. A substrate, a gate electrode formed on the substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, and a semiconductor thin film formed on the semiconductor thin film. In the thin film transistor matrix consisting of the formed drain electrode and source electrode, a gate line connected to the gate electrode is connected to a transparent conductive film and at least two layers formed on the transparent conductive film.
A thin film transistor matrix comprising a metal film of various types. 2. In claim 1, the transparent conductive film is a thin film containing at least one of indium oxide and tin oxide, and the metal film in contact with the transparent conductive film is treated with a chemical that is less corrosive to the transparent conductive film. A thin film transistor matrix characterized by being made of a high melting point metal film that can be etched. 3. In claim 2, the high melting point metal film is made of CrTi.
, Ta, Nb, and Zr. 4. The thin film transistor matrix according to claim 2 or 3, wherein the metal film on the side opposite to the transparent conductive film in contact with the high melting point metal film is made of Al or Al containing a transition metal. 5. In claim 4, the transition metal is Si, Ti, Cμ
, Sb, and Pd. 6. A thin film transistor matrix according to any one of claims 1 to 5, characterized in that a pixel electrode is constituted by a transparent conductive film formed at the same time as the transparent conductive film. 7. The method of manufacturing a thin film transistor matrix according to claim 1, wherein the pixel electrode is formed of a transparent conductive film formed at the same time as the transparent conductive film. 8. In claim 7, the transparent conductive film used for the pixel electrode is processed while being protected by the metal film in contact with the transparent conductive film of the gate line, the semiconductor thin film and the pixel electrode are connected, and the pixel electrode is A method for manufacturing a thin film transistor matrix, the method comprising removing the metal film on the thin film transistor matrix.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP370788A JP2574837B2 (en) | 1988-01-13 | 1988-01-13 | Thin film transistor matrix and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP370788A JP2574837B2 (en) | 1988-01-13 | 1988-01-13 | Thin film transistor matrix and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01180523A true JPH01180523A (en) | 1989-07-18 |
| JP2574837B2 JP2574837B2 (en) | 1997-01-22 |
Family
ID=11564821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP370788A Expired - Lifetime JP2574837B2 (en) | 1988-01-13 | 1988-01-13 | Thin film transistor matrix and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2574837B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992006504A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| US5502583A (en) * | 1993-05-15 | 1996-03-26 | Nec Corporation | Liquid crystal display device capable of compensating for a positioning error between a drain line and a display electrode |
| US6567145B1 (en) * | 1999-03-26 | 2003-05-20 | Hitachi, Ltd. | Liquid crystal display device having conductive lines formed with amorphous oxide conductive layer on metal layer and method of fabrication thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62285464A (en) * | 1986-06-03 | 1987-12-11 | Matsushita Electric Ind Co Ltd | Thin-film transistor array substrate and manufacture thereof |
-
1988
- 1988-01-13 JP JP370788A patent/JP2574837B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62285464A (en) * | 1986-06-03 | 1987-12-11 | Matsushita Electric Ind Co Ltd | Thin-film transistor array substrate and manufacture thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992006504A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| US5502583A (en) * | 1993-05-15 | 1996-03-26 | Nec Corporation | Liquid crystal display device capable of compensating for a positioning error between a drain line and a display electrode |
| US6567145B1 (en) * | 1999-03-26 | 2003-05-20 | Hitachi, Ltd. | Liquid crystal display device having conductive lines formed with amorphous oxide conductive layer on metal layer and method of fabrication thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2574837B2 (en) | 1997-01-22 |
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