JPH08248442A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH08248442A
JPH08248442A JP5229795A JP5229795A JPH08248442A JP H08248442 A JPH08248442 A JP H08248442A JP 5229795 A JP5229795 A JP 5229795A JP 5229795 A JP5229795 A JP 5229795A JP H08248442 A JPH08248442 A JP H08248442A
Authority
JP
Japan
Prior art keywords
layer
metal
liquid crystal
wiring
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5229795A
Other languages
Japanese (ja)
Inventor
Mitsushi Ikeda
光志 池田
Toshiya Kiyota
敏也 清田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5229795A priority Critical patent/JPH08248442A/en
Publication of JPH08248442A publication Critical patent/JPH08248442A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: To obtain low resistance, high chemical resistance in the succeeding processes and to obtain good adhesion property on a glass substrate which requires low temp. treatment by forming a conductive layer with addition of specified metal and a nitride layer of a second metal to constitute a wiring layer. CONSTITUTION: At least the wiring layer consists of a metal layer essentially comprising at least one kind of first metal selected from Cu, Al, Ag, Au, Pt with addition of at least one kind of second metal selected from Ti, Zr, Hf, Al, Ta, Si, B, and a second metal nitride layer which covers the surface of the metal layer. Namely, for example, the gate electrode wire 17a consists of a Cu-Zr alloy conductive layer 20a and a ZrN nitride layer 21a which covers the conductive layer 20a. The ZrN layer 21a is also formed between the conductive layer 20a and a substrate 12. Similarly, the storage capacitor line 19 consists of a Cu-Zr alloy conductive layer 20b and a ZrN insulating layer 21b which covers the conductive layer 20b. Further, the address line is patterned at one time.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は液晶表示装置、とくに基
板上に配置される配線層や電極層に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a wiring layer and an electrode layer arranged on a substrate.

【0002】[0002]

【従来の技術】非結晶質シリコン(a−Si)膜を用い
た薄膜トランジスタ(TFT)をスイッチング素子とし
て設けたアクティブマトリクス型液晶表示装置は、安価
な非結晶質のガラス基板を用いて低温成膜ができるa−
Si膜を用いてTFTアレイを構成することにより、大
面積、高精細、高画質かつ安価なパネルディスプレイ
(フラット型テレビジョン)を実現できる。
2. Description of the Related Art An active matrix type liquid crystal display device provided with a thin film transistor (TFT) using an amorphous silicon (a-Si) film as a switching element is formed at a low temperature by using an inexpensive amorphous glass substrate. A-
By forming a TFT array using a Si film, a large-area, high-definition, high-quality and inexpensive panel display (flat type television) can be realized.

【0003】ところで、この種のアクティブマトリクス
型液晶表示装置を高精細化、大面積化し、かつ画素の開
口率を上げるためには、TFTのソース、ドレインに接
続するデータ線やTFTのゲートに接続するアドレス線
等の電極配線を薄く、細く、かつ長くすることが必要不
可欠である。
By the way, in order to increase the definition and area of this type of active matrix type liquid crystal display device and to increase the aperture ratio of the pixel, it is connected to the data line connected to the source and drain of the TFT and the gate of the TFT. It is indispensable to thin, thin, and lengthen the electrode wiring such as the address line.

【0004】しかもパルス信号の波形歪みをなくすため
には、配線抵抗を十分に低くしなければならないため、
配線用材料の抵抗率が小さくなければならない。しかも
例えばゲート線をガラス基板上に形成し、この上に絶縁
膜やa−Si膜を重ねてTFTを構成する逆スタガー形
のTFT構造を採用する場合、アドレス線やTFTのゲ
ートになるゲート電極線は、その後のプロセスに用いら
れるエッチングなどの薬品処理に耐えられる材料である
ことも要求される。
Moreover, in order to eliminate the waveform distortion of the pulse signal, the wiring resistance must be sufficiently low,
The resistivity of the wiring material must be low. Moreover, for example, when a gate line is formed on a glass substrate and an inverse stagger type TFT structure in which an insulating film or an a-Si film is stacked on the glass line to form a TFT, a gate electrode that becomes a gate of the address line or TFT The wire is also required to be a material that can withstand chemical treatments such as etching used in subsequent processes.

【0005】従来このような要素を満たすアドレス線や
ゲート電極配線材料として、Ta,Ti,Crなどの各
種金属膜、およびそれらの元素を含む合金膜が用いられ
ているが、さらに大面積化,高精細化を図るためにはよ
り低抵抗で加工性がよく、しかも各種薬品処理工程で耐
性が優れた材料が望まれている。
Conventionally, various metal films such as Ta, Ti, and Cr, and alloy films containing these elements have been used as address line and gate electrode wiring materials that satisfy such elements. In order to achieve high definition, a material having lower resistance and good workability and excellent resistance in various chemical treatment steps is desired.

【0006】配線の抵抗率は12インチ以下の640×
480画素のグラフィックアレイに対しては205μΩ
cm以下、15インチ以下の1028×768画素のグ
ラフィックアレイに対しては15μΩcm以下、20イ
ンチ以下の1280×1028画素の大型グラフィック
アレイに対しては10μΩcm以下が必要である。そこ
で、より低抵抗な配線材料として、例えばAl,Cuな
どの金属が考えられるが、例えばAl,Cuでアドレス
線や蓄積容量線を形成した場合、後工程におけるIT
O,Al,SiOx、SiNx用エッチング溶液に対す
る耐性がないために断線が発生する等の問題がある。こ
のため図4に示すように基板1上のAl配線膜2の表面
を耐酸性の良いTa,Cr層3で被覆した配線が使用さ
れているが、このような配線を用いると金属膜の形成工
程およびパターニング、エッチングの工程がそれぞれ1
回ずつ増えコストの増大という問題を発生する。また,
Alの表面を陽極酸化して保護した配線も使用されてい
るが、Alを陽極酸化するために配線をショートする必
要があるなど配線パターンの自由度が制限されまた陽極
酸化の際に配線のコンタクト部の酸化を防ぐためにレジ
スト等のマスクが必要であることからマスク工程が増加
してコストが増大するという問題があった。
The resistivity of the wiring is 640 ×, which is 12 inches or less.
205 μΩ for 480 pixel graphic array
15 μΩcm or less is required for a 1028 × 768 pixel graphic array of cm or less and 15 inches or less, and 10 μΩcm or less for a large graphic array of 1280 × 1028 pixels of 20 inches or less. Therefore, metals such as Al and Cu can be considered as wiring materials having a lower resistance. However, when the address lines and the storage capacitance lines are formed of Al and Cu, for example, IT in a post process is used.
Since there is no resistance to the etching solution for O, Al, SiOx, and SiNx, there is a problem such as disconnection. For this reason, as shown in FIG. 4, a wiring in which the surface of the Al wiring film 2 on the substrate 1 is covered with a Ta and Cr layer 3 having good acid resistance is used. When such wiring is used, a metal film is formed. 1 step each for patterning and etching
There is a problem that the cost increases as the number of times increases. Also,
Wiring in which the surface of Al is anodized and protected is also used, but the flexibility of the wiring pattern is limited, such as the need to short the wiring to anodize Al, and the contact of the wiring during anodization. Since a mask such as a resist is required to prevent the oxidation of the portion, there is a problem that the mask process is increased and the cost is increased.

【0007】また、データ線などのソース,ドレイン電
極配線を基板面に設けるスタガー型のTFT構造の場合
には、ソース,ドレイン電極材料に同様な特性が要求さ
れることになり、さらに同じ様な問題がTFT駆動でな
い液晶表示素子の場合にも存在する。
Further, in the case of a stagger type TFT structure in which source and drain electrode wirings such as data lines are provided on the substrate surface, similar characteristics are required for the source and drain electrode materials, and the same characteristics are obtained. The problem also exists in the case of a liquid crystal display element that is not driven by TFT.

【0008】[0008]

【発明が解決しようとする課題】上記問配線の低抵抗化
として上記Al,Cuの他、Ag、Au、Ptの低抵抗
配線材料が考えられるが、Al,Cuは非常に耐酸性,
耐アルカリ性が弱く、SiO等の酸化膜で被覆しても後
工程の各種薬品処理によって絶縁膜のピンホール等を通
して薬品による配線材料の腐食によって断線を引き起こ
してしまう。又、Cu、Ag、Au,Ptは基板への被
膜の付着性が弱く剥離しやすい。又、Au,PtはSi
O,SiN等の絶縁膜をその上に形成した場合、密着性
が悪いために絶縁膜が剥がれやすいと言う問題が発生す
る。
In order to reduce the resistance of the above wiring, low resistance wiring materials such as Ag, Au and Pt in addition to the above Al and Cu are conceivable. However, Al and Cu are very resistant to acid.
Alkali resistance is weak, and even if it is covered with an oxide film such as SiO, various chemical treatments in the subsequent steps may cause disconnection due to corrosion of the wiring material by chemicals through pinholes or the like of the insulating film. Further, Cu, Ag, Au, and Pt have weak adhesion of the coating film to the substrate and are easily peeled off. Also, Au and Pt are Si
When an insulating film such as O or SiN is formed on the insulating film, there is a problem that the insulating film is easily peeled off due to poor adhesion.

【0009】本発明はこのような事情に対処して、低抵
抗かつ後工程での各種薬品処理に対する耐性を持つ配線
材料、および構成が容易で基板への被着性がよく、信頼
性の高い配線層や電極層をもつ液晶表示装置の提供を目
的とする。
The present invention copes with such a situation and has a low resistance and a wiring material having resistance to various chemical treatments in a later step, and an easy construction, good adherence to a substrate, and high reliability. An object is to provide a liquid crystal display device having a wiring layer and an electrode layer.

【0010】[0010]

【課題を解決するための手段】本発明は、一対の基板
と、これら基板間に挟持される液晶層と、前記基板の前
記液晶層側の表面に形成される電極および前記電極に電
気的に接続され前記基板の表面に配設される配線層とを
具備する液晶表示装置において、少なくとも前記配線層
がCu、Al、Ag、Au、Ptから選ばれた少なくと
も一種の第1の金属を主体にし、Ti、Zr、Hf、A
l、Ta、Si、Bから選ばれた少なくとも一種の第2
の金属を添加してなる金属層と、この金属層の表面を被
覆する、前記第2の金属の窒化物層とを有することを特
徴とする液晶表示装置を得るものである。
According to the present invention, a pair of substrates, a liquid crystal layer sandwiched between the substrates, an electrode formed on the surface of the substrate on the liquid crystal layer side, and the electrode are electrically connected. A liquid crystal display device comprising: a wiring layer connected to and disposed on the surface of the substrate, wherein at least the wiring layer is mainly composed of at least one first metal selected from Cu, Al, Ag, Au, and Pt. , Ti, Zr, Hf, A
at least one second selected from l, Ta, Si and B
A liquid crystal display device comprising a metal layer formed by adding the above metal and a nitride layer of the second metal, which covers the surface of the metal layer.

【0011】[0011]

【作用】本発明の配線材料は、低抵抗率の配線材料であ
る、Al,Au,Cu,Pt,Ag等に耐酸性が良くN
と反応しやすいTi,Zr,Hf,Al等を添加し表面
に耐食性が良く付着力の強いTiN,ZrN,HfNを
形成することにより低抵抗で耐食性,付着力の良い配線
材料が実現できる。
The wiring material of the present invention has good acid resistance to Al, Au, Cu, Pt, Ag, etc., which is a low resistivity wiring material.
By adding Ti, Zr, Hf, Al, etc., which easily react with, and forming TiN, ZrN, HfN having good corrosion resistance and strong adhesion on the surface, a wiring material having low resistance and good corrosion resistance and adhesion can be realized.

【0012】本発明によれば、Al,Au,Cu,Pt
およびこれら金属を主とした合金表面に高耐薬品層を形
成させることにより、低抵抗であり、かつ耐薬品処理特
性においても優れた配線材料を提供できる。これらの金
属配線をアドレスラインとして用いることにより、欠陥
の少ない大面積,高精細,高画質の液晶ディスプレイ
(液晶表示装置)が実現できる。
According to the present invention, Al, Au, Cu, Pt
By forming a high chemical resistance layer on the surface of an alloy mainly containing these metals, it is possible to provide a wiring material having low resistance and excellent chemical resistance treatment characteristics. By using these metal wirings as address lines, a large-area, high-definition, high-quality liquid crystal display (liquid crystal display device) with few defects can be realized.

【0013】本発明の配線材料は、低抵抗性かつ後工程
の耐各種薬品処理特性を満足する配線構造として低抵抗
率の配線材料である、Al,Au,Cu,Pt,Agの
第1の金属に、耐酸性が良く窒素と反応しやすいTi,
Zr,Hf,Al等の易窒化金属を添加しNH3 ,メチ
ルヒドラジン等の窒化性ガス中で熱処理とすることによ
りAl,Au,Cu,Pt,Agと第2の金属の合金か
らなる導電層の表面にTiN,ZrN,HfN,AlN
等を形成する。TiN等の窒化物は耐酸性が強く、基板
との付着力も強いためエッチャントにより腐食され断線
を発生することがなく、内部は低抵抗のCu,Alであ
るため全体として低抵抗で耐食性の良い配線材料が実現
できる。また内部のAl,Au,Cu,Pt,Ag等に
も耐食性及び耐熱性の良いTi,Zr,Hfを添加して
いるため、もし表面の窒化物が破れても内部のエッチン
グを防止することができる。
The wiring material of the present invention is a wiring material having a low resistance and a low resistivity as a wiring structure satisfying various chemical treatment characteristics in the post-process. The first wiring material is made of Al, Au, Cu, Pt, Ag. Ti, which has good acid resistance and easily reacts with nitrogen,
A conductive layer made of an alloy of Al, Au, Cu, Pt, Ag and a second metal by adding an easily nitriding metal such as Zr, Hf and Al and performing heat treatment in a nitriding gas such as NH 3 and methylhydrazine. On the surface of TiN, ZrN, HfN, AlN
And so on. Nitride such as TiN has strong acid resistance and strong adhesion to the substrate so that it is not corroded by an etchant to cause wire breakage, and the inside is Cu and Al with low resistance, so overall low resistance and good corrosion resistance Wiring material can be realized. Further, since Al, Au, Cu, Pt, Ag, and the like inside are also added with Ti, Zr, and Hf having good corrosion resistance and heat resistance, it is possible to prevent internal etching even if the nitride on the surface is broken. it can.

【0014】さらに、本発明に係る配線材料について詳
述する。ガラス基板上にそれぞれAl,Cu,Au,A
g,AlにTi,Zr,Hfを1〜10at%(原子
%)添加した合金膜をそれぞれスパッタ装置により成膜
した。それぞれの膜は、製膜後、またはアニール後にお
いて電気抵抗率はそれぞれ抵抗率が10μΩcm以下と
従来から用いられているMo−Taの約45μΩcm等
に対して、低抵抗配線材料として十分に低い値を得た。
Further, the wiring material according to the present invention will be described in detail. Al, Cu, Au, A on the glass substrate respectively
Alloy films obtained by adding 1 to 10 at% (atomic%) of Ti, Zr, and Hf to g and Al were formed by a sputtering apparatus. The electric resistance of each film after film formation or after annealing is 10 μΩcm or less, which is a sufficiently low value as a low-resistance wiring material, compared to about 45 μΩcm of Mo-Ta which has been conventionally used. Got

【0015】これらの合金膜を燐酸系Alエッチング液
と希HF,ITOエッチャント(HCl,HNO3 ,H
2 Oの混合液)に浸してエッチングさせた。Ti,Z
r,Hf等の耐酸性金属が1at%以上添加されておれ
ば耐酸性に問題が無いことがわかった。抵抗率はTi,
Zr,Hfの添加量とともに増大し、10%以下であれ
ば抵抗率の増大は3倍以下であり大型高精細TFTスイ
ッチング型液晶表示装置のアドレス線として使用できる
が、好ましくは5at%を使用した方が抵抗率が低い。
These alloy films were formed by using a phosphoric acid-based Al etching solution and dilute HF and ITO etchants (HCl, HNO 3 , H).
It was immersed in a mixed solution of 2 O) for etching. Ti, Z
It has been found that there is no problem in acid resistance if an acid resistant metal such as r or Hf is added at 1 at% or more. The resistivity is Ti,
It increases with the addition amount of Zr and Hf, and if it is 10% or less, the increase in resistivity is three times or less and it can be used as an address line of a large-sized high-definition TFT switching type liquid crystal display device, but 5 at% is preferably used. The lower the resistivity.

【0016】このように、Ti、Zr、Hfを1at%
以上残すことによりITOエッチャントに対する耐酸性
が十分強くなり、断線の欠陥がほぼ零になった。
Thus, Ti, Zr, and Hf are contained at 1 at%
By leaving the above, the acid resistance to the ITO etchant became sufficiently strong, and the defects of disconnection became almost zero.

【0017】また、液晶表示装置ではガラス等の耐熱性
の弱い基板を用いるために窒化処理温度は450℃以下
でなければならない。このためには、N2 ガスを用いる
と反応温度が800℃程度であり高過ぎる。これに対
し、NH3 ,メチルヒドラジン等を用いることにより熱
処理温度を450℃以下に低くできた。Ti、Zr、H
fは窒化物の生成エンタルピー△HfがTiNが−8
0.8kcal/mol、ZrNが−87.2、HfN
が−89.3と小さいため低温化が可能である。
Further, in the liquid crystal display device, the nitriding temperature must be 450 ° C. or lower because a substrate having low heat resistance such as glass is used. For this purpose, when N 2 gas is used, the reaction temperature is about 800 ° C., which is too high. On the other hand, the heat treatment temperature could be lowered to 450 ° C. or lower by using NH 3 , methylhydrazine or the like. Ti, Zr, H
f is the enthalpy of formation of nitride ΔHf is −8 for TiN
0.8 kcal / mol, ZrN is -87.2, HfN
Is as small as −89.3, so it is possible to lower the temperature.

【0018】AlNの生成エンタルピーは−74.8k
cal/molと少し大きいが、実用上は使用できる。
また、NH3 ,メチルヒドラジンをプラズマ中で分解す
ることにより300℃以下に窒化温度を低温化できた。
The enthalpy of formation of AlN is -74.8 k.
Although it is a little larger than cal / mol, it can be used in practice.
Further, the nitriding temperature could be lowered to 300 ° C. or lower by decomposing NH 3 and methylhydrazine in plasma.

【0019】またCu、AgやAl等の低融点で低抵抗
な金属との合金化により、TiN、ZrNやAlNの形
成温度を低温化できた。Cu、Ag、Alのそれぞれの
添加量は1〜10at%が窒化温度,抵抗率より良好で
あった。
Further, by forming an alloy with a metal having a low melting point and a low resistance such as Cu, Ag and Al, the formation temperature of TiN, ZrN and AlN can be lowered. The addition amount of each of Cu, Ag, and Al was 1 to 10 at%, which was better than the nitriding temperature and the resistivity.

【0020】熱処理条件は金属の組み合わせにより適宜
選択すれば良く、250〜450℃の間で選択すれば良
い。これにより内部のZr,Ti,Hfの量を制御でき
1〜5%の間で制御すれば低抵抗で耐食性,付着力の良
い配線が実現できた。グラフィックアレイ(VGA)用
のためには1〜10at%以下が好ましく、これより大
きなVGAのためには1〜5at%、1080×102
8画素のスーパーエクステンドグラフィックアレイ(S
XGA)用としては0.5〜3at%が抵抗率の点から
好ましい。
The heat treatment conditions may be appropriately selected depending on the combination of metals, and may be selected between 250 and 450 ° C. As a result, the amount of Zr, Ti, and Hf inside can be controlled, and if the amount of Zr, Ti, and Hf is controlled within the range of 1 to 5%, wiring with low resistance, good corrosion resistance, and good adhesion can be realized. 1 to 10 at% or less is preferable for a graphic array (VGA), and 1 to 5 at% for a larger VGA, 1080 × 102.
8-pixel super extended graphic array (S
For XGA), 0.5 to 3 at% is preferable from the viewpoint of resistivity.

【0021】窒化ガスとしてはメチルヒドラジン(CH
3 NHNH2 )に限らず、ヒドラジン(NH2
2 ),エチルアニリン(C2 5 NHC2 5 ),N
3 等の他のガスを用いても良い。またNH3 またはメ
チルヒドラジンガスをプラズマ中で分解して熱処理する
ことによりZrN形成温度を250〜300℃まで低温
化できた。このように気相から窒化することにより、基
板界面にも窒化膜が形成されるため基板界面部の耐酸性
も向上し、また付着力も向上した。このためプラズマや
イオン注入により表面のみ窒化した場合よりも更に耐酸
性が良く、歩留まりが向上した。
Methylhydrazine (CH
3 NHNH 2 ) as well as hydrazine (NH 2 N
H 2 ), ethylaniline (C 2 H 5 NHC 2 H 5 ), N
Other gas such as H 3 may be used. Further, the ZrN formation temperature could be lowered to 250 to 300 ° C. by decomposing NH 3 or methylhydrazine gas in plasma and performing heat treatment. By nitriding from the vapor phase in this way, a nitride film is also formed on the substrate interface, so that the acid resistance at the substrate interface portion is improved and the adhesive force is also improved. Therefore, the acid resistance was better than that in the case where only the surface was nitrided by plasma or ion implantation, and the yield was improved.

【0022】以上において、Ti、Zr、Hfの量を5
〜10at%に増加すれば表面を窒化しなくても耐酸
性,付着力は十分良いため使用可能であるが、抵抗率が
高くなるため表面を窒化し内部のTi,Zr,Hfの量
を減らして抵抗率を下げた方が大型高精細には好適であ
る。
In the above, the amounts of Ti, Zr and Hf are set to 5
If it is increased to 10 at%, it can be used because the acid resistance and adhesion are sufficiently good without nitriding the surface, but the resistivity is high, so the surface is nitrided and the amount of Ti, Zr, and Hf inside is reduced. It is more suitable for large-scale high-definition to lower the resistivity.

【0023】窒化させる金属としては窒化物の生成エン
タルピー△Hfが小さい方が良く、−60kcal/m
ol以下の物が良く、Al(−74.8)、Ti(−8
0.8)、Zr(−87.2)、Hf(−89.3)や
Ta、Si、B、Sc、Th(−93.5)があり、上
述のTi,Zr、Hf、Al以外にTa,Si,Bを用
いることができる。
As the metal for nitriding, it is better that the enthalpy of formation ΔHf of the nitride is smaller, and it is −60 kcal / m.
ol or less is preferable, Al (-74.8), Ti (-8)
0.8), Zr (-87.2), Hf (-89.3) and Ta, Si, B, Sc, Th (-93.5), and other than Ti, Zr, Hf, and Al described above. Ta, Si, B can be used.

【0024】窒化はゲート絶縁膜堆積前に形成し、成膜
装置の基板加熱時に行うことにより工程の増加無しに実
行でき、コストは増加しない。
The nitriding can be performed without increasing the number of steps by forming it before depositing the gate insulating film and heating the substrate of the film forming apparatus, and the cost does not increase.

【0025】本発明において、配線層の主体となる第1
の金属にAlを用いた場合、易窒化金属である第2の金
属にAlを選ぶと、結果として第1と第2の金属が同じ
Alになる。しかしながら、Al配線をAlNで覆う構
成によって所期の低抵抗率を維持しつつ、耐薬品性、被
着性の良好な配線層やこれと同時に形成する電極層を得
ることができる。
In the present invention, the first main body of the wiring layer
When Al is used as the metal of No. 3, if Al is selected as the second metal that is an easily nitrided metal, the result is that the first and second metals have the same Al. However, the structure in which the Al wiring is covered with AlN makes it possible to obtain a wiring layer having good chemical resistance and adherence and an electrode layer formed at the same time while maintaining a desired low resistivity.

【0026】第1の金属が耐酸性の低いCu,Alの場
合、第2の金属群としてTi,Zr,Hfの窒化性の強
い易窒化金属とAu,Pd,Cr,Ge,Ag,Sm等
の希土類などの耐酸性が強く易窒化金属よりも窒化性の
小さい耐酸性金属をともに添加し、窒化処理時にTi,
Zr,Hf等の窒化性の強い易窒化金属を表面で完全に
反応させ、内部には耐酸性の強い耐酸性金属を残し、プ
ロセスマージンを大きくすることもできる。合金の抵抗
率は添加金属の量により変化するため易窒化金属のみを
添加する場合、易窒化金属の窒化の度合により内部に残
る添加金属の量が変化し抵抗率がバラ付くことがあるの
を防止し、製造マージンを大きくすることができる。
When the first metal is Cu or Al, which has low acid resistance, the second metal group includes easily nitriding metals such as Ti, Zr, and Hf having a strong nitriding property and Au, Pd, Cr, Ge, Ag, and Sm. Acid resistant metals such as rare earths, which have strong acid resistance and are less nitriding than easily nitriding metals, are added together.
It is also possible to increase the process margin by completely reacting the easily nitriding metal having strong nitriding property such as Zr and Hf on the surface and leaving the acid resistant metal having strong acid resistance inside. Since the resistivity of the alloy changes depending on the amount of the added metal, when adding only the easily nitrided metal, the amount of the added metal remaining inside may change due to the degree of nitriding of the easily nitrided metal, and the resistivity may vary. It is possible to prevent and increase the manufacturing margin.

【0027】さらに、易窒化金属と耐酸性金属の選択法
としてはTi,Zr,Hf,Sc,Siのような窒化性
の強い金属の中より2種類選択し、例えばZrのように
同群のうち窒化性の一番大きな金属を窒化し、Tiのよ
うに少し窒化性の弱い金属を耐酸性向上用の金属として
選択することもできる。
Further, as a method of selecting the easily nitriding metal and the acid resistant metal, two kinds of metals having a strong nitriding property such as Ti, Zr, Hf, Sc and Si are selected, and the same group of metals such as Zr is selected. Of these, the metal having the highest nitriding property may be nitrided, and a metal having a slightly weaker nitriding property such as Ti may be selected as the metal for improving the acid resistance.

【0028】本発明における配線材料は逆スタガー形の
TFTに限るものではなく、エッチングスットパー/逆
スタガー形、バックチャネル/逆スタガー形、スタガー
形TFTにおいても差し支えない。又、ゲート線に限ら
ず信号線等に用いても良い。また、TFTの半導体膜は
a−Si膜に限ったものではなく、ポリシリコン膜であ
っても何等差し支えない。
The wiring material in the present invention is not limited to the reverse stagger type TFT, but may be an etching stopper / reverse stagger type, back channel / reverse stagger type, or stagger type TFT. Further, it may be used not only as a gate line but also as a signal line or the like. Further, the semiconductor film of the TFT is not limited to the a-Si film, and may be a polysilicon film without any problem.

【0029】[0029]

【実施例】以下本発明の実施例を図面を参照して説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

【0030】(実施例1)図1乃至図3は本実施例をT
FTスイッチングを用いたアクティブマトリクス型液晶
表示装置に適用して示すものである。図1に示すよう
に、液晶表示装置10は、一方の面にITO(インジウ
ム錫酸化物)膜の透明共通電極13を形成したガラスの
観察側基板11と、一方の面にITO膜の透明画素電極
14を形成した対向基板12とを、各電極側の面を対面
させて配置する。
(Embodiment 1) FIG. 1 to FIG.
This is applied to an active matrix type liquid crystal display device using FT switching. As shown in FIG. 1, a liquid crystal display device 10 includes a glass observation-side substrate 11 having an ITO (indium tin oxide) film transparent common electrode 13 formed on one surface, and an ITO film transparent pixel on one surface. The counter substrate 12 on which the electrodes 14 are formed is arranged with the surfaces on the electrode sides facing each other.

【0031】両基板11、12は基板間隙剤を介して数
μmの間隙をおいて配置されて周縁を封着され、この間
隙に液晶層15が充填されて基板により挟持される。
The substrates 11 and 12 are arranged with a gap of several μm therebetween with a substrate gap agent and the peripheral edges are sealed. The liquid crystal layer 15 is filled in this gap and sandwiched by the substrates.

【0032】画素電極14のある対向基板12はマトリ
クス基板と称され、図3に示す回路と平面的に等価な2
次面配列で画素電極14、TFTスイッチング素子16
およびアドレス線(ゲート線)17、データ線18、蓄
積容量線19が配置される。
The counter substrate 12 having the pixel electrodes 14 is called a matrix substrate, and is a substrate equivalent to the circuit shown in FIG.
Pixel electrode 14 and TFT switching element 16 in the next surface arrangement
An address line (gate line) 17, a data line 18, and a storage capacitance line 19 are arranged.

【0033】すなわち、画面表示の行方向に延長された
n本のアドレス線17と列方向に延長されたm本のデー
タ線18とがマトリクス状に配置され、さらに各アドレ
ス線に平行に蓄積容量線19が配置される。
That is, n address lines 17 extending in the row direction of the screen display and m data lines 18 extending in the column direction are arranged in a matrix, and the storage capacitors are arranged in parallel with each address line. The line 19 is arranged.

【0034】アドレス線とデータ線が囲む領域単位にT
FTスイッチング素子16と画素電極14が形成され、
TFT16はアドレス線17とデータ線18に領域単位
の交差部で電気的に接続される。すなわち、TFTのド
レイン電極がデータ線18に、ソース電極が画素電極1
4に、ゲート電極がアドレス線17に接続される。、な
お、図において、符号15aは領域単位の液晶層部分す
なわち領域単位で画素電極14と共通電極13に挟まれ
た液晶層部分であり、各1画素を形成する。
T is a unit of the area surrounded by the address line and the data line.
The FT switching element 16 and the pixel electrode 14 are formed,
The TFT 16 is electrically connected to the address line 17 and the data line 18 at the intersection of the area units. That is, the drain electrode of the TFT is the data line 18, and the source electrode of the TFT is the pixel electrode 1.
4, the gate electrode is connected to the address line 17. In the figure, reference numeral 15a denotes a liquid crystal layer portion in a unit of area, that is, a liquid crystal layer portion sandwiched between the pixel electrode 14 and the common electrode 13 in a unit of region, and forms one pixel each.

【0035】図2はガラス基板12上のTFTスイッチ
ング素子16、アドレス線から一体的に延長されたゲー
ト電極線17a、蓄積容量線19の配置断面を拡大して
示すもので、ゲート電極線17aはCuとZrの合金か
らなる導電層20aとこれを被覆するZrN窒化層21
aからなる。ZrN層21aは導電層20aと基板12
間にも介在する。
FIG. 2 is an enlarged sectional view showing the arrangement of the TFT switching element 16 on the glass substrate 12, the gate electrode line 17a integrally extended from the address line, and the storage capacitance line 19, and the gate electrode line 17a is Conductive layer 20a made of an alloy of Cu and Zr and ZrN nitride layer 21 covering the conductive layer 20a
a. The ZrN layer 21a includes the conductive layer 20a and the substrate 12
Also intervenes in between.

【0036】同様に蓄積容量線19は、CuとZrの合
金からなる導電層20bとこれを被覆するZrN絶縁層
21bからなる。図2に図示しないがアドレス線17も
同時にパターン形成する。
Similarly, the storage capacitance line 19 is composed of a conductive layer 20b made of an alloy of Cu and Zr and a ZrN insulating layer 21b covering the conductive layer 20b. Although not shown in FIG. 2, the address line 17 is also patterned at the same time.

【0037】これら電極層17a、配線層17、19を
形成した基板上に、絶縁膜22が堆積され、その上面の
TFT領域に(a−Si)層16aが形成され、さら
に、ドレイン電極層16bおよびソース電極層16cが
形成される。一方、蓄積容量線19上の画素領域にIT
Oからなる画素電極14が形成され、ソース電極層16
cと電気的に接続される。ドレイン電極層16bは図2
では示しないが、データ線に電気的に接続される。
The insulating film 22 is deposited on the substrate on which the electrode layer 17a and the wiring layers 17 and 19 are formed, the (a-Si) layer 16a is formed in the TFT region on the upper surface thereof, and the drain electrode layer 16b is further formed. And the source electrode layer 16c is formed. On the other hand, in the pixel area on the storage capacitance line 19, the IT
The pixel electrode 14 made of O is formed, and the source electrode layer 16
It is electrically connected to c. The drain electrode layer 16b is shown in FIG.
Although not shown, it is electrically connected to the data line.

【0038】この構成のアドレス線17、ゲート電極線
17aおよび蓄積容量線19の製法をさらに説明する。
A method of manufacturing the address line 17, the gate electrode line 17a and the storage capacitance line 19 having this structure will be further described.

【0039】まず、ガラス基板12上にCuとZrを同
時にスパッタし,Zr10at%(原子%)のCuZr
合金膜を3000A(オングストローム)堆積させ、燐
酸系溶液によりエッチングを行って、線幅20μmのア
ドレス線17、線幅12μmのゲート電極線17aおよ
び線幅35μmの蓄積容量線19のCuZr合金層パタ
ーンを形成した。
First, Cu and Zr were simultaneously sputtered on the glass substrate 12, and Zr was 10 at% (atomic%) CuZr.
An alloy film is deposited at 3000 A (angstrom) and etched with a phosphoric acid solution to form a CuZr alloy layer pattern of an address line 17 having a line width of 20 μm, a gate electrode line 17a having a line width of 12 μm and a storage capacitor line 19 having a line width of 35 μm. Formed.

【0040】次に、メチルヒドラジン雰囲気中で400
℃で熱処理し、パターン中のZrを窒化し表面にZrN
の窒化層21a、21bを形成した。すなわち、この熱
処理によりCuZr合金層のZrが表面に拡散して窒化
してZrNの窒化層21a、21bになり内部のCuZ
r導電層20a、20b中のZrの密度は減少し2at
%になった。窒化層21a、21bは導電層と基板12
間にも形成された。導電層表面の窒化層の膜厚は100
0Aであった。
Next, 400 in a methylhydrazine atmosphere.
Heat treatment at ℃, nitriding Zr in the pattern, ZrN on the surface
And nitrided layers 21a and 21b were formed. That is, by this heat treatment, Zr of the CuZr alloy layer diffuses to the surface and is nitrided to form the ZrN nitride layers 21a and 21b, and the CuZr in the inside is
The density of Zr in the r conductive layers 20a and 20b is reduced to 2 at
%Became. The nitride layers 21a and 21b are the conductive layer and the substrate 12
Also formed in between. The thickness of the nitride layer on the surface of the conductive layer is 100.
It was 0A.

【0041】次にプラズマCVD法により絶縁膜22と
して3000AのSiOx22a、500AのSiNx
22bを積層し、さらにアンドープ(a−Si)16a
を1000A、ストッパーSiNx16dを2000A
堆積した。ストッパーSiNxをエッチングした後、n
の(a−Si)16eを500A堆積した。Moを5
00A堆積した後にパターニングしてa−Siの島を形
成した。ITO画素電極14を形成した後にコンタクト
ホールを開口した。この後、ドレイン電極層16bおよ
びソース電極層16cとなるMo層を500A,Al層
を0.5μm堆積した後、Alエッチング液により、同
ドレイン電極16b及びソース電極16cを形成した。
このアルミAl層0.5μmの形成時に、同時にデータ
線パターンを形成しておき、データ線18をAlで形成
する。
Next, the plasma CVD method is used as the insulating film 22 to form 3000A of SiOx 22a and 500A of SiNx.
22b are stacked, and further undoped (a-Si) 16a
1000A, stopper SiNx16d 2000A
Deposited. After etching the stopper SiNx, n
+ (A-Si) 16e was deposited at 500 A. Mo 5
After depositing 00A, patterning was performed to form a-Si islands. After forming the ITO pixel electrode 14, a contact hole was opened. Thereafter, a Mo layer serving as the drain electrode layer 16b and the source electrode layer 16c was deposited to 500 A and an Al layer was deposited to 0.5 μm, and then the drain electrode 16b and the source electrode 16c were formed by an Al etching solution.
A data line pattern is formed at the same time when the aluminum Al layer of 0.5 μm is formed, and the data line 18 is formed of Al.

【0042】次にn(a−Si)16eをCDEによ
りエッチングし、次いでSiNxの保護膜を形成し、コ
ンタクト部に開口を設けてTFTアレイを完成した。
Next, the n + (a-Si) 16e was etched by CDE, then a protective film of SiNx was formed, and an opening was provided in the contact portion to complete the TFT array.

【0043】このように構成された液晶駆動用マトリク
ス基板12では、アドレス線として従来用いられている
Mo−Ta合金等の抵抗率約30〜45μΩcmに比
べ、10μΩcm未満と1/3〜1/4以上も小さい値
が得られ、従来よりもアドレス線の幅を小さくできるた
め開口率の拡大がはかれ、また従来より大面積,高精
細,高画質の液晶ディスプレイに対応して配線長の増大
にも対応できる。また、表面の窒化によりITO,A
l,SiOx,SiNxエッチング溶液に対する耐性も
向上しているために、Al,Cuやこれらの合金をゲー
ト線に用いた場合に比べ、断線による欠陥が飛躍的に減
少した。
In the liquid crystal driving matrix substrate 12 thus constructed, the resistivity of the Mo-Ta alloy or the like which has been conventionally used as the address line is about 30 to 45 μΩcm, which is less than 10 μΩcm and 1/3 to 1/4. A smaller value is obtained, and the aperture ratio can be expanded because the width of the address line can be made smaller than in the past, and the wiring length can be increased in response to large area, high definition, and high image quality liquid crystal displays. Can also handle. Also, due to the nitriding of the surface, ITO, A
Since the resistance to the 1, l, SiOx, and SiNx etching solutions is also improved, defects due to disconnection are dramatically reduced as compared with the case where Al, Cu, or an alloy thereof is used for the gate line.

【0044】(実施例2)実施例1と同様にAuに10
at%Zrを添加した。AuはCuに比べて耐酸性が良
いため内部にZrを残す必要がないため、430℃で時
間を長くして十分にZrを窒化した。内部のZr量は
0.5しょうR融点が低いためCuよりat%以下であ
った。これにより抵抗率は3μΩcm以下と十分に低く
できた。
(Example 2) As in Example 1, 10
at% Zr was added. Since Au has better acid resistance than Cu, it is not necessary to leave Zr inside, so that the time was lengthened at 430 ° C. to sufficiently nitride Zr. The amount of Zr in the inside was at% or less than that of Cu because the melting point of 0.5 R was low. As a result, the resistivity could be sufficiently lowered to 3 μΩcm or less.

【0045】(実施例3)実施例1と同様にAlに10
at%Zrを添加した。AlはCuに比べて融点が低い
ためCuより低い300〜350℃で窒化できた。内部
のZr量は2at%であった。これにより抵抗率は10
μΩcm以下であった。
(Embodiment 3) Al in the same manner as in Embodiment 1
at% Zr was added. Since Al has a lower melting point than Cu, it could be nitrided at 300 to 350 ° C., which is lower than Cu. The internal Zr amount was 2 at%. This gives a resistivity of 10
It was μΩcm or less.

【0046】(実施例4)実施例1と同様にCuに10
at%Zr、3at%Tiを添加した。400℃で窒化
したところ、Zrは窒化しやすいためほぼ全部が表面で
窒化し、内部には2.5at%のTiが残り、実施例1
に比べ内部のTi量をよく制御できた。抵抗率は10μ
Ωcm以下と低くできた。
(Embodiment 4) As in Embodiment 1, Cu is added to 10
At% Zr and 3 at% Ti were added. When nitrided at 400 ° C., since Zr is easily nitrided, almost all is nitrided on the surface, and 2.5 at% of Ti remains inside.
The amount of Ti inside could be controlled better than that of Resistivity is 10μ
It was as low as Ωcm or less.

【0047】(実施例5)実施例1と同様にCuに10
at%Hf、3at%Taを添加した。400℃で窒化
したところ、HfはZrよりも窒化しやすく、TaはT
iよりも窒化しにくいためHfはほぼ全部が表面で窒化
し、内部には3at%のTaが残り、実施例4に比べて
内部のTa量をさらに良く制御できた。抵抗率は10μ
Ωcm以下と低くできた。
(Embodiment 5) As in Embodiment 1, Cu is added to 10
At% Hf and 3 at% Ta were added. When nitrided at 400 ° C, Hf is easier to nitride than Zr and Ta is T
Since nitriding is more difficult than i, almost all of Hf is nitrided on the surface, and Ta of 3 at% remains inside, so that the amount of Ta inside can be controlled better than in Example 4. Resistivity is 10μ
It was as low as Ωcm or less.

【0048】(実施例6)実施例1と同様にAuに1a
t%Tiを添加した。430℃で十分に窒化し、Tiを
ほぼ全部表面で窒化し内部には初期の添加量とほとんど
変わらない1at%のTiが残り、実施例5に比べて内
部のTi量をさらに良く制御できた。抵抗率は3μΩc
m以下と低くできた。
(Example 6) As in Example 1, 1a was added to Au.
t% Ti was added. Sufficiently nitriding at 430 ° C., nitriding Ti almost entirely on the surface, and 1 at% Ti, which is almost the same as the initial addition amount, remained inside, and the amount of Ti in the inside could be controlled better than in Example 5. . Resistivity is 3μΩc
It was as low as m or less.

【0049】(実施例7)実施例1と同様にAl0メチ
ルヒドラジンで300〜350℃で窒化した。Alを用
いたため窒化温度を十分に低温化できた。表面は窒化し
内部はAlであった。Alを用いたため抵抗率は3μΩ
cm以下とほぼAlと等しい値まで十分に低くできた。
(Example 7) As in Example 1, nitriding was performed with Al0 methylhydrazine at 300 to 350 ° C. Since Al was used, the nitriding temperature could be lowered sufficiently. The surface was nitrided and the inside was Al. Resistivity is 3μΩ because Al is used
It could be sufficiently lowered to a value equal to or less than cm and almost equal to Al.

【0050】[0050]

【発明の効果】以上述べたように、本発明に係わる配線
材料は、低抵抗性を具備しかつ、後工程における高耐薬
品特性をも具備し、しかも低温処理が必要なガラス基板
への被着性がよい。したがって、各種電子部品の信号用
配線に利用した場合良好な機能発揮に大きく寄与する。
また、液晶装置の信号配線や実装する駆動用半導体素子
の電極の形成として用いた場合は、低抵抗なアドレスラ
イン等を実現できる。さらに、この配線層は液晶表示装
置製造工程でのパターニングやエッチングを増やさずに
熱処理のみで得られ、しかもその後の熱処理構成やエッ
チング工程を経ても低抵抗配線層として優れた特性を発
揮する。
As described above, the wiring material according to the present invention has a low resistance and a high chemical resistance property in the post-process, and it can be applied to a glass substrate requiring a low temperature treatment. Good wearability. Therefore, when it is used for signal wiring of various electronic components, it greatly contributes to good performance.
Further, when it is used for forming a signal wiring of a liquid crystal device or an electrode of a driving semiconductor element to be mounted, a low resistance address line or the like can be realized. Further, this wiring layer can be obtained only by heat treatment without increasing patterning or etching in the liquid crystal display device manufacturing process, and exhibits excellent characteristics as a low resistance wiring layer even after the subsequent heat treatment structure or etching process.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の液晶表示素子の概略断面図。FIG. 1 is a schematic cross-sectional view of a liquid crystal display element of an embodiment of the present invention.

【図2】本発明の実施例の要部を拡大して示す断面図。FIG. 2 is a cross-sectional view showing an enlarged main part of the embodiment of the present invention.

【図3】本発明の実施例のアクティブマトリクス型液晶
表示素子の等価回路図。
FIG. 3 is an equivalent circuit diagram of an active matrix type liquid crystal display element according to an embodiment of the present invention.

【図4】従来例のアクティブマトリクス型基板の要素構
成を示す断面図。
FIG. 4 is a sectional view showing an element structure of a conventional active matrix type substrate.

【符号の説明】[Explanation of symbols]

11…観察側基板 12…対向基板 13…透明共通電極 14…透明画素電極 15…液晶層 16…TFTスイッチング素子 17…アドレス線 17a…ゲート電極線 18…データ線 19…蓄積容量線 20a、20b…導電層 21a、20b…窒化層 11 ... Observation-side substrate 12 ... Counter substrate 13 ... Transparent common electrode 14 ... Transparent pixel electrode 15 ... Liquid crystal layer 16 ... TFT switching element 17 ... Address line 17a ... Gate electrode line 18 ... Data line 19 ... Storage capacitance line 20a, 20b ... Conductive layers 21a, 20b ... Nitriding layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 一対の基板と、これら基板間に挟持され
る液晶層と、前記基板の前記液晶層側の表面に形成され
る電極および前記電極に電気的に接続され前記基板の表
面に配設される配線層とを具備する液晶表示装置におい
て、少なくとも前記配線層がCu、Al、Ag、Au、
Ptから選ばれた少なくとも一種の第1の金属を主体に
し、Ti、Zr、Hf、Al、Ta、Si、Bから選ば
れた少なくとも一種の第2の金属を添加してなる導電層
と、この導電層の表面を被覆する、前記第2の金属の窒
化物層とを有することを特徴とする液晶表示装置。
1. A pair of substrates, a liquid crystal layer sandwiched between the substrates, an electrode formed on the surface of the substrate on the liquid crystal layer side, and an electrode electrically connected to the electrode and arranged on the surface of the substrate. In a liquid crystal display device including a wiring layer provided, at least the wiring layer includes Cu, Al, Ag, Au,
A conductive layer mainly composed of at least one first metal selected from Pt and added with at least one second metal selected from Ti, Zr, Hf, Al, Ta, Si and B; A liquid crystal display device, comprising: the second metal nitride layer covering the surface of the conductive layer.
JP5229795A 1995-03-13 1995-03-13 Liquid crystal display device Pending JPH08248442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5229795A JPH08248442A (en) 1995-03-13 1995-03-13 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5229795A JPH08248442A (en) 1995-03-13 1995-03-13 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH08248442A true JPH08248442A (en) 1996-09-27

Family

ID=12910870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5229795A Pending JPH08248442A (en) 1995-03-13 1995-03-13 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH08248442A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6043859A (en) * 1996-11-28 2000-03-28 Nec Corporation Active matrix base with reliable terminal connection for liquid crystal display device
WO2001093320A1 (en) * 2000-06-01 2001-12-06 Korea Institute Of Science And Technology Platinum electrode structure for semiconductor and method for enhancing adhesion between semiconductor substrate and platinum electrode
JP2003031588A (en) * 2001-07-19 2003-01-31 Sony Corp Manufacturing method for thin-film semiconductor device, and manufacturing method for display device
JP2004093746A (en) * 2002-08-30 2004-03-25 Advanced Display Inc Liquid crystal display
US6744070B2 (en) 1998-09-03 2004-06-01 Sharp Kabushiki Kaisha Thin film transistor and liquid crystal display device
KR100471770B1 (en) * 1996-12-23 2005-06-17 삼성전자주식회사 LCD Display
KR100635949B1 (en) * 2000-09-04 2006-10-18 삼성전자주식회사 A wire structure and a method of manufacturing the same, and a thin film transistor substrate including the wire structure and a method of manufacturing the same
KR100670051B1 (en) * 1999-12-01 2007-01-16 삼성전자주식회사 A thin film transistor array panel and a manufacturing method thereof
JP2008203808A (en) * 2006-09-08 2008-09-04 Mitsubishi Materials Corp Wiring and electrode for flat panel display using tft transistor free from thermal defect generation and having excellent adhesiveness and sputtering target for forming the same
US7528466B2 (en) 2004-12-29 2009-05-05 Au Optronics Corp. Copper gate electrode of liquid crystal display device and method of fabricating the same
US7821009B2 (en) 2004-12-07 2010-10-26 Samsung Electronics Co., Ltd. Signal line, a thin film transistor array panel comprising the signal line, and method for manufacturing the same
JP2011232507A (en) * 2010-04-27 2011-11-17 Hitachi Displays Ltd Display device
US8304299B2 (en) 2009-11-10 2012-11-06 Samsung Display Co., Ltd. Thin film transistor substrate and manufacturing method thereof

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6043859A (en) * 1996-11-28 2000-03-28 Nec Corporation Active matrix base with reliable terminal connection for liquid crystal display device
KR100471770B1 (en) * 1996-12-23 2005-06-17 삼성전자주식회사 LCD Display
US6744070B2 (en) 1998-09-03 2004-06-01 Sharp Kabushiki Kaisha Thin film transistor and liquid crystal display device
KR100670051B1 (en) * 1999-12-01 2007-01-16 삼성전자주식회사 A thin film transistor array panel and a manufacturing method thereof
WO2001093320A1 (en) * 2000-06-01 2001-12-06 Korea Institute Of Science And Technology Platinum electrode structure for semiconductor and method for enhancing adhesion between semiconductor substrate and platinum electrode
KR100635949B1 (en) * 2000-09-04 2006-10-18 삼성전자주식회사 A wire structure and a method of manufacturing the same, and a thin film transistor substrate including the wire structure and a method of manufacturing the same
JP4650656B2 (en) * 2001-07-19 2011-03-16 ソニー株式会社 Thin film semiconductor device manufacturing method and display device manufacturing method
JP2003031588A (en) * 2001-07-19 2003-01-31 Sony Corp Manufacturing method for thin-film semiconductor device, and manufacturing method for display device
JP2004093746A (en) * 2002-08-30 2004-03-25 Advanced Display Inc Liquid crystal display
US7821009B2 (en) 2004-12-07 2010-10-26 Samsung Electronics Co., Ltd. Signal line, a thin film transistor array panel comprising the signal line, and method for manufacturing the same
US8507303B2 (en) 2004-12-07 2013-08-13 Samsung Display Co., Ltd. Thin film transistor array panel and method for manufacturing the same
US7528466B2 (en) 2004-12-29 2009-05-05 Au Optronics Corp. Copper gate electrode of liquid crystal display device and method of fabricating the same
US7829393B2 (en) 2004-12-29 2010-11-09 Au Optronics Corp. Copper gate electrode of liquid crystal display device and method of fabricating the same
JP2008203808A (en) * 2006-09-08 2008-09-04 Mitsubishi Materials Corp Wiring and electrode for flat panel display using tft transistor free from thermal defect generation and having excellent adhesiveness and sputtering target for forming the same
US8304299B2 (en) 2009-11-10 2012-11-06 Samsung Display Co., Ltd. Thin film transistor substrate and manufacturing method thereof
US8686423B2 (en) 2009-11-10 2014-04-01 Samsung Display Co., Ltd. Thin film transistor substrate and manufacturing method thereof
JP2011232507A (en) * 2010-04-27 2011-11-17 Hitachi Displays Ltd Display device

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