KR100297861B1 - Solid-state device with thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a solid state device having a thin-film transistor and its manufacturing step with improved yield and reliability, by using a wiring-layer structure that is preventive against annealing and wet-etching steps in a thin-film transistor manufacturing step. CONSTITUTION: A thin-film transistor 50 on a main face of a substrate 40 includes a gate electrode 53 and a gate wiring layer 60. The gate electrode 53 and the gate wiring layer 60 are made up of a lower polysilicon layer 61, a molybdenum silicide layer 62, and an upper polysilicon layer 63. In this case, the upper polysilicon layer 63 is used as an etching stopper when a wet-etching step is carried out for a layer insulating film 57 to form first, second and third connecting holes 651, 671, and 661.

Description

Method of manufacturing multilayer conductor system

1 is a plan view showing a thin film transistor and a gate wiring layer formed on an active matrix substrate of an embodiment of the present invention.

2 (a) to 2 (f) are cross-sectional views of a process showing process steps of a thin film transistor and a gate wiring layer.

3 is a block diagram showing the overall configuration of a liquid crystal display panel using the active matrix substrate shown in FIG.

4 (a) is a circuit diagram of a shift register formed on the active matrix substrate shown in FIG.

4 (b) is a circuit diagram of an inverter.

4 (c) and 4 (d) are circuit diagrams of a clocked inverter.

5 is a plan view showing a conventional thin film transistor and its gate wiring layer.

6 is a state diagram around the contact hole in the gate wiring layer of the prior art.

FIG. 7 is a cross sectional view taken along the line 7-7 in FIG.

8 is a cross sectional view taken along the line 8-8 in FIG.

9 is a cross sectional view taken along the line 9-9 in FIG.

The present invention relates to thin film transistor structures and methods of fabrication, in particular to structures and methods for protecting underlying wiring layers from the undesirable consequences of annealing and wet etching.

Thin film transistors (TFTs) with high on-off ratios and fast response are often used as switching elements to achieve high contrast characteristics. TFTs are commonly used in active matrix substrates for liquid crystal panels and circuit boards for image sensors.

As shown in FIG. 5, the TFT is performed using an undoped silicon layer 501a formed on the surface of the substrate 40a, a gate oxide film 55a formed on the surface thereof, and a gate electrode 53a as a mask. It has a source region 51a and a drain region 52a formed by manufacturing a portion of the silicon layer 501a that is conducted by ion implantation.

In the liquid crystal panel, a plurality of pixels are arranged in a matrix on the surface of the substrate 40a and an image is displayed by switching the display state of each pixel. Therefore, if the display operation of a particular pixel is delayed, the display quality is significantly reduced.

A wiring material having a low electrical resistance is commonly used for the gate wiring layer 60a. In addition, since the gate wiring layer 60a is formed at the same time as the gate electrode 53a of the thin film transistor 50a, it is preferable that the gate electrode 53a on the wiring material constituting the gate wiring layer 60a can be formed. .

Therefore, the gate wiring layer 60a and the gate electrode 53a are formed of two layers including the lower polysilicon layer 61a and the upper molybdenum silicide 62a in the active matrix substrate shown in FIGS. 5 and 7. It is formed as a structure. In addition, the source electrode 65a is electrically coupled to the source region 51a of the thin film transistor 50a via the first contact hole 651a in the interlayer insulating film 57a. The upper wiring layer 66a is electrically coupled to the gate wiring layer 60a via the second contact hole 662a in the interlayer insulating film 57a.

In the production process of the active matrix substrate having the TFT (boa) and the gate wiring layer 6oa as the above configuration, ion implantation is performed using the gate electrode 53a as a mask to form the source and drain regions 51a and 52a. All. The implanted impurities need to be activated by high temperature process steps. In addition, since the grain diameter of the interlayer insulating film 57a is too coarse when formed by the CVD method, it is necessary to make the grain better quality, which is also done as a high temperature process step. Therefore, the process step is performed when all of the substrates 40a are annealed at silver higher than about 1000 degrees Celsius, so that the interlayer insulating film 57a is of high quality while the impurity ions implanted in the silicon layer 501a are activated.

However, in the structure of the gate electrode 53a and the gate wiring layer 60a of the prior art, the change of the molybdenum silicide layer 62a due to the annealing process causes abnormal etching of the interlayer insulating film 57a during the subsequent wet etching step. do. That is, when the molybdenum silicide layer 62a is annealed in an atmosphere of approximately 1000 degrees Celsius, large grains 62c are grown as shown in FIG. Therefore, when the second contact foil 661a is formed in the interlayer insulating film 57a by wet etching, the etchant can easily penetrate into the molybdenum silicide layer 62a along the grain boundary 62b and the etchant is grained. It can easily penetrate into the lower silicon 61a along the grain boundary 61b generated to coincide with the boundary 62b, and the etching developed from the region penetrated by the etching liquid causes defects in the substrate 40a in the vertical direction ( A defect 57b of the interlayer insulating film 57a is generated in the horizontal direction with 40b. It causes an increase in electrical resistance and opens the circuit of the gate wiring layer 60, thereby lowering the yield and stability of the active matrix substrate.

Tungsten silicide layers are described in J. Electrochem. Soc. When used as reported in Solid Science and Technology, 1981, Vol. 128, No. 10, 2208-2212, that kind of problem arises.

There is a need for a thin film transistor structure and production method that can improve yield and stability by eliminating the overetching and consequent yield issues resulting from the annealing and wet etching steps.

The polysilicon layer doped with an impurity may be used as a protective layer that is at least conductive to the metal silicide layer in the region where the contact hole is etched. In addition, the gate electrode of the thin film transistor has a multilayer structure composed of the same layer as the lower wiring layer, and the gate electrode and the lower wiring layer of the thin film transistor may be simultaneously formed. At this time, in order to alleviate the stress effect between the gate insulating film and the gate electrode of the thin film transistor, it is preferable to form the lower surface of the gate electrode and the lower wiring layer from the polysilicon layer.

In the solid state device having the above structure, the lower wiring layer is a gate wiring layer diffused from the gate electrode of the TFT, and the lower wiring layer and the thin film transistor can be used to form an active matrix for a display panel on the substrate surface. The scanning line of the active matrix is constructed from the gate wiring layer and it can be used as the black matrix.

A production method for a solid-state device provided as a thin film transistor having the above structure comprises forming a region on a substrate surface including a process gate electrode for forming a gate insulating film of the thin film transistor on the surface of a semiconductor region on the substrate surface and a region in which a lower wiring layer is formed. Laminating each layer, patterning all of the layers together, forming a gate electrode and a lower wiring layer, and forming source-drain regions of the thin film transistor on the semiconductor region by introducing impurities from the surface, on the surface Forming an interlayer insulating film, annealing the minimum region where the thin film transistor and the lower wiring layer are formed; forming a contact hole by wet etching of the interlayer insulating film with an etching solution after the photoresist layer is patterned on the etched angle. Mold the upper wiring layer And a step for.

In the present invention, the lower wiring layer has a heat resistant and conductive protective film on the upper surface of the metal silicide layer.

The heat resistant and conductive protective film is resistant to the etchant used to form the contact hole in the interlayer insulating film.

Therefore, the interlayer insulating film is wet etched to form a contact hole, and the etching after annealing is stopped by the conductive protective film. It consequently improves yield and stability by preventing the occurrence of abnormal etching.

Other objects, advantages and advantages as well as a more complete understanding of the present invention will become apparent and appreciated by reference to the following description and claims, which are associated with the accompanying drawings.

In the active matrix liquid crystal display panel of FIG. 3, the pixel matrix 22, the signal line driver circuit 12 and the scanning line driver circuit 21 are formed on the same transparent substrate 11, whereby the display device is more precise and inexpensive. It can be manufactured by miniaturization. The signal line driver circuit 12 includes a shift register 13, sample and hold circuits 17, 18, 19 and video signal lines 14, 15, 16. The scanning line driver circuit 21 includes a shift register 20 and a buffer circuit 23. The pixel matrix 22 includes a plurality of signal lines 26, 27, and 28 coupled to the signal line driver circuit 12, a plurality of scanning lines 24 and 25 and a scanning line coupled to the scanning line driver circuit 21. And a plurality of pixels 32 and 33 formed at the intersections of the signal lines with each other, and each of the pixels 32 and 33 includes a TFT 29 and a liquid crystal cell 30. The clock signal line 34 for inputting the clock signal to the shift register 13 is disposed on the side toward the signal line driver circuit 12, while the clock signal line for inputting the clock signal to the shift register 20 ( 37 is disposed on the side toward the scanning line driver circuit 21. The start signal lines 35 and 38 input a start signal to the signal line drive circuit 12 and the scanning line drive circuit 21.

In addition to the TFTs 29 formed in the respective pixels 32 and 33, a plurality of TFTs are formed on the active matrix substrate and joined to each other by wiring on the gate wiring layer. For example, in the shift register 20, the unit shift register is clocked inverters 3a and 4a or clocks driven by non-overlapping clock signals CLA and CLA, as shown in FIG. 4 (a). The inverters 3b and 4b, and the inverter 2 has a CMOS structure made of the p-channel TFT 201 and the n-channel TFT 202 shown in FIG. 4 (b). In addition, the clocked inverters 3a and 4a use two p-channel gate wiring layers 60a TFTs 301a and 372a and n-channel TFTs 401a and 402a as shown in FIG. 4 (c). On the other hand, the clocked inverters 3b and 4b have two P-channel TFTs 301a and 302a and n-channel TFTs 401a and 402a, as shown in FIG. 4 (d). Further, based on the bit output signal output from the shift register, each pixel 29, 30 performs a display operation to form a prescribed image. Therefore, when the electrical resistance of the scanning lines 24 and 25 for driving the TFTs 29 of the respective pixels 32 and 33 is high, the pixels in the cross section of the substrate 11 arranged in the matrix, for example, the TFTs The display operation of (27) is delayed, thereby lowering the display quality of the video. Further, the display quality of the image is lowered when the electrical resistance of the gate wiring layer connecting the TFTs of the respective shift registers 13 and 20 is high, and a delay occurs at the input-output timing of the signal of the specific unit shift register. .

In order to solve the above problem, a TFT and a gate wiring layer having the following configuration are used in the active matrix substrate of the above embodiment.

1, 8 and 9, the substrate 40 is a transparent glass substrate for an active matrix substrate and a silicon layer 501 is present on its surface. The silicon layer 501 has a thickness of between 300 and 600 microseconds. have.

The source region 51 and the drain region 52 are formed by ion implantation of phosphorous such as n-type impurities using the gate electrode 53 formed on the gate oxide film 55 on the surface of the silicon layer 501 such as a mask. Both ends of the conductive silicon layer 501 and the gate oxide film 55 are formed and arranged, and the gate electrode 53, the source region 51, and the drain region 52 form a TFT 50. It forms an n-channel transistor, and as is known by those skilled in the art, a p-channel transistor is formed by implanting boron (B) instead of phosphorus (P). In particular, the (P), such as ₃₁ P ⁺ are implanted at a dose of energy and 1E15 / cm ² 90keV boron, such as ₁₁ B ⁺ are implanted at a dose of energy 40keV and 1E15 / cm ^2. In addition, an interlayer insulating film 57 is formed on the surface of the TFT 50, and the source electrode 65 is electrically coupled to the source region 51 of the TFT 50 via the first contact hole 651. The drain electrode 67 is electrically coupled to the drain region 52 via the third contact hole 671.

When the TFT 50 is used as the switching element for the pixel region, the aluminum electrode can be replaced by the drain electrode 67 and the ITO layer can be used with the partial change of the required structure.

The gate wiring layer 60 formed as a single unit together with the gate electrode 53 has an upper portion via the second contact hole 661 formed in the interlayer insulating film 57 from the region where the TFT 50 is formed and electrically coupled. It extends to the wiring layer 66.

The gate wiring layer 60 includes a lower polysilicon layer 61 approximately 1000 microns thick, a molybdenum silicide layer 62 (metal oxide layer) approximately 2000 microns thick and an upper polysilicon layer 63 approximately 1000 microns thick (conductive Protective layer). In addition, since the gate wiring layer 60 and the gate electrode 53 are simultaneously formed in one unit, the gate electrode 53 has a lower polysilicon layer 61 having a thickness of about 1000 mW and a molybdenum silicide layer 62 having a thickness of about 2000 mW. ) And an upper polysilicon layer 63 of approximately 1000 microns thick.

The reason for providing the molybdenum silicide layer 62 on the gate wiring layer 60 is to reduce the electrical resistance of the gate wiring layer 60. The resistance of the gate wiring layer 60 is reduced to prevent signal delays that would otherwise result.

The reason for providing the upper polysilicon layer 63 on the gate wiring layer 60 is to control the size of the wet etching resulting from the grain boundary formed in the molybdenum silicon layer 62 by annealing. To avoid negative consequences. That is, when annealing is formed in the process of producing the TFT 50 and the gate wiring layer 60, the grains in the molybdenum silicide layer 62 are largely grown in the boundary, and the grain boundary is the interlayer insulating film 57 Has a low resistance to penetrate the etchant, and the etchant penetrates along the grain boundary where the top surface of the molybdenum silicide layer 62 is exposed, resulting in abnormal etching. To prevent it, the upper polysilicon layer 63, which is not affected by the grain boundaries of the molybdenum silicide layer 62 and reacquires high resistance for etching by the etching liquid and etching by the etching liquid, is used as a stopper for wet etching. acts as a stopper and prevents abnormal etching.

Further, if the gate wiring layer 60 does not pass light, the scanning lines 24 and 25 of the active matrix shown in FIG. 3 can be constructed from the gate wiring layer 60, which is used as the black matrix for the liquid crystal display panel. By being used, the black matrix can form the pixels 32 and 33 with high positional precision, thereby improving the display quality of the liquid crystal display panel. In addition, the gate wiring layer 60 and the gate electrode 53 include the lower polysilicon layer 61 as the lowest layer, and the stress effect on the gate oxide film 55 is small and the gate wiring layer 60 is reduced. Suitable multilayer structures may also be applied to the gate electrode 53.

The method of producing an active matrix substrate having this kind of configuration is explained using Figs. 2 (a) to 2 (f) which are cross sectional views of a process showing the TFT and gate wiring layer forming steps of the present invention.

First, as shown in FIG. 2 (a), the gate oxide film 55 is thermally oxidized or electron cyclotron resonant chemical vapor on the silicon layer 501 formed in the region on the surface of the substrate 40 on which the TFT 50 is formed. It is formed by deposition (ECRCVD) technology.

Next, the undoped polysilicon 61 constituting the lower portion of the gate electrode 53 and the gate wiring layer 60 is, for example, by an LPCVD technique using Si ₂ H ₆ at approximately 600 degrees Celsius and low pressure. After being formed to about 1000 mm thick on all surfaces of the substrate 40, the molybdenum layer 62 is formed to about 2000 mm thick on its surface by sputtering techniques and the polysilicon layer 63 is subjected to CVD techniques. It is formed on its surface to a thickness of about 1000 mm 3. In this state, the sheet resistance of the layer is 40 to 50 Ω / square. Impurity doped polysilicon may be used in the polysilicon layer 63, or undoped polysilicon may be used by the introduction of impurities in subsequent processing steps and then becomes conductive. An impurity doped polysilicon layer may also be used for the polysilicon layer 61.

The composite of molybdenum silicide layer 62 may be a molybdenum-rich composite beyond that indicated by Mosi ₂ .

Next, the polysilicon layer 61, molybdenum silicide layer 62, and polysilicon layer 63 are simultaneously patterned by photoetching using a resist mask having a mask pattern set on the surface of the polysilicon layer 63. The gate electrode 53 and the gate wiring layer 60 are left as shown in FIGS. 1, 8, 9 and 2 (c).

Next, as shown in FIG. 2 (d), ion implantation or shower doping of phosphorus (P) like n-type impurities from the surface is performed to make a conductive silicon layer 501 portion and As shown in FIG. 1, FIG. 8, and FIG. 9, the source region 51 and the drain region 52 of the TFT 50 are formed. Shower doping is similar to ion implantation but without mass separation.

Next, as shown in FIG. 2 (e), an interlayer insulating film 57 which is a silicon oxide film is formed on the surface by CVD technique.

Next, both the minimum region where the TFT 50 and the gate wiring layer 60 are formed, that is, the substrate 40, are both annealed in a nitrogen gas atmosphere at approximately 1000 degrees Celsius for approximately 20 minutes. The annealing drops the sheet resistance of the gate wiring layer 60 from approximately 40-50 Ω / square to 4-5 Ω / square. It also activates impurities introduced into the source and drain regions 51 and 52 and makes the interlayer insulating film 57 more compact.

Next, as shown in FIG. 2 (f), its surface covered by the resist mask 571, which is a mask pattern defined for forming the first, second and third contact holes 651, 661 and 671, is shown. The interlayer insulating film 57 having is wet-etched by, for example, a fluorine (F) etching solution. As used herein, the fluorine etching solution is hydrofluoric acid. An etchant mixture of HF and NH ₄ F (1: 6) is commonly used at room temperature.

An aluminum layer is formed on all surfaces of the interlayer insulating film 57, the aluminum layer is patterned, and the upper wiring layer 66, the source electrode 65, and the drain electrode 66 are shown in FIGS. 1, 8, and 9 It is formed as shown in the figure.

As explained above, the structure is used in the production method of the active matrix substrate of the above embodiment, which provides the molybdenum silicide layer 62 to the gate wiring layer 60 and reduces the electrical resistance of the gate wiring layer 60, Silicon layer 63 functions like an etch stopper to prevent abnormal etching even though large grains grow in the molybdenum silicide layer 62 resulting in annealing causing the etching solution to easily penetrate along the grain boundaries. Do it. For this reason, the electrical resistance of the gate wiring layer 60 is small, thereby preventing the delay of the display operation in the pixel and improving the display quality. In addition, since abnormal etching is prevented, increased electrical resistance and open circuit in the gate wiring layer 60 are not generated, and show high yield and stability.

The present invention relates to an image sensor having a lower wiring layer formed of a TFT at least a metal silicide layer or a metal layer having a high melting point, and an upper wiring layer electrically coupled to a lower wiring layer through a contact hole in an interlayer insulating film. It can also be applied to circuit boards for other applications. Further, the structure is used in this embodiment in which a polysilicon layer is provided on both the gate wiring layer (lower wiring layer) and the gate electrode of the TFT on the layer surface of the top of the metal silicide layer, but the structure is a polysilicon layer or other conductive, protective film. Silver is used to be provided only in the lower wiring layer connected to the conductivity in the upper wiring layer via the contact hole in the interlayer insulating film. Molybdenum layers, tungsten layers or other high melting metal layers may also be used in place of or in addition to the metal silicide layers.

While the invention has been described in connection with many specific embodiments, numerous additional alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Therefore, the invention described herein is intended to embrace all alternatives, modifications, applications and variations consistent with the spirit and scope of the appended claims.

Claims (6)

A method of manufacturing a multilayer conductor system that functions as a black matrix of a display panel, comprising the steps of: a) providing a substrate, b) forming an undoped film of semiconductor material on the substrate, c) Patterning an undoped film; d) forming a gate insulating film on exposed surfaces of the undoped semiconductor material; e) forming a first conductive layer on the substrate and the gate insulating film; f) forming a second conductive layer on the first conductive layer, g) forming a third conductive layer on the second conductive layer, and h) applying a photoresist layer on the third conductive layer; Patterning the photoresist layer, i) etching the third, second and first conductive layers using the patterned photoresist as a mask to form a gate electrode and a gate wiring layer J) implanting impurity ions into the undoped film of the semiconductor material using the gate electrode as a mask to form a source region and a drain region of the thin film transistor; k) the substrate, the thin film transistor, and the gate. Forming an insulating film on the wiring layer, l) annealing the first, second and third conductive layers, m) forming a contact hole of the insulating film by wet etching; and n) forming an upper wiring layer on said patterned insulating film. The method of claim 1, wherein the substrate is a transparent glass, the undoped film of the semiconductor material is a polysilicon film, the first conductive layer is a polysilicon film of about 1,000 GPa thick, and the third conductive layer is about 1,000 GPa A polysilicon film having a thickness, wherein the insulating film is a silicon oxide film. The method of claim 2, wherein the second conductive layer is about 2,000 mm thick and is a material selected from the group consisting of molybdenum and tungsten. The method of claim 2, wherein the second conductive layer is a high melting point metal. The method of claim 1, wherein forming the first conductive film comprises depositing polysilicon from Si ₂ H ₆ in a low pressure atmosphere at about 600 ° C. ₃ . The method of claim 5, wherein the annealing comprises inserting the substrate and the layers formed on the substrate into a furnace at about 1,000 ° C. for about 20 minutes.