JPH05326960A - Solid-state device with thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a solid state device having a thin-film transistor and its manufacturing step with improved yield and reliability, by using a wiring-layer structure that is preventive against annealing and wet-etching steps in a thin-film transistor manufacturing step. CONSTITUTION:A thin-film transistor 50 on a main face of a substrate 40 includes a gate electrode 53 and a gate wiring layer 60. The gate electrode 53 and the gate wiring layer 60 are made up of a lower polysilicon layer 61, a molybdenum silicide layer 62, and an upper polysilicon layer 63. In this case, the upper polysilicon layer 63 is used as an etching stopper when a wet-etching step is carried out for a layer insulating film 57 to form first, second and third connecting holes 651, 671, and 661.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state device having a thin film transistor and a method of manufacturing the same, and more particularly to a technique for protecting a lower wiring layer from an annealing process and a wet etching process in the manufacturing process.

[0002]

2. Description of the Related Art In an active matrix substrate of a liquid crystal display panel or a circuit substrate for an image sensor, a thin film transistor (TFT) having a high on / off ratio and a high response speed is frequently used as a switching element for the purpose of ensuring high contrast characteristics. Has been done. This thin film transistor has, for example, FIGS. 5 (a) and 5 (b).
As shown in FIG. 3, the non-doped silicon layer 501a formed on the front surface side of the substrate 40a, the gate oxide film 55a formed on the front surface side, and the ion implantation performed using the gate electrode 53a as a mask Layer 50
1a has a source region 51a and a drain region 52a which are made conductive. Here, in a liquid crystal display panel or the like, a large number of pixels are arranged in a grid pattern on the front surface side of the substrate 40a and a predetermined screen is displayed by switching the display state of each pixel. Is delayed, the display quality is significantly degraded.
Therefore, a wiring material having a low electric resistance is selected and used for the gate wiring layer 60a formed in the active matrix circuit. Further, since the gate wiring layer 60a is formed at the same time as the gate electrode 53a of the thin film transistor 50a, the wiring material forming the gate wiring layer 60a is required to be able to form the gate electrode 53a as well. Therefore, in the active matrix substrate shown in FIGS. 5A and 5B, the gate wiring layer 60a and the gate electrode 53a are both the lower-side lower polysilicon layer 61a and the upper-side molybdenum silicide layer 62a. Is formed in a two-layer structure. Then, in the source region 51a of the thin film transistor 30a, the first connection hole 651a of the interlayer insulating film 57a formed on the surface side thereof is formed.
The source electrode 65a is conductively connected through the gate wiring layer 60a, and the upper wiring layer 66a is conductively connected to the gate wiring layer 60a through the second connection hole 661a in the interlayer insulating film 57.

[0003]

In the manufacturing process of the active matrix substrate having the thin film transistor 50a and the gate wiring layer 60a having such a structure, ion implantation is performed using the gate electrode 53a as a mask to make a part of the silicon layer 501a conductive. Source area 5
In order to form 1a and the drain region 52a, it is necessary to activate the implanted impurities. Further, since the grain size of the interlayer insulating film 57a is coarse as it is formed by the CVD method, it is necessary to make it dense. Therefore, the substrate 40
A step of performing heat treatment at about 1000 ° C. or higher on the entire a to activate the impurities ion-implanted into the silicon layer 501a and densify the interlayer insulating film 57a is performed.

However, in the structure of the conventional gate electrode 53a and the gate wiring layer 60a, there is a problem that abnormal etching is likely to occur in the wet etching process for the interlayer insulating film 57a due to the alteration of the molybdenum silicide layer 62a by the annealing process. is there. That is, when the molybdenum silicide layer 62a is subjected to heat treatment in an atmosphere of about 1000 ° C. in the annealing step, large grains 62c grow as shown in FIG. Therefore, if wet etching is performed on the interlayer insulating film 57a to form the second connection hole 661a, the etching solution easily permeates along the grain boundary 62b of the molybdenum silicide layer 62a, and further, the grain is not removed. As a result of the etching solution penetrating along the grain boundary 61b of the lower-side polysilicon layer 61a generated corresponding to the boundary 62b, the etching progresses from the penetrating side of the etching solution, so that in the vertical direction, The defect 40b is generated on the side of the substrate 40a, and the defect 57b is generated in the interlayer insulating film 57a in the lateral direction. Therefore, there is a problem that the electrical resistance value of the gate wiring layer 60 increases or disconnection occurs, and the yield and reliability of the active matrix substrate are low. Such a problem is caused by J. Elec
trochim. Soc. , SOLID-STATE
SCIENCE AND TECHNOLOGY 19
81, Vol. 128, No. 10,2208-221
As reported in No. 2, it also occurs when a tungsten silicide layer is used.

In view of the above problems, the object of the present invention is to
A solid-state device including a thin film transistor capable of improving yield and reliability and a method of manufacturing the same are adopted by adopting a wiring layer structure that can withstand an annealing process and a wet etching process performed during a manufacturing process of a thin film transistor.

[0006]

Means for Solving the Problems In order to solve the above problems, the means taken in the present invention is a source / drain in which impurities are introduced on the surface side of the same substrate by using a gate electrode on a gate insulating film as a mask. A thin film transistor having a region, a lower wiring layer having at least a metal silicide layer such as molybdenum silicide or tungsten silicide or a refractory metal layer, and a lower wiring layer through a connection hole of an interlayer insulating film on the surface side thereof. For a solid-state device including a thin film transistor having an upper wiring layer for conductive connection, a heat-resistant conductive protective film on the upper layer side of the lower wiring layer that has etching resistance to an etching solution for an interlayer insulating film. Is provided. In the present invention,
Heat resistance means, for example, 100 during the manufacturing process of a solid state device.
This means that even if a heat treatment at about 0 ° C. is performed, the etching resistance and the penetration resistance of the etching solution are not significantly reduced.

Here, as the conductive protective film, for example, an impurity-doped polysilicon layer can be adopted. Further, the gate electrode of the thin film transistor may have a multi-layer structure including the same layer as the lower wiring layer so that the gate electrode of the thin film transistor and the lower wiring layer can be formed simultaneously.
In this case, it is preferable that the lower wiring layer and the lower layer of the gate electrode are formed of a polysilicon layer in order to reduce the influence of stress between the gate insulating film and the gate electrode of the thin film transistor.

In the solid-state device having such a structure, the lower wiring layer is a gate wiring layer extending from the gate electrode of the thin film transistor, and the lower wiring layer and the thin film transistor are used to display the display panel on the front surface side of the substrate. It is suitable for forming an active matrix for. In addition, it is preferable that the gate wiring layer form a scan line of an active matrix and that the scan line be used as a black matrix.

In a method of manufacturing a solid-state device having a thin film transistor having such a structure, for example, a step of forming a gate insulating film of the thin film transistor on the surface of the semiconductor region on the front surface side of the substrate, and a step of forming the gate insulating film on the front surface side of the substrate A step of laminating each layer constituting them in a region including a formation region of an electrode and a lower wiring layer, a step of collectively patterning each of these layers to form a gate electrode and a lower wiring layer, and a surface thereof A step of forming a source / drain region of the thin film transistor in the semiconductor region by introducing impurities from the side, a step of forming an interlayer insulating film on the surface side of them, and at least annealing the formation region of the thin film transistor and the lower wiring layer. And the etching solution with the surface side covered with a mask having a predetermined mask pattern. Therefore performing a step of forming a connection hole by performing wet etching on the interlayer insulating film, and forming an upper-side wiring layer on their surface.

[0010]

In the solid-state device provided with the thin film transistor according to the present invention having the above means, the lower wiring layer is
Since a heat-resistant conductive protective film having etching resistance against an etching solution for the interlayer insulating film is provided on the upper side of the metal silicide layer or the refractory metal layer, the thin film transistor is formed in the manufacturing process of the solid-state device including the thin film transistor. Even if the etching resistance of the metal silicide layer or the refractory metal layer or the permeation resistance of the etching solution is lowered by the annealing treatment required for the purpose, the metal silicide layer or the refractory metal layer is not affected by the heat resistance, the corrosion resistance and the corrosion resistance. It is protected by a conductive protective film having a high penetration resistance of the etching solution. Therefore, when the interlayer insulating film is wet-etched to form the connection hole after the annealing treatment, the etching is stopped by the conductive protective film. Therefore, since abnormal etching does not occur, both yield and reliability are high.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. In this example, an active matrix substrate of a liquid crystal display panel will be described as an example of a solid-state device including a thin film transistor.

FIG. 1 is an explanatory view showing the constitution of a thin film transistor and its gate wiring layer (lower wiring layer) formed on an active matrix substrate according to an embodiment of the present invention, and FIG. Figure, Figure 1 (b) is Figure 1
1A is a sectional view taken along line IV-IV ′ in FIG. 1A, and FIG.
FIG. 5A is a sectional view taken along line VV ′ of FIG. The overall configuration of a liquid crystal display panel using the active matrix substrate of this example is shown in a block diagram in FIG.

First, before describing the structure of a thin film transistor (TFT) and a gate wiring layer, which are the features of this example, the overall structure of a liquid crystal display panel will be described with reference to FIG.

In the active matrix type liquid crystal display panel shown in FIG. 3, the pixel matrix 22, the signal line driving circuit 12 and the scanning line driving circuit 21 are formed on the same transparent substrate 11 to reduce the size of the display device. Higher definition and lower cost are being pursued. Here, the signal line drive circuit 12 includes a shift register 13, sample hold circuits 17, 18, 19 and video signal lines 14, 15,
On the other hand, the scanning line driving circuit 21 has a shift register 20 and a buffer circuit 23. Further, the pixel matrix 22 includes a plurality of signal lines 26, 27, 28, ... Connected to the signal line drive circuit 12, and the scanning line drive circuit 2
.. and a plurality of pixels 32, 33 ... Formed at the intersections of these scanning lines and signal lines, and each pixel 32, 33. A thin film transistor 29 and a liquid crystal cell 30 are included in. Here, a clock signal line 34 for inputting a clock signal to the shift register 13 is arranged on the signal line drive circuit 12 side, while a clock signal line 34 for inputting a clock signal to the shift register 13 is arranged on the scan line drive circuit 21 side. A clock signal line 37 to which a clock signal should be input is arranged. Reference numerals 35 and 38 denote start signal lines for inputting start signals to the signal line drive circuit 12 and the scanning line drive circuit 21. In addition to the thin film transistor 29 formed in each of the pixels 32, 33, ..., Many thin film transistors are formed on the active matrix substrate, and they are connected to each other by a gate wiring layer. For example, in the shift register 20 of the scanning line driving circuit 21, the unit shift register is, as shown in FIG. Clocked inverters 3b and 4b,
And an inverter 2, of which the inverter 2
Is a p-channel type thin film transistor 201 and an n-channel type thin film transistor 20 as shown in FIG.
2 has a CMOS structure. Further, as shown in FIG. 4C, the clocked inverters 3a and 4a include two p-channel thin film transistors 301a and 301a.
302a and an n-channel thin film transistor 401a,
And the clocked inverters 3b and 4b.
4D, as shown in FIG. 4D, is composed of two p-channel type thin film transistors 301b and 302b and n-channel type thin film transistors 401b and 402b, and can be driven by a clock signal CLA * of opposite phase. .. Then, based on the bit output signals output from these shift registers, each of the pixels 29, 30 ... Performs a display operation to form a predetermined screen. Therefore, if the electric resistance values of the scanning lines 24, 25 ... For driving the thin film transistors 29 of the pixels 29, 30 ... Are high, for example, among the pixels 29 arranged in a grid pattern,
The display operation in the pixels on the edge side of the substrate 11 is delayed, and the display quality of the screen is degraded. In addition, each shift register 1
The display quality of the screen is deteriorated even when the gate wiring layer that connects the thin film transistors 3 and 20 has a high electric resistance value and a signal input / output timing is delayed in a specific unit shift register.

Therefore, in the active matrix substrate according to this example, a thin film transistor and a gate wiring layer having the following configurations are adopted.

In FIGS. 1A to 1C, a substrate 40 is a transparent glass substrate for an active matrix substrate,
A silicon layer 501 is provided on the surface side, and the gate oxide film 5 on the surface side is provided on both end sides of the silicon layer 501.
By the ion implantation of phosphorus or the like as an n-type impurity performed using the gate electrode 53 formed on the mask 5 as a mask, the source region 51 and the drain region 52, which are partially made conductive, become self-aligned. The thin film transistor 50 is formed by the gate oxide film 55, the gate electrode 53, the source region 51, and the drain region 52. Further, an interlayer insulating film 57 is formed on the surface side of the thin film transistor 50, and the source electrode 65 is conductively connected to the source region 51 of the thin film transistor 50 through the first connection hole 651.
The drain electrode 67 is conductively connected to the drain region 52 through the third connection hole 671. Here, when the thin film transistor 50 is used as a switching element in the pixel region, the structure is partially changed as necessary, and an ITO layer is used as the drain electrode 67 instead of the aluminum electrode. On the other hand, the gate wiring layer 60 formed integrally with the gate electrode 53 extends from the formation region of the thin film transistor 50, and the second connection formed in the interlayer insulating film 57 is connected to the gate wiring layer 60. Hole 66
The upper wiring layer 66 is electrically conductively connected via 1. The gate wiring layer 60 includes a lower polysilicon layer 61 having a thickness of about 1000Å, a molybdenum silicide layer 62 (metal silicide layer) having a thickness of about 2000Å, and an upper polysilicon layer 63 (conductivity of about 1000Å). It has a three-layer structure composed of a protective film). Moreover, since the gate wiring layer 60 and the gate electrode 53 are integrally formed at the same time, the gate electrode 53 of the thin film transistor 50 is formed.
The lower side polysilicon layer 61 having a thickness of about 1000 Å,
It has a three-layer structure including a molybdenum silicide layer 62 having a thickness of about 2000Å and an upper-side polysilicon layer 63 having a thickness of about 1000Å.

The reason for providing the molybdenum silicide layer 62 on the gate wiring layer 60 is to reduce the electrical resistance value of the gate wiring layer 60. That is, in a liquid crystal display panel or the like, as described above, a large number of pixels are arranged in a grid and a predetermined screen is displayed by switching the display state of each pixel, so that the display operation in a specific pixel is delayed. This is because the display quality is remarkably deteriorated, so that the resistance of the gate wiring layer 60 is lowered to prevent a signal delay due to the resistance.

The reason for providing the upper polysilicon layer 63 on the gate wiring layer 60 is that the interlayer insulating film 57 is included in the manufacturing process of the thin film transistor 50 and the gate wiring layer 60.
When the first connection hole 651, the second connection hole 661, and the third connection hole 671 are formed by wet etching on the above, the molybdenum silicide layer 62 is formed in the molybdenum silicide layer 62 by the annealing treatment performed prior to this step. This is to prevent the effects of grain bandaries. That is, when an annealing process is performed in the manufacturing process of the thin film transistor 50 and the gate wiring layer 60, grains grow large in the molybdenum silicide layer 62 and grain boundaries are generated. When the molybdenum silicide layer 62 is exposed on the outermost surface, the penetration resistance of 57 to the etching solution is low.
The etching solution penetrates along the grain boundary, causing abnormal etching. On the other hand, since the upper polysilicon layer 63 is not affected by the grain boundary of the molybdenum silicide layer 62 even after the annealing treatment, it has high etching resistance to the etching solution and high penetration resistance of the etching solution. It functions as a stopper for wet etching and prevents abnormal etching.

Therefore, in the active matrix substrate of this embodiment, since the gate wiring layer 60 is provided with the molybdenum silicide layer 62, the electric resistance value of the gate wiring layer 60 is small, so that the display operation in the pixel is delayed. No, the display quality is high. Further, since the upper-layer side polysilicon layer 63 is provided on the outermost layer of the gate wiring layer 60, abnormal etching that has occurred in the conventional gate wiring layer can be prevented, so that the electrical resistance value of the gate wiring layer 60 increases and No breakage occurs, and both yield and reliability are high.

Further, since the gate wiring layer 60 is impermeable to light, the gate wiring layer 60 allows the structure shown in FIG.
The scanning lines 24, 25 ... Of the active matrix shown in FIG.
., And by using it as a black matrix of a liquid crystal display panel, pixels 32, 33 ...
It is possible to form a black matrix with high alignment accuracy with, and improve the display quality of the liquid crystal display panel. Further, the gate wiring layer 60 and the gate electrode 53
Has a lower-side polysilicon layer 61 on the lowermost side thereof, the influence of stress or the like on the gate oxide film 55 is small, and a multi-layer structure suitable for the gate wiring layer 60 is applied to the gate electrode 53. But there is no problem.

A method of manufacturing the active matrix substrate having such a structure will be described with reference to FIG.

2A to 2F are process sectional views showing a part of a thin film transistor forming process and a gate wiring layer forming process in the method of manufacturing an active matrix substrate of this embodiment.

First, as shown in FIG. 2A, the substrate 40
A gate oxide film 55 is formed on the silicon layer 501 formed in the region where the thin film transistor 50 is to be formed on the surface side of the substrate by thermal oxidation or ECRCVD.

Next, as shown in FIG. 2B, the gate electrode 5 is formed on the region including the region where the gate electrode 53 and the gate wiring layer 60 are to be formed, that is, the entire surface of the substrate 40.
3 and the non-doped lower-side polysilicon layer 61 forming the lower layer of the gate wiring layer 60, using Si ₂ H ₆ in an LPCVD method, for example, in an atmosphere at a temperature of about 600 ° C. and low pressure. After forming it to a thickness of about 1000Å, a molybdenum silicide layer 62 having a thickness of about 2000Å is formed on the surface side by a sputtering method, and an upper polysilicon layer having a thickness of about 1000Å is formed on the surface side. 63 is formed by the CVD method. In this state, the sheet resistance value of these layers is 40 to 50 Ω / □. here,
Impurity-doped polysilicon may be used for the upper-side polysilicon layer 63, or non-doped polysilicon may be used to make it conductive by an impurity introduction step performed in a later step. On the other hand, the lower polysilicon layer 61 may also be an impurity-doped polysilicon layer. The molybdenum silicide layer 62 may have a Mo-rich composition with a composition deviation from the composition formula represented by MoSi ₂ .

Next, the lower polysilicon layer 61, the molybdenum silicide layer 62, and the upper polysilicon layer 63 are collectively packaged with the upper polysilicon layer 63 covered with a resist mask having a predetermined mask pattern. Then, patterning is performed by photoetching, and FIG.
As shown in (c) and FIGS. 1A to 1C, the gate electrode 53 and the gate wiring layer 60 are left.

Next, as shown in FIG. 2 (d), phosphorus as an n-type impurity is ion-implanted or ion-shower-doped from the surface side of the surfaces of FIGS.
As shown in (c), part of the silicon layer 501 is made conductive to form the source region 51 and the drain region 52 of the thin film transistor 50.

Next, as shown in FIG. 2E, an interlayer insulating film 57, which is a silicon oxide film, is formed on the surface side of these by a CVD method.

Next, at least the thin film transistor 50
Then, the formation region of the gate wiring layer 60, that is, the entire substrate 40 is annealed in a nitrogen gas atmosphere at about 1000 ° C. By this annealing treatment, the sheet resistance value of the gate wiring layer 60 is about 100Ω /
What was □ decreased to 4 to 5Ω / □. Further, the impurities introduced into the source region 51 and the drain region 52 of the silicon layer 501 are also activated. In addition, the interlayer insulating film 57 is also densified.

Next, as shown in FIG. 2F, with the surface side of the interlayer insulating film 57 covered with a mask resist mask 571 having a predetermined mask pattern, for example, a fluorine-based etching solution is used to etch the interlayer insulating film. 57 is wet-etched to form a first connection hole 651, a second connection hole 661, and a third connection hole 671.

Then, the entire surface of the interlayer insulating film 57 is
1 (a) to 1 (c) after forming an aluminum layer forming the upper wiring layer 66, the source electrode 65 and the drain electrode 66, the aluminum layer is patterned.
As shown in, the upper wiring layer 66, the source electrode 65, and the drain electrode 66 are formed.

As described above, in the method of manufacturing the active matrix substrate of this embodiment, the structure in which the molybdenum silicide layer 62 is provided in the gate wiring layer 60 to reduce the electric resistance value thereof, but the upper layer side thereof is used. Since the upper-layer side polysilicon layer 63 is provided, even if a large grain grows in the molybdenum silicide layer 62 due to the annealing process and the etching solution easily penetrates along the grain boundary, the upper-layer side polysilicon layer 63 is formed. Since the silicon layer 63 functions as an etching stopper, abnormal etching does not occur. Therefore, in the active matrix substrate of this example, since the electric resistance value of the gate wiring layer 60 is small, the display operation in the pixel is not delayed, so that the display quality is high and abnormal etching is prevented. Therefore, the electrical resistance value of the gate wiring layer 60 does not increase or the wire breakage does not occur, and both the yield and the reliability are high.

In this example, an active matrix substrate was described as an example of a solid-state device provided with a thin film transistor, but it can also be applied to a circuit substrate for an image sensor or the like, and on the surface side of the same substrate, on the gate insulating film. Connection between a thin film transistor having source / drain regions in which impurities are introduced by using a gate electrode as a mask, a lower wiring layer having at least a metal silicide layer or a refractory metal layer, and an interlayer insulating film formed on the surface side thereof The application is not limited as long as it is a solid-state device having an upper wiring layer conductively connected to a lower wiring layer through a hole. Also,
In this example, a polysilicon layer is provided on the upper side of the metal silicide layer for both the gate wiring layer (lower wiring layer) and the gate electrode of the thin film transistor. Only the lower wiring layer, which is electrically connected to the upper wiring layer through the hole, may have a structure having a conductive protective film such as a polysilicon layer. Further, instead of the metal silicide layer or in addition to the metal silicide layer, a refractory metal layer such as a molybdenum layer or a tungsten layer may be provided.

[0033]

As described above, in the solid state device provided with the thin film transistor according to the present invention, for example, the substrate for active matrix display, the lower wiring layer such as the gate wiring layer is the metal silicide layer or the refractory metal layer. It is characterized in that the upper layer side is provided with a heat-resistant conductive protective film having etching resistance against an etching solution for the interlayer insulating film. Therefore, according to the present invention, since the metal silicide layer or the refractory metal layer is provided in the lower wiring layer, the electric resistance thereof is small. Further, even if the etching resistance of the metal silicide layer or the refractory metal layer or the penetration resistance of the etching solution is lowered by the annealing treatment performed during the manufacturing process of the solid-state device, the surface side thereof has high heat resistance and corrosion resistance. Since it is covered with the conductive protective film, wet etching is stopped by this conductive protective film, and abnormal etching does not occur, so that the yield and reliability of the solid-state device are improved.

[Brief description of drawings]

1A is a plan view showing a configuration of a thin film transistor and a gate wiring layer thereof formed on an active matrix substrate according to an embodiment of the present invention, and FIG. 1B is an IV of FIG. 1A.
A cross-sectional view taken along the line -IV ', (c) is a V- of FIG. 1 (a)
It is a sectional view taken along the line V ′.

FIG. 2 is a process cross-sectional view showing a part of a process of manufacturing a thin film transistor and a gate wiring layer in the method of manufacturing the active matrix substrate shown in FIG.

3 is a block diagram showing an overall configuration of a liquid crystal display panel using the active matrix substrate shown in FIG.

4 (a) is a circuit diagram of a shift register formed on the active matrix substrate shown in FIG. 1, (b) is a circuit diagram of its inverter, and (c) and (d) are circuit diagrams of its clocked inverter. Is.

FIG. 5 is a plan view showing a configuration of a conventional thin film transistor and its gate wiring layer, (b) is VI-VI ′ of FIG. 5 (a).
It is sectional drawing in a line.

FIG. 6 is an explanatory diagram showing a state around a connection hole for a conventional gate wiring layer.

[Explanation of symbols]

 11 ... Transparent substrate 12 ... Signal line drive circuit 13, 20 ... Shift register 21 ... Scan line drive circuit 22 ... Pixel matrix 24, 25 ... Scan line 26, 27, 28 ... ..Signal line 29, 50, 50a ... Thin film transistor 30 ... Liquid crystal cell 32, 33 ... Pixel 51, 51a ... Source region 52, 52a ... Drain region 53, 53a ... Gate electrode 57, 57a ... Interlayer insulating film 60, 60a ... Gate wiring layer (lower wiring layer) 61, 61a ... Lower polysilicon layer 62, 62a ... Molybdenum silicide layer 63 ... Upper poly Silicon layer (conductive protection layer) 66 ... Upper wiring layer 651, 651a ... First connection hole 661, 661a ... Second connection hole 671 ... Third connection hole

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 27/12 A 29/40 A 9055-4M 29/62 G 9055-4M

Claims (8)

[Claims] 1. A source / impurity source on the surface of the same substrate in which impurities are introduced using the gate electrode on the gate insulating film as a mask.
A thin film transistor having a drain region, a lower wiring layer having at least a metal silicide layer or a refractory metal layer, and conductive connection to the lower wiring layer through a connection hole of an interlayer insulating film formed on the surface side thereof. An upper wiring layer, and the lower wiring layer, on the upper side thereof,
A solid-state device including a thin film transistor, comprising a heat-resistant conductive protective film having etching resistance against an etching solution for the interlayer insulating film. 2. The solid state device according to claim 1, wherein the conductive protective film is an impurity-doped polysilicon layer. 3. The solid-state thin film transistor according to claim 1, wherein the gate electrode of the thin film transistor has a multi-layer structure including the same layer as the lower wiring layer. apparatus. 4. The solid state device according to claim 3, wherein the lower wiring layer and the gate electrode have a polysilicon layer on the lower side thereof. 5. The thin film transistor according to claim 1, wherein the metal silicide layer is formed of at least one of a molybdenum silicide layer and a tungsten silicide layer. Solid state device. 6. The wiring layer according to claim 1, wherein the lower wiring layer is a gate wiring layer extending from a gate electrode of the thin film transistor, and the gate wiring layer and the thin film transistor are used. A solid-state device including a thin film transistor, wherein an active matrix circuit for a display panel is formed on the front surface side of the substrate. 7. The scan line of a pixel matrix is formed by the gate wiring layer on the front surface side of the substrate according to claim 6, and the black matrix of the display panel is formed by these scan lines. A solid-state device provided with a thin film transistor. 8. A method of manufacturing a solid-state device comprising a thin film transistor as defined in any one of claims 1 to 7, wherein a gate insulating film of the thin film transistor is provided on a surface of a semiconductor region on a surface side of the substrate. A step of forming the layers, a step of laminating the respective layers constituting the gate electrode and the lower wiring layer on the surface side of the substrate in a region including the formation region of the gate electrode and the lower wiring layer, and patterning these layers at once. A step of forming the gate electrode and the lower wiring layer, a step of introducing impurities from the surface side thereof to form source / drain regions of the thin film transistor in the semiconductor region, and an interlayer insulating film on the surface side thereof. And a step of annealing at least the formation region of the thin film transistor and the lower wiring layer, and the surface thereof. Wet etching the interlayer insulating film with the etching solution to form the connection holes with the side covered with a mask having a predetermined mask pattern, and forming the upper wiring layer on the surface side thereof. The manufacturing method of the solid-state device provided with the thin-film transistor characterized by having the process.