JPH0529772A - Circuit substrate for high-speed signal transmission - Google Patents
Circuit substrate for high-speed signal transmissionInfo
- Publication number
- JPH0529772A JPH0529772A JP3179237A JP17923791A JPH0529772A JP H0529772 A JPH0529772 A JP H0529772A JP 3179237 A JP3179237 A JP 3179237A JP 17923791 A JP17923791 A JP 17923791A JP H0529772 A JPH0529772 A JP H0529772A
- Authority
- JP
- Japan
- Prior art keywords
- signal transmission
- layer
- ground
- power plane
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Waveguides (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高速信号を伝送する回
路基板の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a circuit board for transmitting high speed signals.
【０００２】[0002]
【従来の技術】図３はかかる従来の高速信号伝送用回路
基板の上面及び断面図である。この図に示すように、第
１層（表面）は高速信号伝送用ライン（以下、伝送ライ
ンという）であり、伝送ライン１、部品搭載用パッド４
及び接続用パッド（以下、総称してパッドという）、誘
電体層３ａからなる。第２層はグランド／電源プレーン
であり、グランド／電源プレーン２ａ、誘電体層３ｂか
らなる。第３層は中層の伝送ライン用信号層であり、中
層の伝送ライン７、誘電体層３ｃからなる。第４層はグ
ランド／電源プレーンであり、グランド／電源プレーン
２ｂ、誘電体層３ｄからなる。2. Description of the Related Art FIG. 3 is a top view and a sectional view of such a conventional high-speed signal transmission circuit board. As shown in this figure, the first layer (surface) is a high-speed signal transmission line (hereinafter referred to as a transmission line), and the transmission line 1 and the component mounting pad 4
And a connection pad (hereinafter, collectively referred to as a pad) and a dielectric layer 3a. The second layer is a ground / power plane, and is composed of a ground / power plane 2a and a dielectric layer 3b. The third layer is a middle-layer transmission line signal layer, and includes the middle-layer transmission line 7 and the dielectric layer 3c. The fourth layer is a ground / power plane, which is composed of a ground / power plane 2b and a dielectric layer 3d.
【０００３】上記したように、高速信号を伝送させるた
めに、伝送ライン（パッドを含む）とグランド／電源プ
レーン間を均一な厚さの誘電体で挟む構造となってお
り、伝送ラインのみ誘電体の厚さと伝送ラインの幅によ
り、インピーダンス整合がなされていた。As described above, in order to transmit a high-speed signal, the transmission line (including the pad) and the ground / power supply plane are sandwiched by dielectrics of uniform thickness, and only the transmission line is dielectric. Impedance matching was performed depending on the thickness and the width of the transmission line.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、前記の
高速信号伝送用回路基板の構造では、伝送ラインの幅と
異なるパッドに対しては、インピーダンス整合を行なっ
てはいなかった。また、伝送ラインをインピーダンス整
合させているため、誘電体の厚さが先に決まっており、
パッドとグランド間の誘電体の厚さが一定となっている
ことから、パッドに対してインピーダンス整合させよう
とした場合、パッドの幅を調節するより方法がないが、
実際には部品搭載用であったり、接続用であったり、そ
のパッドの幅はまちまちであり、インピーダンス整合は
困難であった。However, in the above-mentioned structure of the circuit board for high-speed signal transmission, impedance matching has not been performed for pads having a width different from that of the transmission line. Also, because the impedance of the transmission line is matched, the thickness of the dielectric is decided first,
Since the thickness of the dielectric between the pad and ground is constant, if you try to match the impedance to the pad, there is no way to adjust the width of the pad,
Actually, the widths of pads for component mounting or connection were different, and impedance matching was difficult.
【０００５】従って、伝送ラインのパッド部で反射が起
こり、高速信号の伝送特性を劣化させていた。本発明
は、以上述べた高速信号の伝送ラインのパッド部におけ
る反射の問題を除去するため、パッド部のみグランドま
での誘電体の厚さを変えることにより、インピーダンス
整合を図り、反射の少ない高速信号伝送用回路基板を提
供することを目的とする。Therefore, reflection occurs at the pad portion of the transmission line, which deteriorates the transmission characteristics of high-speed signals. In order to eliminate the above-mentioned problem of reflection at the pad portion of the high-speed signal transmission line, the present invention achieves impedance matching by changing the thickness of the dielectric material only to the pad portion to the ground, thereby reducing the high-speed signal with less reflection. An object is to provide a circuit board for transmission.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するために、
（Ａ）信号伝送用導体層と中層に形成したグランド／電
源プレーンとの間に誘電体層を形成することによりイン
ピーダンス整合を図る高速信号伝送用回路基板におい
て、表面に形成される第１の信号伝送用導体層と、該第
１の信号伝送用導体層の下方に誘電体層を介して形成さ
れる第１のグランド／電源プレーン層と、該第１のグラ
ンド／電源プレーン層の下方に誘電体層を介して形成さ
れる第２の信号伝送用導体層と、該第２の信号伝送用導
体層の下方に形成される第２のグランド／電源プレーン
層と、前記第１の信号伝送用導体層のパッド部のインピ
ーダンス整合を前記第１のグランド／電源プレーン層と
誘電体層で行なうために介在する前記パッド部の直下に
該パッド部より若干大きいくり抜き部と、前記第２の信
号伝送用導体層に前記パッド部直下に該パッド部より若
干大きめの配線禁止領域とを設けるようにしたものであ
る。In order to achieve the above object, the present invention provides (A) a dielectric layer between a signal transmission conductor layer and a ground / power plane formed in an intermediate layer. In a high-speed signal transmission circuit board for impedance matching, a first signal transmission conductor layer formed on a surface and a first signal transmission conductor layer formed below the first signal transmission conductor layer with a dielectric layer interposed therebetween. Ground / power plane layer, a second signal transmission conductor layer formed below the first ground / power plane layer via a dielectric layer, and a second signal transmission conductor layer below the second signal transmission conductor layer. The second ground / power plane layer formed on the first ground / power plane layer and the pad portion of the first signal transmission conductor layer are impedance-matched between the first ground / power plane layer and the dielectric layer. The pad should be placed directly below the pad. A hollow portion slightly larger than the pad portion and a wiring prohibited region slightly larger than the pad portion are provided immediately below the pad portion in the second signal transmission conductor layer.
【０００７】（Ｂ）また、上記高速信号伝送用回路基板
において、表面に形成される第１の信号伝送用導体層
と、該第１の信号伝送用導体層の下方に誘電体層を介し
て形成される第１のグランド／電源プレーン層と、該第
１のグランド／電源プレーン層の下方に誘電体層を介し
て形成される第２の信号伝送用導体層と、該第２の信号
伝送用導体層の下方に誘電体層を介して形成される第３
の信号伝送用導体層と、該第３の信号伝送用導体層の下
方に誘電体層を介して形成される第２のグランド／電源
プレーン層と、前記信号伝送用導体層のパッド部のイン
ピーダンス整合を前記第１のグランド／電源プレーン層
と誘電体層で行なうために介在する前記パッド部の直下
に該パッド部より若干大きいくり抜き部と、前記第２及
び第３の信号伝送用導体層にそれぞれ前記パッド部直下
に該パッド部より若干大きめの配線禁止領域とを設ける
ようにしたものである。(B) In the above-mentioned high-speed signal transmission circuit board, the first signal transmission conductor layer formed on the surface and the dielectric layer below the first signal transmission conductor layer are interposed. A first ground / power plane layer formed, a second signal transmission conductor layer formed below the first ground / power plane layer via a dielectric layer, and the second signal transmission A third layer formed below the conductor layer for use with a dielectric layer interposed
Signal transmission conductor layer, a second ground / power plane layer formed below the third signal transmission conductor layer via a dielectric layer, and an impedance of the pad portion of the signal transmission conductor layer. Immediately below the pad portion interposed to perform matching with the first ground / power plane layer and the dielectric layer, a hollow portion slightly larger than the pad portion, and the second and third signal transmission conductor layers are provided. Immediately below the pad portion, a wiring-prohibited region slightly larger than the pad portion is provided.
【０００８】（Ｃ）更に、上記高速信号伝送用回路基板
において、表面に形成される第１の信号伝送用導体層
と、該第１の信号伝送用導体層の下方に誘電体層を介し
て形成される第１のグランド／電源プレーン層と、該第
１のグランド／電源プレーン層の下方に誘電体層を介し
て形成される第２の信号伝送用導体層と、該第２の信号
伝送用導体層の下方に誘電体層を介して形成される第２
のグランド／電源プレーン層と、該第２のグランド／電
源プレーン層の下方に誘電体層を介して形成される第３
の信号伝送用導体層と、該第３の信号伝送用導体層の下
方に誘電体層を介して形成される第３のグランド／電源
プレーン層と、該第３のグランド／電源プレーン層に下
方に形成される誘電体層と、前記第１の信号伝送用導体
層のパッド部のインピーダンス整合を前記第１のグラン
ド／電源プレーン層と誘電体層で行なうために介在する
前記パッド部の直下に該パッド部より若干大きい第１の
くり抜き部と、前記第２の信号伝送用導体層には前記第
１のくり抜き部直下に前記パッド部より若干大きめの第
１の配線禁止領域と、前記第３のグランド／電源プレー
ン層には前記第１の配線禁止領域の直下に前記パッド部
より若干大きい第２のくり抜き部と、前記第３の信号伝
送用導体層に前記第２のくり抜き部の直下に前記パッド
部より若干大きめの第２の配線禁止領域とを設けるよう
にしたものである。(C) Further, in the high-speed signal transmission circuit board, the first signal transmission conductor layer formed on the surface and the dielectric layer below the first signal transmission conductor layer are interposed. A first ground / power plane layer formed, a second signal transmission conductor layer formed below the first ground / power plane layer via a dielectric layer, and the second signal transmission A second layer formed below the conductor layer for use with a dielectric layer interposed
Ground / power plane layer, and a third layer formed below the second ground / power plane layer via a dielectric layer.
Signal transmission conductor layer, a third ground / power plane layer formed below the third signal transmission conductor layer via a dielectric layer, and a third ground / power plane layer below the third ground / power plane layer. Directly below the pad portion interposed for impedance matching between the dielectric layer formed on the first dielectric layer and the pad portion of the first signal transmission conductor layer with the first ground / power plane layer and the dielectric layer. A first hollow portion slightly larger than the pad portion, a first wiring prohibited region slightly larger than the pad portion immediately below the first hollow portion in the second signal transmission conductor layer, and the third wiring In the ground / power plane layer, a second hollow portion slightly larger than the pad portion just below the first wiring prohibited area, and a second hollow portion in the third signal transmission conductor layer just below the second hollow portion. A little larger than the pad part It is obtained so as to provide a second wiring prohibited area.
【０００９】[0009]
【作用】本発明によれば、上記したように、高速信号伝
送用回路基板において、インピーダンス整合されている
伝送ラインよりも幅の広いパッド部に対して、該パッド
の下のグランド／電源プレーンを部分的に取り除きくり
抜き部を形成し、前記パッドからグランド／電源プレー
ンまでの誘電体層の厚さを厚くすることにより、パッド
の幅を変更することなく、インピーダンス整合を図るこ
とができる。According to the present invention, as described above, in the circuit board for high-speed signal transmission, the ground / power plane below the pad is provided for the pad portion wider than the impedance-matched transmission line. Impedance matching can be achieved without changing the width of the pad by partially removing the hollow portion and increasing the thickness of the dielectric layer from the pad to the ground / power plane.
【００１０】[0010]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明の第１の実施例を
示す高速信号伝送用回路基板の上面及び断面図、図２は
その高速信号伝送用回路基板の分解斜視図である。これ
らの図において、１１は表層の伝送ライン、１２ａ及び
１２ｂはグランド／電源プレーン、１３ａ〜１３ｄは誘
電体層、１４はパッド、１５はくり抜き部、１６は伝送
ラインとパッドの接続部、１７は中層の伝送ライン、１
８は配線禁止領域である。Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a top view and a sectional view of a high-speed signal transmission circuit board showing a first embodiment of the present invention, and FIG. 2 is an exploded perspective view of the high-speed signal transmission circuit board. In these drawings, 11 is a surface transmission line, 12a and 12b are ground / power planes, 13a to 13d are dielectric layers, 14 is a pad, 15 is a cutout portion, 16 is a transmission line and pad connection portion, and 17 is Middle layer transmission line, 1
Reference numeral 8 is a wiring prohibited area.
【００１１】ここで、伝送ライン１１は、その伝送ライ
ン１１の幅とグランド／電源プレーン１２ａまでの高
さ、すなわち誘電体層１３ａの厚さによりインピーダン
ス整合されている。その伝送ライン１１は、パッド１４
に接続されている。そのパッド１４の直下のグランド／
電源プレーン１２ａには部分的にくり抜き部１５を設
け、パッド１４からグランド／電源プレーン１２ａまで
の誘電体層の厚さを厚くしている。Here, the transmission line 11 is impedance-matched by the width of the transmission line 11 and the height to the ground / power plane 12a, that is, the thickness of the dielectric layer 13a. The transmission line 11 has a pad 14
It is connected to the. Ground directly under the pad 14
The power plane 12a is partially provided with a hollow portion 15 to increase the thickness of the dielectric layer from the pad 14 to the ground / power plane 12a.
【００１２】ここで、くり抜き部１５は電界の広がりを
考慮し、パッド１４よりも若干大きめとするが、伝送ラ
イン１１との接続方向のみ、伝送ライン１１のインピー
ダンス整合を考慮して、両者の接続部１６までのくり抜
きとする。また、グランド／電源プレーン１２ａ及び１
２ｂ間の中層の伝送ライン１７信号層には、くり抜き部
１５よりも若干広めの配線禁止領域１８を設ける。Here, the cutout portion 15 is made slightly larger than the pad 14 in consideration of the spread of the electric field. However, only in the connecting direction with the transmission line 11, the impedance matching of the transmission line 11 is considered and the connection between the two is made. Cut to part 16. Also, ground / power planes 12a and 1
In the signal layer of the middle transmission line 17 between 2b, a wiring prohibited area 18 slightly wider than the cut-out portion 15 is provided.
【００１３】このように構成することにより、パッド１
４からグランド／電源プレーンまでの誘導体層の厚さ
は、グランド／電源プレーン１２ｂまでとなり、くり抜
き部１５を設ける前の３倍の誘導体層の厚さとなり、表
層の伝送ライン１１の２〜４倍程度の幅のパッド１４に
対して、インピーダンス整合性が向上し、反射が大幅に
少なくなる。With this structure, the pad 1
The thickness of the dielectric layer from 4 to the ground / power plane is up to the ground / power plane 12b, which is three times the thickness of the dielectric layer before the hollow portion 15 is provided, which is 2 to 4 times the thickness of the transmission line 11 on the surface layer. The impedance matching is improved and the reflection is significantly reduced with respect to the pad 14 having a moderate width.
【００１４】図４は本発明の第２実施例を示す高速信号
伝送用回路基板の上面及び断面図であり、図４（ａ）は
その高速信号伝送用回路基板の上面図、図４（ｂ）はそ
の高速信号伝送用回路基板の上面図である。図中、２１
は表層の伝送ライン、２２ａ及び２２ｂはグランド／電
源プレーン、２３ａ〜２３ｅは誘電体層、２４はパッ
ド、２５はくり抜き部、２６は伝送ラインとパッドの接
続部、２７，２８は中層の伝送ライン、２９ａ，２９ｂ
は配線禁止領域である。FIG. 4 is a top view and a sectional view of a circuit board for high speed signal transmission showing a second embodiment of the present invention, and FIG. 4 (a) is a top view of the circuit board for high speed signal transmission, and FIG. 4) is a top view of the circuit board for high-speed signal transmission. 21 in the figure
Is a transmission line on the surface layer, 22a and 22b are ground / power planes, 23a to 23e are dielectric layers, 24 is a pad, 25 is a cutout portion, 26 is a connection portion between a transmission line and a pad, and 27 and 28 are middle-layer transmission lines. , 29a, 29b
Is a wiring prohibited area.
【００１５】この図に示すように、２つのグランド／電
源プレーン２２ａ及び２２ｂの間に２層分の伝送ライン
２７，２８用信号層を挟むようにしている。この場合も
第１の実施例と同様、電界の広がりを考慮して、くり抜
き部２５及び配線禁止領域２９ａ、２９ｂを上層から下
層に行くにつれてパッド２４より徐々に広くなるように
して、表層の伝送ライン２１の３〜５倍の広さのパッド
に対応できるようにしている。As shown in this figure, two layers of signal lines for transmission lines 27 and 28 are sandwiched between two ground / power planes 22a and 22b. Also in this case, as in the first embodiment, in consideration of the spread of the electric field, the hollow portion 25 and the wiring prohibited areas 29a and 29b are gradually made wider than the pad 24 from the upper layer to the lower layer, and the transmission of the surface layer is performed. The pad is made to be 3 to 5 times wider than the line 21.
【００１６】図５は本発明の第３実施例を示す高速信号
伝送用回路基板の上面及び断面図である。この図におい
て、３１は表層の伝送ライン、３２ａ，３２ｂ及び３２
ｃはグランド／電源プレーン、３３ａ〜３３ｆは誘電体
層、３４はパッド、３５は１段目のくり抜き部、３６は
伝送ラインとパッドの接続部、３７は２段目のくり抜き
部、３９ａ，３９ｂは配線禁止領域、４１，４２は中層
の伝送ラインである。FIG. 5 is a top view and a sectional view of a circuit board for high-speed signal transmission showing a third embodiment of the present invention. In this figure, 31 is a surface transmission line, 32a, 32b and 32.
c is a ground / power plane, 33a to 33f are dielectric layers, 34 is a pad, 35 is a first-stage hollow portion, 36 is a transmission line / pad connecting portion, 37 is a second-stage hollow portion, and 39a and 39b. Is a wiring prohibited area, and 41 and 42 are middle-layer transmission lines.
【００１７】この実施例は、表層の伝送ライン３１の幅
に比べてパッド３４の幅が極端に広い場合、例えば４〜
６倍の例である。この図に示すように、表面にパッド３
４を有する伝送ライン３１が形成されており、誘電体層
３３ａを介してパッド３４の直下にそのパッド３４より
若干広めの１段目のくり抜き部３５が形成されたグラン
ド／電源プレーン３２ａを設ける。この場合、１段目の
くり抜き部３５は伝送ライン１１とパッド３４の接続部
３６側は広がっていないが、その接続部３６と反対側は
広くなるように形成されている。In this embodiment, when the width of the pad 34 is extremely wider than the width of the transmission line 31 on the surface layer, for example, 4 to 4.
This is an example of 6 times. As shown in this figure, the pad 3 is
4 is formed, and the ground / power supply plane 32a is provided immediately below the pad 34 via the dielectric layer 33a in which the hollowed-out portion 35 of the first stage slightly wider than the pad 34 is formed. In this case, the hollow portion 35 of the first stage is formed such that the side of the transmission line 11 and the pad 34 which is on the connecting portion 36 side is not widened, but the side opposite to the connecting portion 36 is wide.
【００１８】更に、誘電体層３３ｂを介して１段目のく
り抜き部３５の直下にその１段目のくり抜き部３５より
若干広めの配線禁止領域３９ａを有する伝送ライン４１
を設ける。また、誘電体層３３ｃを介して配線禁止領域
３９ａの直下にその配線禁止領域３９ａより若干広めの
２段目のくり抜き部３７を有するグランド／電源プレー
ン３２ｂを設ける。この場合には、２段目のくり抜き部
３７は伝送ライン１１とパッド３４の接続部３６及びそ
の接続部３６の反対側ともに広くなるように形成する。Further, a transmission line 41 having a wiring-prohibited region 39a, which is slightly wider than the first-stage hollow portion 35, is provided directly below the first-stage hollow portion 35 with the dielectric layer 33b interposed therebetween.
To provide. Further, a ground / power plane 32b having a second step hollow portion 37 slightly wider than the wiring prohibited area 39a is provided directly below the wiring prohibited area 39a via the dielectric layer 33c. In this case, the hollowed-out portion 37 of the second stage is formed so that both the connecting portion 36 of the transmission line 11 and the pad 34 and the opposite side of the connecting portion 36 are wide.
【００１９】また、誘電体層３３ｄを介して２段目のく
り抜き部３７より若干広めの配線禁止領域３９ｂを有す
る伝送ライン４２を設ける。また、その下方には誘電体
層３３ｅを介してベタ状のグランド／電源プレーン３２
ｃを設ける。最下層には誘電体層３３ｆを形成する。な
お、本発明は上記実施例に限定されるものではなく、本
発明の趣旨に基づいて種々の変形が可能であり、これら
を本発明の範囲から排除するものではない。Further, a transmission line 42 having a wiring-prohibited region 39b slightly wider than the cutout portion 37 in the second stage is provided via the dielectric layer 33d. In addition, a solid-state ground / power supply plane 32 is provided below the dielectric layer 33e.
c is provided. A dielectric layer 33f is formed on the bottom layer. The present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.
【００２０】[0020]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、高速伝送用回路基板の伝送ラインのパッド部で
パッド直下のグランド／電源プレーンに部分的にくり抜
き部を設けることにより、パッドからグランド／電源プ
レーンまでの誘電体層の高さを変化させることで、イン
ピーダンス整合を図り、反射を抑え、高速信号の伝送特
性の向上を図ることができる。As described above in detail, according to the present invention, the cutout portion is partially provided in the ground / power supply plane immediately below the pad in the transmission line pad portion of the high-speed transmission circuit board. By changing the height of the dielectric layer from the pad to the ground / power supply plane, impedance matching can be achieved, reflection can be suppressed, and high-speed signal transmission characteristics can be improved.
【００２１】また、高速伝送用回路基板の表層の伝送ラ
インに対するパッドの広さに対応してグランド／電源プ
レーンのくり抜き部や中層の伝送ラインの配線禁止領域
の構成を変更して、的確なインピーダンス整合を図り、
反射を抑え、高速信号の伝送特性の向上を図ることがで
きる。Further, the structure of the cut-out portion of the ground / power plane and the wiring prohibited area of the middle-layer transmission line is changed in accordance with the size of the pad with respect to the transmission line on the surface layer of the high-speed transmission circuit board to obtain an accurate impedance. To align,
It is possible to suppress reflection and improve the transmission characteristics of high-speed signals.
【図１】本発明の第１の実施例を示す高速信号伝送用回
路基板の上面及び断面図である。FIG. 1 is a top view and a cross-sectional view of a high-speed signal transmission circuit board showing a first embodiment of the present invention.
【図２】本発明の第１の実施例を示す高速信号伝送用回
路基板の分解斜視図である。FIG. 2 is an exploded perspective view of a circuit board for high-speed signal transmission showing the first embodiment of the present invention.
【図３】従来の高速信号伝送用回路基板の上面及び断面
図である。FIG. 3 is a top view and a cross-sectional view of a conventional high-speed signal transmission circuit board.
【図４】本発明の第２実施例を示す高速信号伝送用回路
基板の上面及び断面図である。FIG. 4 is a top view and a sectional view of a high-speed signal transmission circuit board showing a second embodiment of the present invention.
【図５】本発明の第３実施例を示す高速信号伝送用回路
基板の上面及び断面図である。FIG. 5 is a top view and a cross-sectional view of a high-speed signal transmission circuit board showing a third embodiment of the present invention.
１１，２１，３１ 表層の伝送ライン
１２ａ，１２ｂ，２２ａ，２２ｂ，３２ａ，３２ｂ，３
２ｃ グランド／電源プレーン
１３ａ〜１３ｄ，２３ａ〜２３ｅ，３３ａ〜３３ｆ
誘電体層
１４，２４，３４ パッド
１５，２５，３５，３７ くり抜き部
１６，２６，３６ 伝送ラインとパッドの接続部
１７，２７，２８，４１，４２ 中層の伝送ライン
１８，２９ａ，２９ｂ，３９ａ，３９ｂ 配線禁止領
域11, 21, 31 Surface transmission lines 12a, 12b, 22a, 22b, 32a, 32b, 3
2c Ground / power planes 13a to 13d, 23a to 23e, 33a to 33f
Dielectric layers 14, 24, 34 Pads 15, 25, 35, 37 Cutouts 16, 26, 36 Transmission line / pad connection parts 17, 27, 28, 41, 42 Middle-layer transmission lines 18, 29a, 29b, 39a , 39b Wiring prohibited area
Claims (4)
ンド／電源プレーンとの間に誘電体層を形成することに
よりインピーダンス整合を図る高速信号伝送用回路基板
において、 （ａ）表面に形成される第１の信号伝送用導体層と、 （ｂ）該第１の信号伝送用導体層の下方に誘電体層を介
して形成される第１のグランド／電源プレーン層と、 （ｃ）該第１のグランド／電源プレーン層の下方に誘電
体層を介して形成される第２の信号伝送用導体層と、 （ｄ）該第２の信号伝送用導体層の下方に誘電体層を介
して形成される第２のグランド／電源プレーン層と、 （ｅ）前記第１の信号伝送用導体層のパッド部のインピ
ーダンス整合を前記第１のグランド／電源プレーン層と
誘電体層で行なうために介在する前記パッド部の直下に
該パッド部より若干大きいくり抜き部と、 （ｆ）前記第２の信号伝送用導体層に、前記パッド部直
下に該パッド部より若干大きめの配線禁止領域とを設け
ることを特徴とする高速信号伝送用回路基板。1. A high-speed signal transmission circuit board for impedance matching by forming a dielectric layer between a signal transmission conductor layer and a ground / power plane formed in an intermediate layer, which is formed on the surface (a). A first signal transmission conductor layer, (b) a first ground / power plane layer formed below the first signal transmission conductor layer via a dielectric layer, and (c) the first A second signal transmission conductor layer formed below the first ground / power plane layer via a dielectric layer; and (d) below the second signal transmission conductor layer via a dielectric layer. (E) Interposed to perform impedance matching between the second ground / power plane layer and the pad portion of the first signal transmission conductor layer to be formed between the first ground / power plane layer and the dielectric layer. Immediately below the pad section A slightly larger cut out portion, (f) said second signal transmission conductor layer, high-speed signal transmission circuit board, characterized in that provided between the pad portion slightly larger routing prohibited area than the pad section immediately below.
ンド／電源プレーンとの間に誘電体層を形成することに
よりインピーダンス整合を図る高速信号伝送用回路基板
において、 （ａ）表面に形成される第１の信号伝送用導体層と、 （ｂ）該第１の信号伝送用導体層の下方に誘電体層を介
して形成される第１のグランド／電源プレーン層と、 （ｃ）該第１のグランド／電源プレーン層の下方に誘電
体層を介して形成される第２の信号伝送用導体層と、 （ｄ）該第２の信号伝送用導体層の下方に誘電体層を介
して形成される第３の信号伝送用導体層と、 （ｅ）該第３の信号伝送用導体層の下方に誘電体層を介
して形成される第２のグランド／電源プレーン層と、 （ｆ）前記信号伝送用導体層のパッド部のインピーダン
ス整合を前記第１のグランド／電源プレーン層と誘電体
層で行なうために介在する前記パッド部の直下に該パッ
ド部より若干大きいくり抜き部と、 （ｇ）前記第２及び第３の信号伝送用導体層にそれぞれ
前記パッド部直下に該パッド部より若干大きめの配線禁
止領域とを設けることを特徴とする高速信号伝送用回路
基板。2. A high-speed signal transmission circuit board for impedance matching by forming a dielectric layer between a signal transmission conductor layer and a ground / power plane formed in an intermediate layer, which is formed on the surface (a). A first signal transmission conductor layer, (b) a first ground / power plane layer formed below the first signal transmission conductor layer via a dielectric layer, and (c) the first A second signal transmission conductor layer formed below the first ground / power plane layer via a dielectric layer; and (d) below the second signal transmission conductor layer via a dielectric layer. A third conductor layer for signal transmission to be formed, and (e) a second ground / power plane layer formed below the third conductor layer for signal transmission with a dielectric layer in between, (f) Impedance matching of the pad portion of the signal transmission conductor layer is controlled by the first graph. And a power source plane layer and a dielectric layer, and a cutout portion slightly larger than the pad portion just below the pad portion, which is interposed so as to be performed, and (g) the pads on the second and third signal transmission conductor layers, respectively. A circuit board for high-speed signal transmission, characterized in that a wiring-prohibited region slightly larger than the pad portion is provided immediately below the portion.
ンド／電源プレーンとの間に誘電体層を形成することに
よりインピーダンス整合を図る高速信号伝送用回路基板
において、 （ａ）表面に形成される第１の信号伝送用導体層と、 （ｂ）該第１の信号伝送用導体層の下方に誘電体層を介
して形成される第１のグランド／電源プレーン層と、 （ｃ）該第１のグランド／電源プレーン層の下方に誘電
体層を介して形成される第２の信号伝送用導体層と、 （ｄ）該第２の信号伝送用導体層の下方に誘電体層を介
して形成される第２のグランド／電源プレーン層と、 （ｅ）該第２のグランド／電源プレーン層の下方に誘電
体層を介して形成される第３の信号伝送用導体層と、 （ｆ）該第３の信号伝送用導体層の下方に誘電体層を介
して形成される第３のグランド／電源プレーン層と、 （ｇ）該第３のグランド／電源プレーン層に下方に形成
される誘電体層と、 （ｈ）前記第１の信号伝送用導体層のパッド部のインピ
ーダンス整合を前記第１のグランド／電源プレーン層と
誘電体層で行なうために介在する前記パッド部の直下に
該パッド部より若干大きい第１のくり抜き部と、 （ｉ）前記第２の信号伝送用導体層には前記第１のくり
抜き部直下に前記パッド部より若干大きめの第１の配線
禁止領域と、 （ｊ）前記第３のグランド／電源プレーン層には前記第
１の配線禁止領域の直下に前記パッド部より若干大きい
第２のくり抜き部と、 （ｋ）前記第３の信号伝送用導体層に前記第２のくり抜
き部の直下に前記パッド部より若干大きめの第２の配線
禁止領域とを設けることを特徴とする高速信号伝送用回
路基板。3. A high-speed signal transmission circuit board for impedance matching by forming a dielectric layer between a signal transmission conductor layer and a ground / power plane formed in an intermediate layer, which is formed on the surface (a). A first signal transmission conductor layer, (b) a first ground / power plane layer formed below the first signal transmission conductor layer via a dielectric layer, and (c) the first A second signal transmission conductor layer formed below the first ground / power plane layer via a dielectric layer; and (d) below the second signal transmission conductor layer via a dielectric layer. A second ground / power plane layer formed (e) a third signal transmission conductor layer formed below the second ground / power plane layer via a dielectric layer; (f) Formed below the third conductor layer for signal transmission via a dielectric layer A third ground / power plane layer, (g) a dielectric layer formed below the third ground / power plane layer, and (h) an impedance of a pad portion of the first signal transmission conductor layer. A first hollow portion slightly larger than the pad portion, which is interposed just below the pad portion for performing matching between the first ground / power plane layer and the dielectric layer, and (i) for the second signal transmission. A first wiring prohibited area slightly larger than the pad portion is provided directly below the first cutout portion in the conductor layer, and (j) Immediately below the first wiring prohibited area in the third ground / power plane layer. A second hollow portion slightly larger than the pad portion, and (k) a second wiring prohibited region slightly larger than the pad portion just below the second hollow portion in the third signal transmission conductor layer. Is provided Speed signal transmission circuit board.
板表面から下方に向かい、徐々に大きくしていくことを
特徴とする請求項１、２又は３記載の高速信号伝送用回
路基板。4. The circuit board for high-speed signal transmission according to claim 1, wherein the hollowed-out portion and the wiring prohibited area are gradually increased downward from the surface of the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3179237A JP2654414B2 (en) | 1991-07-19 | 1991-07-19 | Circuit board for high-speed signal transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3179237A JP2654414B2 (en) | 1991-07-19 | 1991-07-19 | Circuit board for high-speed signal transmission |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0529772A true JPH0529772A (en) | 1993-02-05 |
| JP2654414B2 JP2654414B2 (en) | 1997-09-17 |
Family
ID=16062343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3179237A Expired - Lifetime JP2654414B2 (en) | 1991-07-19 | 1991-07-19 | Circuit board for high-speed signal transmission |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2654414B2 (en) |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0715148A (en) * | 1993-06-11 | 1995-01-17 | Internatl Business Mach Corp <Ibm> | Multilayer circuit board |
| US7064627B2 (en) | 2003-07-24 | 2006-06-20 | Via Technologies, Inc. | Signal transmission structure having a non-reference region for matching to a conductive ball attached to the signal transmission structure |
| JP2006173400A (en) * | 2004-12-16 | 2006-06-29 | Canon Inc | Printed wiring board |
| US7183491B2 (en) | 2003-01-27 | 2007-02-27 | Fujitsu Limited | Printed wiring board with improved impedance matching |
| JP2007123361A (en) * | 2005-10-25 | 2007-05-17 | Ricoh Co Ltd | Printed wiring board, method of adjusting impedance therein, electronic apparatus, and image formation device |
| JP2007141522A (en) * | 2005-11-15 | 2007-06-07 | Fujitsu Component Ltd | Cable connector |
| US7276668B2 (en) | 2004-02-17 | 2007-10-02 | Via Technologies, Inc. | Circuit board with mounting pads for reducing parasitic effect |
| US7307220B2 (en) * | 2005-01-12 | 2007-12-11 | Hewlett-Packard Development Company, L.P. | Circuit board for cable termination |
| JP2009010411A (en) * | 2008-08-22 | 2009-01-15 | National Institute Of Advanced Industrial & Technology | Multilayer fine wiring structure |
| JP2009200108A (en) * | 2008-02-19 | 2009-09-03 | Nec Corp | Wiring board |
| JP2010129616A (en) * | 2008-11-25 | 2010-06-10 | Samsung Electronics Co Ltd | Circuit board for high-frequency signal transmission |
| JP2010219501A (en) * | 2009-03-17 | 2010-09-30 | Hon Hai Precision Industry Co Ltd | Circuit board, and electronic apparatus having the same |
| JP4605930B2 (en) * | 2001-03-29 | 2011-01-05 | 京セラ株式会社 | High frequency semiconductor device storage package |
| JP2011082907A (en) * | 2009-10-09 | 2011-04-21 | Nec Corp | High-speed transmission wiring structure |
| JP2011514007A (en) * | 2008-03-11 | 2011-04-28 | アルカテル−ルーセント | 10GXFP compliant PCB |
| JP2013089727A (en) * | 2011-10-17 | 2013-05-13 | Fujikura Ltd | Flexible printed circuit board |
| JP2017183638A (en) * | 2016-03-31 | 2017-10-05 | Ｒｉｔａエレクトロニクス株式会社 | Multilayer printed wiring board |
| CN110996505A (en) * | 2019-12-31 | 2020-04-10 | 联想(北京)有限公司 | Printed circuit board and electronic equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5878497A (en) * | 1981-11-04 | 1983-05-12 | 日本電気株式会社 | Multilayer printed circuit board |
-
1991
- 1991-07-19 JP JP3179237A patent/JP2654414B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5878497A (en) * | 1981-11-04 | 1983-05-12 | 日本電気株式会社 | Multilayer printed circuit board |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2513443B2 (en) * | 1993-06-11 | 1996-07-03 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Multilayer circuit board assembly |
| JPH0715148A (en) * | 1993-06-11 | 1995-01-17 | Internatl Business Mach Corp <Ibm> | Multilayer circuit board |
| JP4605930B2 (en) * | 2001-03-29 | 2011-01-05 | 京セラ株式会社 | High frequency semiconductor device storage package |
| US7183491B2 (en) | 2003-01-27 | 2007-02-27 | Fujitsu Limited | Printed wiring board with improved impedance matching |
| US7064627B2 (en) | 2003-07-24 | 2006-06-20 | Via Technologies, Inc. | Signal transmission structure having a non-reference region for matching to a conductive ball attached to the signal transmission structure |
| US7276668B2 (en) | 2004-02-17 | 2007-10-02 | Via Technologies, Inc. | Circuit board with mounting pads for reducing parasitic effect |
| JP2006173400A (en) * | 2004-12-16 | 2006-06-29 | Canon Inc | Printed wiring board |
| JP4717431B2 (en) * | 2004-12-16 | 2011-07-06 | キヤノン株式会社 | Printed wiring board |
| US7307220B2 (en) * | 2005-01-12 | 2007-12-11 | Hewlett-Packard Development Company, L.P. | Circuit board for cable termination |
| JP2007123361A (en) * | 2005-10-25 | 2007-05-17 | Ricoh Co Ltd | Printed wiring board, method of adjusting impedance therein, electronic apparatus, and image formation device |
| JP2007141522A (en) * | 2005-11-15 | 2007-06-07 | Fujitsu Component Ltd | Cable connector |
| JP4673191B2 (en) * | 2005-11-15 | 2011-04-20 | 富士通コンポーネント株式会社 | Cable connector |
| JP2009200108A (en) * | 2008-02-19 | 2009-09-03 | Nec Corp | Wiring board |
| JP2011514007A (en) * | 2008-03-11 | 2011-04-28 | アルカテル−ルーセント | 10GXFP compliant PCB |
| JP2009010411A (en) * | 2008-08-22 | 2009-01-15 | National Institute Of Advanced Industrial & Technology | Multilayer fine wiring structure |
| JP2010129616A (en) * | 2008-11-25 | 2010-06-10 | Samsung Electronics Co Ltd | Circuit board for high-frequency signal transmission |
| JP2010219501A (en) * | 2009-03-17 | 2010-09-30 | Hon Hai Precision Industry Co Ltd | Circuit board, and electronic apparatus having the same |
| JP2011082907A (en) * | 2009-10-09 | 2011-04-21 | Nec Corp | High-speed transmission wiring structure |
| JP2013089727A (en) * | 2011-10-17 | 2013-05-13 | Fujikura Ltd | Flexible printed circuit board |
| JP2017183638A (en) * | 2016-03-31 | 2017-10-05 | Ｒｉｔａエレクトロニクス株式会社 | Multilayer printed wiring board |
| CN110996505A (en) * | 2019-12-31 | 2020-04-10 | 联想(北京)有限公司 | Printed circuit board and electronic equipment |
| CN110996505B (en) * | 2019-12-31 | 2022-02-18 | 联想(北京)有限公司 | Printed circuit board and electronic equipment |
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| Publication number | Publication date |
|---|---|
| JP2654414B2 (en) | 1997-09-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970513 |