JPH06260773A - Pad structure of high speed signal transmission circuit board - Google Patents
Pad structure of high speed signal transmission circuit boardInfo
- Publication number
- JPH06260773A JPH06260773A JP5041649A JP4164993A JPH06260773A JP H06260773 A JPH06260773 A JP H06260773A JP 5041649 A JP5041649 A JP 5041649A JP 4164993 A JP4164993 A JP 4164993A JP H06260773 A JPH06260773 A JP H06260773A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ground
- pad
- signal transmission
- power plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は高速信号を伝送する回路
基板のパッド部の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a pad portion of a circuit board for transmitting high speed signals.
【０００２】[0002]
【従来の技術】従来、この種の分野の技術としては、
「特願平３−１７９２３７ 高速信号伝送用回路基板」
に開示されるものがある。図５はかかる第１の従来例を
示す高速信号伝送用回路基板のパッド部の構造を示す図
であり、図５（ａ）はその高速信号伝送用回路基板のパ
ッド部の平面図、図５（ｂ）はその高速信号伝送用回路
基板のパッド部の断面図である。2. Description of the Related Art Conventionally, as a technique of this kind of field,
"Japanese Patent Application No. 3-179237 High-speed signal transmission circuit board"
Are disclosed in. FIG. 5 is a diagram showing the structure of the pad portion of the circuit board for high-speed signal transmission showing the first conventional example, and FIG. 5 (a) is a plan view of the pad portion of the circuit board for high-speed signal transmission, FIG. (B) is a cross-sectional view of a pad portion of the circuit board for high-speed signal transmission.
【０００３】これらの図に示すように、第１層（表層）
は、高速信号用ライン（以下、伝送ラインという）層で
あり、伝送ライン１、部品搭載用パッド４及び接続用パ
ッド（以下、総称してパッドという）、誘電体層３ａか
らなる。第２層はグランド／電源プレーン層であり、グ
ランド／電源プレーン２ａ、誘電体層３ｂからなる。第
３層は中層の伝送ライン層であり、中層の伝送ライン
７、誘電体層３ｃからなる。第４層はグランド／電源プ
レーン層であり、グランド／電源プレーン２ｂ、誘電体
層３ｄからなる。As shown in these figures, the first layer (surface layer)
Is a high-speed signal line (hereinafter referred to as transmission line) layer, and includes a transmission line 1, a component mounting pad 4, a connection pad (hereinafter collectively referred to as pad), and a dielectric layer 3a. The second layer is a ground / power plane layer, and is composed of a ground / power plane 2a and a dielectric layer 3b. The third layer is a middle-layer transmission line layer, and includes a middle-layer transmission line 7 and a dielectric layer 3c. The fourth layer is a ground / power plane layer, and is composed of a ground / power plane 2b and a dielectric layer 3d.
【０００４】図６は第２の従来例を示す高速信号伝送用
回路基板のパッド部の構造を示す図であり、図６（ａ）
はその高速信号伝送用回路基板のパッド部の平面図、図
６（ｂ）はその高速信号伝送用回路基板の伝送ラインの
パッド部の断面図、図７はその高速信号伝送用回路基板
の伝送ラインのパッド部の分解斜視図である。これらの
図に示すように、第１層は、伝送ライン１１、パッド１
４、誘電体層１３ａからなる。第２層はパッド１４の直
下に部分的くり抜き部１５を設けたグランド／電源プレ
ーン１２ａ、誘電体層１３ｂからなる。第３層はくり抜
き部１５より若干広めの配線禁止領域１８、中層の伝送
ライン１７、誘電体層１３ｃからなる。第４層はグラン
ド／電源プレーン１２ｂ、誘電体層１３ｄからなる。な
お、１６は伝送ラインとパッドとの接続部である。FIG. 6 is a diagram showing a structure of a pad portion of a circuit board for high-speed signal transmission showing a second conventional example, and FIG.
6B is a plan view of the pad portion of the circuit board for high-speed signal transmission, FIG. 6B is a sectional view of the pad portion of the transmission line of the circuit board for high-speed signal transmission, and FIG. 7 is transmission of the circuit board for high-speed signal transmission. It is a disassembled perspective view of the pad part of a line. As shown in these figures, the first layer includes the transmission line 11 and the pad 1.
4 and the dielectric layer 13a. The second layer is composed of a ground / power plane 12a having a partial cutout 15 provided directly below the pad 14 and a dielectric layer 13b. The third layer is composed of a wiring prohibited area 18, which is slightly wider than the cut-out portion 15, a middle-layer transmission line 17, and a dielectric layer 13c. The fourth layer comprises a ground / power plane 12b and a dielectric layer 13d. Reference numeral 16 is a connecting portion between the transmission line and the pad.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、第１の
従来例の場合、伝送ラインの幅と異なるパッドに対して
は、インピーダンス整合を行っていなかった。また、伝
送ラインをインピーダンス整合させているため、誘電体
層の厚さが先に決まっており、パッドとグランド間の誘
電体層の厚さが一定となっていることから、パッドに対
してインピーダンス整合させようとした場合、パッドの
幅を伝送ラインと同じにするより方法がないが、実際に
は部品搭載用パッドであったり、接続用パッドであった
り、そのパッド幅はまちまちであり、インピーダンス整
合が困難であるという問題点があった。However, in the case of the first conventional example, impedance matching is not performed for the pad having a width different from that of the transmission line. In addition, since the impedance of the transmission line is matched, the thickness of the dielectric layer is determined first, and the thickness of the dielectric layer between the pad and ground is constant, so the impedance to the pad is When trying to match, there is no way to make the pad width the same as the transmission line, but it is actually a component mounting pad, a connection pad, and the pad width varies, There was a problem that matching was difficult.
【０００６】この問題点を解決するために、第２の従来
例のパッド部の直下のグランドに部分的にくり抜き部を
設け、グランドまでの誘電体層の厚さを変えることで、
パッド幅を伝送ラインと同じ幅にせずにインピーダンス
整合を図ることができた。しかし、伝送ラインと誘電体
層の厚さによるインピーダンス整合の関係より、１層あ
たりの誘電体層の厚さが決まっていることから、パッド
からグランドまでの厚さは誘電体層厚の整数倍に制限さ
れ、完全なインピーダンス整合は困難であるという問題
点があった。したがって、パッド部で反射が起こり、高
速信号の伝送特性を劣化させていた。In order to solve this problem, a hollow portion is partially provided in the ground immediately below the pad portion of the second conventional example, and the thickness of the dielectric layer up to the ground is changed,
Impedance matching could be achieved without making the pad width the same as the transmission line. However, since the thickness of each dielectric layer is determined by the impedance matching relationship between the transmission line and the thickness of the dielectric layer, the thickness from the pad to the ground is an integer multiple of the dielectric layer thickness. However, there is a problem that perfect impedance matching is difficult. Therefore, reflection occurs at the pad portion, which deteriorates the transmission characteristics of high-speed signals.
【０００７】本発明は、以上述べた高速信号伝送用回路
基板のパッド部のインピーダンス整合が困難であるとい
う問題点を除去するため、伝送ラインより幅の広いパッ
ドに対して、パッドから配線の引き出し方向にパッド直
下のグランドのくり抜き部分を小さく形成して、パッド
とグランドのオーバーラップ部分を形成し、このオーバ
ーラップ量を調整することにより、インピーダンス整合
を図り、パッド部での反射の少ない高速信号伝送用回路
基板のパッド部の構造を提供することを目的とする。In order to eliminate the above-mentioned problem that it is difficult to match the impedance of the pad portion of the circuit board for high-speed signal transmission, the present invention draws a wiring from the pad to a pad wider than the transmission line. Direction, a small hollow part of the ground directly under the pad is formed to form an overlapping part of the pad and the ground, and by adjusting the amount of this overlap, impedance matching is achieved and high-speed signals with little reflection at the pad part. An object is to provide a structure of a pad portion of a transmission circuit board.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成するために、信号伝送用導体層と中層に形成したグラ
ンド／電源プレーンとの間に誘電体層を形成することに
よりインピーダンス整合を図る高速信号伝送用回路基板
のパッド部の構造において、表面に形成される幅の広い
パッド部を有する第１の信号伝送用導体層と、該第１の
信号伝送用導体層の下方に誘電体層を介して形成される
第１のグランド／電源プレーン層と、該第１のグランド
／電源プレーン層の下方に誘電体層を介して形成される
第２の信号伝送用導体層と、該第２の信号伝送用導体層
の下方に誘電体層を介して形成される第２のグランド／
電源プレーン層と、前記パッド部の直下の前記第１のグ
ランド／電源プレーン層に該パッド部の配線引き出し方
向の寸法は小さく、該パッド部の配線引き出し方向以外
の方向の寸法は若干大きく形成されるくり抜き部と、前
記第２の信号伝送用導体層に、前記第１のグランド／電
源プレーン層のくり抜き部より若干大きめの配線禁止領
域とを設けるようにしたものである。To achieve the above object, the present invention achieves impedance matching by forming a dielectric layer between a signal transmission conductor layer and a ground / power plane formed in an intermediate layer. In a structure of a pad portion of a circuit board for high-speed signal transmission intended, a first conductor layer for signal transmission having a wide pad portion formed on a surface, and a dielectric below the first conductor layer for signal transmission. A first ground / power plane layer formed via a layer, a second signal transmission conductor layer formed below the first ground / power plane layer via a dielectric layer, and A second ground formed below the second signal transmission conductor layer via a dielectric layer /
The power plane layer and the first ground / power plane layer immediately below the pad section are formed such that the dimension of the pad section in the wiring lead-out direction is small and the dimension of the pad section in a direction other than the wiring lead-out direction is slightly larger. The cutout portion and the wiring prohibited area, which is slightly larger than the cutout portion of the first ground / power plane layer, are provided in the second signal transmission conductor layer.
【０００９】また、信号伝送用導体層と中層に形成した
グランド／電源プレーンとの間に誘電体層を形成するこ
とによりインピーダンス整合を図る高速信号伝送用回路
基板において、表面に形成される幅の広いパッド部を有
する第１の信号伝送用導体層と、該第１の信号伝送用導
体層の下方に誘電体層を介して形成される第１のグラン
ド／電源プレーン層と、該第１のグランド／電源プレー
ン層の下方に誘電体層を介して形成される第２の信号伝
送用導体層と、該第２の信号伝送用導体層の下方に誘電
体層を介して形成される第２のグランド／電源プレーン
層と、該第２のグランド／電源プレーン層の下方に誘電
体層を介して形成される第３の信号伝送用導体層と、該
第３の信号伝送用導体層の下方に誘電体層を介して形成
される第３のグランド／電源プレーン層と、前記パッド
部の直下の前記第１のグランド／電源プレーン層に該パ
ッド部の配線引き出し方向の寸法は小さく、該パッド部
の配線引き出し方向以外の方向の寸法は若干大きく形成
される第１のくり抜き部と、前記第２の信号伝送用導体
層に、前記第１のくり抜き部より若干大きめの第１の配
線禁止領域と、前記パッド部の直下の前記第２のグラン
ド／電源プレーン層に該パッド部の配線引き出し方向の
寸法は若干小さく、前記パッド部の配線引き出し方向以
外の方向の寸法は前記第１のくり抜き部より若干大きく
形成される第２のくり抜き部と、前記第２の信号伝送用
導体層に、前記第２のくり抜き部より若干大きめの第２
の配線禁止領域とを設けるようにしたものである。Further, in a high-speed signal transmission circuit board for impedance matching by forming a dielectric layer between the signal transmission conductor layer and the ground / power plane formed in the middle layer, the width formed on the surface can be reduced. A first signal transmission conductor layer having a wide pad portion, a first ground / power plane layer formed below the first signal transmission conductor layer with a dielectric layer interposed therebetween, and the first signal transmission conductor layer. A second signal transmission conductor layer formed below the ground / power plane layer via a dielectric layer, and a second signal transmission layer formed below the second signal transmission conductor layer via a dielectric layer. Ground / power plane layer, a third signal transmission conductor layer formed below the second ground / power plane layer via a dielectric layer, and a third signal transmission conductor layer below the third signal transmission conductor layer. A third graph formed on the Of the pad / power plane layer and the first ground / power plane layer immediately below the pad portion, the dimension of the pad portion in the wiring lead-out direction is small, and the dimension of the pad portion in a direction other than the wiring lead-out direction is slightly large. The first cutout portion to be formed, the second signal transmission conductor layer, a first wiring prohibited region slightly larger than the first cutout portion, and the second ground immediately below the pad portion. And a second hollow portion formed in the power plane layer in which the dimension of the pad portion in the wiring lead-out direction is slightly smaller, and the dimension of the pad portion in a direction other than the wiring lead-out direction is slightly larger than the first hollow portion. The second conductor layer for signal transmission has a second layer slightly larger than the second hollow portion.
The wiring prohibited area is provided.
【００１０】[0010]
【作用】本発明によれば、上記したように、高速信号伝
送用回路基板のパッド部でパッド直下のグランド／電源
プレーンにくり抜き部を設ける際、パッドから伝送ライ
ンの引き出し方向にパッドとグランド／電源プレーンの
オーバーラップをインピーダンス整合が図れるようにく
り抜き部を形成し、パッドからグランド／電源プレーン
までの誘電体層の厚さを部分的に変化させることによ
り、インピーダンス整合を図り、反射を抑え、高速信号
の伝送特性の向上を図ることができる。According to the present invention, as described above, when the cutout portion is provided in the ground / power supply plane immediately below the pad in the pad portion of the circuit board for high-speed signal transmission, the pad and the ground / power supply line are extended from the pad to the transmission line. By forming a cutout so that the impedance of the power plane overlap can be matched, and by partially changing the thickness of the dielectric layer from the pad to the ground / power plane, impedance matching is achieved and reflection is suppressed. It is possible to improve the transmission characteristics of high-speed signals.
【００１１】[0011]
【実施例】以下、本発明の実施例について図を参照しな
がら詳細に説明する。図１は本発明の第１の実施例を示
す高速信号伝送用回路基板のパッド部の構造を示す図で
あり、図１（ａ）はその高速信号伝送用回路基板のパッ
ド部の上面図、図１（ｂ）はその高速信号伝送用回路基
板のパッド部の断面図、図２はその高速信号伝送用回路
基板のパッド部の分解斜視図である。Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing a structure of a pad portion of a circuit board for high speed signal transmission showing a first embodiment of the present invention, and FIG. 1 (a) is a top view of the pad portion of the circuit board for high speed signal transmission, 1B is a cross-sectional view of the pad portion of the high-speed signal transmission circuit board, and FIG. 2 is an exploded perspective view of the pad portion of the high-speed signal transmission circuit board.
【００１２】これらの図において、２１は表層の伝送ラ
イン、２２ａ及び２２ｂはグランド／電源プレーン、２
３ａ〜２３ｄは誘電体層、２４は表層の伝送ライン２１
のパッド、２５は第１のグランド／電源プレーン２２ａ
のくり抜き部、２６は伝送ライン２１とパッド２４の接
続部、２７は中層の伝送ライン、２８は配線禁止領域、
２９はパッド２４と第１のグランド／電源プレーン２２
ａとのオーバーラップ部である。In these figures, 21 is a surface transmission line, 22a and 22b are ground / power planes, 2
3a to 23d are dielectric layers, and 24 is a surface transmission line 21.
Pad, 25 is the first ground / power plane 22a
A hollow portion, 26 is a connecting portion between the transmission line 21 and the pad 24, 27 is a middle layer transmission line, 28 is a wiring prohibited area,
29 is the pad 24 and the first ground / power plane 22
It is an overlapping portion with a.
【００１３】ここで、表層の伝送ライン２１は、その伝
送ライン２１の幅と第１のグランド／電源プレーン２２
ａまでの厚さ、すなわち、誘電体層２３ａの厚さにより
インピーダンス整合されている。その表層の伝送ライン
２１はパッド２４に接続されている。このパッド２４
は、その表層の伝送ライン２１よりも幅が広い。そのパ
ッド２４の直下の第１のグランド／電源プレーン２２ａ
にくり抜き部２５を設ける。この際、くり抜き部２５
は、パッド２４から表層の伝送ライン２１の引き出し方
向以外はパッド２４より若干大きく、引き出し方向には
若干小さく形成する。したがって、パッド２４と第１の
グランド／電源プレーン２２ａのオーバーラップ部２９
が設けられる。Here, the transmission line 21 on the surface layer has the width of the transmission line 21 and the first ground / power plane 22.
Impedance matching is performed by the thickness up to a, that is, the thickness of the dielectric layer 23a. The transmission line 21 on the surface layer is connected to the pad 24. This pad 24
Is wider than the transmission line 21 on the surface layer. The first ground / power plane 22a immediately below the pad 24
A hollow portion 25 is provided. At this time, the hollow portion 25
Is formed to be slightly larger than the pad 24 except for the direction in which the transmission line 21 on the surface layer is extended from the pad 24, and slightly smaller in the direction in which the transmission line 21 is extended. Therefore, the pad 24 and the overlapping portion 29 of the first ground / power plane 22a
Is provided.
【００１４】また、グランド／電源プレーン２２ａ及び
２２ｂ間の中層の伝送ライン２７の信号層には、くり抜
き部２５よりも若干広めの配線禁止領域２８を設ける。
このように構成し、オーバーラップ部２９のオーバーラ
ップ量を調節することにより、表層の伝送ライン２１の
パッド２４からグランド／電源プレーン２２ｂまでの誘
電体層の厚さを部分的に変えることができ、パッド部の
インピーダンス整合を図ることができる。In the signal layer of the intermediate transmission line 27 between the ground / power supply planes 22a and 22b, a wiring prohibited area 28 which is slightly wider than the hollow portion 25 is provided.
By thus configuring and adjusting the amount of overlap of the overlap portion 29, the thickness of the dielectric layer from the pad 24 of the transmission line 21 on the surface layer to the ground / power plane 22b can be partially changed. The impedance matching of the pad portion can be achieved.
【００１５】本発明の高速信号伝送用回路基板における
特性インピーダンスのシュミレーション結果を図３に示
す。この図において、誘電率４．９の多層基板、表層の
伝送ラインの幅０．２ｍｍ、誘電体層厚０．１１ｍｍ／
層、周波数（ｆ）１０ＧＨｚの場合において、図３
（ａ）に示すような３種類のパッドサイズ、つまり、パ
ッドＡはパッド長さｌが２．５ｍｍ、パッド幅ｗが０．
３ｍｍであり、パッドＢはパッド長さｌが２．５ｍｍ、
パッド幅ｗが０．４ｍｍであり、パッドＣはパッド長さ
ｌが２．５ｍｍ、パッド幅ｗが０．５ｍｍである。FIG. 3 shows the result of simulation of characteristic impedance in the circuit board for high speed signal transmission of the present invention. In this figure, a multi-layer substrate having a dielectric constant of 4.9, a surface transmission line width of 0.2 mm, and a dielectric layer thickness of 0.11 mm /
Layer, frequency (f) 10 GHz, FIG.
3 types of pad sizes as shown in (a), that is, the pad A has a pad length 1 of 2.5 mm and a pad width w of 0.
3 mm, the pad B has a pad length 1 of 2.5 mm,
The pad width w is 0.4 mm, the pad length l of the pad C is 2.5 mm, and the pad width w is 0.5 mm.
【００１６】このようなパッドサイズでシュミレーショ
ンを行った。ここで、特性インピーダンス（Ｚ0 ）を５
０Ωにするには、図３（ｂ）の縦軸の特性インピーダン
ス５０Ωと各パッドのシュミレーション結果が交わる点
よりオーバーラップ量（Ｌ）が求まる。すなわち、パッ
ドＡ（長さが２．５ｍｍ、幅が０．３ｍｍ）の場合、オ
ーバーラップ量１．０ｍｍ、パッドＢ（長さが２．５ｍ
ｍ、幅が０．４ｍｍ）の場合、オーバーラップ量０．５
ｍｍ、パッドＣ（長さが２．５ｍｍ、幅が０．５ｍｍ）
の場合、オーバーラップ量０．２ｍｍとすれば、インピ
ーダンス整合が可能になる。Simulation was performed with such a pad size. Here, the characteristic impedance (Z 0 ) is set to 5
To obtain 0Ω, the overlap amount (L) is obtained from the point where the characteristic impedance of 50Ω on the vertical axis of FIG. 3B and the simulation result of each pad intersect. That is, in the case of pad A (length 2.5 mm, width 0.3 mm), the overlap amount 1.0 mm, pad B (length 2.5 m
m, width 0.4 mm), overlap amount 0.5
mm, pad C (length 2.5 mm, width 0.5 mm)
In the case of, if the overlap amount is 0.2 mm, impedance matching becomes possible.
【００１７】次に、本発明の第２実施例について説明す
る。図４は本発明の第２実施例を示す高速信号伝送用回
路基板のパッド部の構造を示す図であり、図４（ａ）は
その高速信号伝送用回路基板のパッド部の上面図、図４
（ｂ）はその高速信号伝送用回路基板のパッド部の断面
図である。この実施例では、表層のパッドの幅が広くな
った場合について述べる。Next, a second embodiment of the present invention will be described. FIG. 4 is a diagram showing a structure of a pad portion of a high-speed signal transmission circuit board showing a second embodiment of the present invention, and FIG. 4 (a) is a top view of the pad portion of the high-speed signal transmission circuit board. Four
(B) is a cross-sectional view of a pad portion of the circuit board for high-speed signal transmission. In this embodiment, the case where the width of the pad on the surface layer is wide is described.
【００１８】この図において、３１は表層の伝送ライ
ン、３２ａ〜３２ｃはグランド／電源プレーン、３３ａ
〜３３ｆは誘電体層、３４は表層の伝送ライン３１のパ
ッド、３５ａは第１のグランド／電源プレーン３２ａの
くり抜き部、３５ｂは第２のグランド／電源プレーン３
２ｂのくり抜き部、３６は表層の伝送ライン３１とパッ
ド３４の接続部、３７ａ及び３７ｂは中層の伝送ライ
ン、３８ａ及び３８ｂは中層の伝送ラインの配線禁止領
域、３９ａは表層の伝送ライン３１のパッド３４と第１
のグランド／電源プレーン３２ａとのオーバーラップ
部、３９ｂは表層の伝送ライン３１のパッド３４と第２
のグランド／電源プレーン３２ｂとのオーバーラップ部
である。In the figure, 31 is a surface transmission line, 32a to 32c are ground / power planes, and 33a.
33f is a dielectric layer, 34 is a pad of the transmission line 31 on the surface layer, 35a is a hollow portion of the first ground / power plane 32a, and 35b is a second ground / power plane 3.
2b is a hollow portion, 36 is a connecting portion of the surface transmission line 31 and the pad 34, 37a and 37b are middle layer transmission lines, 38a and 38b are wiring prohibited areas of the middle layer transmission line, and 39a is a pad of the surface transmission line 31. 34 and 1
Of the ground / power supply plane 32a, and 39b are the second and third pads 34 of the transmission line 31 on the surface layer.
Of the ground / power supply plane 32b.
【００１９】この実施例では、第１実施例では２層のグ
ランド／電源プレーンであったものを３層に増やし、表
層の伝送ライン３１のパッド３４と第１のグランド／電
源プレーン３２ａとのオーバーラップ部３９ａ及び表層
の伝送ライン３１のパッド３４と第２のグランド／電源
プレーン３２ｂとのオーバーラップ部３９ｂを調節する
ことにより、インピーダンス整合を図ることができる。In this embodiment, the number of ground / power planes of two layers in the first embodiment is increased to three, and the pad 34 of the transmission line 31 on the surface layer and the first ground / power plane 32a are overlaid. Impedance matching can be achieved by adjusting the overlapping portion 39b between the wrap portion 39a and the pad 34 of the surface transmission line 31 and the second ground / power supply plane 32b.
【００２０】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.
【００２１】[0021]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、高速信号伝送用回路基板のパッド部でパッド直
下のグランド／電源プレーンにくり抜き部を設ける際、
パッドから伝送ラインの引き出し方向に、パッドとグラ
ンド／電源プレーンのオーバーラップをインピーダンス
整合が図れるようにくり抜き部を形成する。As described above in detail, according to the present invention, when the hollow portion is provided in the ground / power plane immediately below the pad in the pad portion of the circuit board for high-speed signal transmission,
A cutout is formed in the direction of drawing the transmission line from the pad so that the impedance of the overlap between the pad and the ground / power plane can be matched.
【００２２】したがって、パッドからグランド／電源プ
レーンまでの誘電体層の厚さを部分的に変化させること
により、インピーダンス整合を図り、反射を抑え、高速
信号の伝送特性の向上を図ることができる。Therefore, by partially changing the thickness of the dielectric layer from the pad to the ground / power plane, impedance matching can be achieved, reflection can be suppressed, and transmission characteristics of high-speed signals can be improved.
【図１】本発明の第１の実施例を示す高速信号伝送用回
路基板のパッド部の構造を示す図である。FIG. 1 is a diagram showing a structure of a pad portion of a circuit board for high-speed signal transmission showing a first embodiment of the present invention.
【図２】本発明の第１の実施例を示す高速信号伝送用回
路基板のパッド部の分解斜視図である。FIG. 2 is an exploded perspective view of a pad portion of the high-speed signal transmission circuit board according to the first embodiment of the present invention.
【図３】本発明の高速信号伝送用回路基板における特性
インピーダンスのシュミレーション結果を示す図であ
る。FIG. 3 is a diagram showing a simulation result of characteristic impedance in the circuit board for high-speed signal transmission of the present invention.
【図４】本発明の第２の実施例を示す高速信号伝送用回
路基板のパッド部の構造を示す図である。FIG. 4 is a diagram showing a structure of a pad portion of a circuit board for high-speed signal transmission showing a second embodiment of the present invention.
【図５】第１の従来例を示す高速信号伝送用回路基板の
パッド部の構造を示す図である。FIG. 5 is a diagram showing a structure of a pad portion of a circuit board for high-speed signal transmission showing a first conventional example.
【図６】第２の従来例を示す高速信号伝送用回路基板の
パッド部の構造を示す図である。FIG. 6 is a diagram showing a structure of a pad portion of a high-speed signal transmission circuit board showing a second conventional example.
【図７】第２の従来例を示す高速信号伝送用回路基板の
伝送ラインのパッド部の分解斜視図である。FIG. 7 is an exploded perspective view of a pad portion of a transmission line of a circuit board for high-speed signal transmission showing a second conventional example.
２１，３１ 表層の伝送ライン ２２ａ，２２ｂ，３２ａ〜３２ｃ グランド／電源プ
レーン ２３ａ〜２３ｄ，３３ａ〜３３ｆ 誘電体層 ２４，３４ 表層の伝送ラインのパッド ２５，３５ａ，３５ｂ くり抜き部 ２６，３６ 伝送ラインとパッドの接続部 ２７，３７ａ，３７ｂ 中層の伝送ライン ２８，３８ａ，３８ｂ 配線禁止領域 ２９，３９ａ，３９ｂ オーバーラップ部21, 31 Surface layer transmission line 22a, 22b, 32a to 32c Ground / power plane 23a to 23d, 33a to 33f Dielectric layer 24, 34 Surface layer transmission line pad 25, 35a, 35b Cutout portion 26, 36 Transmission line and Pad connection part 27, 37a, 37b Middle layer transmission line 28, 38a, 38b Wiring prohibited area 29, 39a, 39b Overlap part
Claims (2)
ンド／電源プレーンとの間に誘電体層を形成することに
よりインピーダンス整合を図る高速信号伝送用回路基板
のパッド部の構造において、 （ａ）表面に形成される幅の広いパッド部を有する第１
の信号伝送用導体層と、 （ｂ）該第１の信号伝送用導体層の下方に誘電体層を介
して形成される第１のグランド／電源プレーン層と、 （ｃ）該第１のグランド／電源プレーン層の下方に誘電
体層を介して形成される第２の信号伝送用導体層と、 （ｄ）該第２の信号伝送用導体層の下方に誘電体層を介
して形成される第２のグランド／電源プレーン層と、 （ｅ）前記パッド部の直下の前記第１のグランド／電源
プレーン層に該パッド部の配線引き出し方向の寸法は小
さく、該パッド部の配線引き出し方向以外の方向の寸法
は若干大きく形成されるくり抜き部と、 （ｆ）前記第２の信号伝送用導体層に、前記第１のグラ
ンド／電源プレーン層のくり抜き部より若干大きめの配
線禁止領域とを設けることを特徴とする高速信号伝送用
回路基板のパッド部の構造。1. A structure of a pad portion of a high-speed signal transmission circuit board for impedance matching by forming a dielectric layer between a signal transmission conductor layer and a ground / power plane formed in an intermediate layer, comprising: ) First having a wide pad portion formed on the surface
(B) a first ground / power plane layer formed below the first signal transmission conductor layer via a dielectric layer, and (c) the first ground. / A second signal transmission conductor layer formed below the power plane layer via the dielectric layer, and (d) formed below the second signal transmission conductor layer via the dielectric layer. A second ground / power plane layer; and (e) a dimension of the pad portion on the first ground / power plane layer immediately below the pad portion in the wiring lead-out direction is small, and the dimension of the pad portion other than the wiring lead-out direction is small. The size of the direction is formed to be slightly larger, and (f) the second signal transmission conductor layer is provided with a wiring prohibited region which is slightly larger than the cutout part of the first ground / power plane layer. Of the circuit board for high-speed signal transmission characterized by The structure of the head portion.
ンド／電源プレーンとの間に誘電体層を形成することに
よりインピーダンス整合を図る高速信号伝送用回路基板
のパッド部の構造において、 （ａ）表面に形成される幅の広いパッド部を有する第１
の信号伝送用導体層と、 （ｂ）該第１の信号伝送用導体層の下方に誘電体層を介
して形成される第１のグランド／電源プレーン層と、 （ｃ）該第１のグランド／電源プレーン層の下方に誘電
体層を介して形成される第２の信号伝送用導体層と、 （ｄ）該第２の信号伝送用導体層の下方に誘電体層を介
して形成される第２のグランド／電源プレーン層と、 （ｅ）該第２のグランド／電源プレーン層の下方に誘電
体層を介して形成される第３の信号伝送用導体層と、 （ｆ）該第３の信号伝送用導体層の下方に誘電体層を介
して形成される第３のグランド／電源プレーン層と、 （ｇ）前記パッド部の直下の前記第１のグランド／電源
プレーン層に該パッド部の配線引き出し方向の寸法は小
さく、該パッド部の配線引き出し方向以外の方向の寸法
は若干大きく形成される第１のくり抜き部と、 （ｈ）前記第２の信号伝送用導体層に、前記第１のくり
抜き部より若干大きめの第１の配線禁止領域と、 （ｉ）前記パッド部の直下の前記第２のグランド／電源
プレーン層に該パッド部の配線引き出し方向の寸法は若
干小さく、前記パッド部の配線引き出し方向以外の方向
の寸法は前記第１のくり抜き部より若干大きく形成され
る第２のくり抜き部と、 （ｊ）前記第２の信号伝送用導体層に、前記第２のくり
抜き部より若干大きめの第２の配線禁止領域とを設ける
ことを特徴とする高速信号伝送用回路基板のパッド部の
構造。2. The structure of a pad portion of a high-speed signal transmission circuit board for impedance matching by forming a dielectric layer between a signal transmission conductor layer and a ground / power plane formed in an intermediate layer, wherein: ) First having a wide pad portion formed on the surface
(B) a first ground / power plane layer formed below the first signal transmission conductor layer via a dielectric layer, and (c) the first ground. / A second signal transmission conductor layer formed below the power plane layer via the dielectric layer, and (d) formed below the second signal transmission conductor layer via the dielectric layer. A second ground / power plane layer; (e) a third signal transmission conductor layer formed below the second ground / power plane layer via a dielectric layer; and (f) the third layer. A third ground / power plane layer formed below the signal transmission conductor layer via a dielectric layer, and (g) the pad portion on the first ground / power plane layer immediately below the pad portion. Is small in the wiring drawing direction, and the dimension of the pad part in a direction other than the wiring drawing direction A first hollow portion formed to be slightly larger; (h) a first wiring prohibited area slightly larger than the first hollow portion in the second signal transmission conductor layer; and (i) the pad portion. Is formed on the second ground / power plane layer immediately below the pad portion, and the dimension of the pad portion in the wiring lead-out direction is slightly smaller, and the dimension of the pad portion in the direction other than the wiring lead-out direction is formed slightly larger than that of the first hollow portion. A second hollow portion, and (j) a second wiring prohibited area, which is slightly larger than the second hollow portion, is provided in the second conductor layer for signal transmission. Circuit board pad structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5041649A JPH06260773A (en) | 1993-03-03 | 1993-03-03 | Pad structure of high speed signal transmission circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5041649A JPH06260773A (en) | 1993-03-03 | 1993-03-03 | Pad structure of high speed signal transmission circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06260773A true JPH06260773A (en) | 1994-09-16 |
Family
ID=12614206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5041649A Withdrawn JPH06260773A (en) | 1993-03-03 | 1993-03-03 | Pad structure of high speed signal transmission circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06260773A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003043085A3 (en) * | 2001-11-13 | 2003-11-06 | Ibm | Electronic device carrier adapted for transmitting high frequency signals |
| JP2006173400A (en) * | 2004-12-16 | 2006-06-29 | Canon Inc | Printed wiring board |
| JP2010206069A (en) * | 2009-03-05 | 2010-09-16 | Nec Corp | Circuit board |
| JP2010212617A (en) * | 2009-03-12 | 2010-09-24 | Sumitomo Electric Ind Ltd | Flexible wiring board |
| JP2011082907A (en) * | 2009-10-09 | 2011-04-21 | Nec Corp | High-speed transmission wiring structure |
| JP2012151365A (en) * | 2011-01-20 | 2012-08-09 | Three M Innovative Properties Co | Circuit board and electronic component including circuit board |
| KR20160149999A (en) * | 2015-06-19 | 2016-12-28 | 호시덴 가부시기가이샤 | Multilayered printed wiring board and connection structure of multilayered printed wiring board and connector |
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1993
- 1993-03-03 JP JP5041649A patent/JPH06260773A/en not_active Withdrawn
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7015574B2 (en) | 2001-11-13 | 2006-03-21 | International Business Machines Corporation | Electronic device carrier adapted for transmitting high frequency signals |
| WO2003043085A3 (en) * | 2001-11-13 | 2003-11-06 | Ibm | Electronic device carrier adapted for transmitting high frequency signals |
| JP4717431B2 (en) * | 2004-12-16 | 2011-07-06 | キヤノン株式会社 | Printed wiring board |
| JP2006173400A (en) * | 2004-12-16 | 2006-06-29 | Canon Inc | Printed wiring board |
| JP2010206069A (en) * | 2009-03-05 | 2010-09-16 | Nec Corp | Circuit board |
| JP2010212617A (en) * | 2009-03-12 | 2010-09-24 | Sumitomo Electric Ind Ltd | Flexible wiring board |
| JP2011082907A (en) * | 2009-10-09 | 2011-04-21 | Nec Corp | High-speed transmission wiring structure |
| JP2012151365A (en) * | 2011-01-20 | 2012-08-09 | Three M Innovative Properties Co | Circuit board and electronic component including circuit board |
| KR20160149999A (en) * | 2015-06-19 | 2016-12-28 | 호시덴 가부시기가이샤 | Multilayered printed wiring board and connection structure of multilayered printed wiring board and connector |
| CN106257967A (en) * | 2015-06-19 | 2016-12-28 | 星电株式会社 | Multilayer printed-wiring board and multilayer printed-wiring board and the attachment structure of adapter |
| JP2017011046A (en) * | 2015-06-19 | 2017-01-12 | ホシデン株式会社 | Multilayer printed wiring board, and connection structure of multilayer printed wiring board and connector |
| US10548220B2 (en) | 2015-06-19 | 2020-01-28 | Hosiden Corporation | Multilayer printed wiring board, and connection structure of multilayer printed wiring board and connector |
| CN106257967B (en) * | 2015-06-19 | 2020-07-03 | 星电株式会社 | Multilayer printed wiring board and connection structure of multilayer printed wiring board and connector |
| CN112738999A (en) * | 2020-10-28 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Differential signal via hole and coupling capacitor impedance continuity design method and PCB |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000509 |