JPH0371703A - Connection method for multi-layer substrate - Google Patents
Connection method for multi-layer substrateInfo
- Publication number
- JPH0371703A JPH0371703A JP1206815A JP20681589A JPH0371703A JP H0371703 A JPH0371703 A JP H0371703A JP 1206815 A JP1206815 A JP 1206815A JP 20681589 A JP20681589 A JP 20681589A JP H0371703 A JPH0371703 A JP H0371703A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- characteristic impedance
- microstrip line
- soldering land
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 title claims description 5
- 238000005476 soldering Methods 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
Landscapes
- Waveguides (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高周波回路に多層基板を用い、特定の特性イ
ンピーダンスのマイクロストリップ線路に部品接続のた
めの半田付ランドパターンを設は接続する、多層基板接
続方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention uses a multilayer board for a high frequency circuit, and connects a soldered land pattern for connecting components to a microstrip line having a specific characteristic impedance. The present invention relates to a multilayer board connection method.
特性インピーダンスの変化に板厚を変化させるという手
法でこれを応用すると、マイクロストリップ線路幅を変
えても、一定の特性インピーダンスとなるよう板厚を変
えるという手法が考えられる。なおこの種のものとして
関連するもののには例えば実開昭55−31373号公
報等が挙げられる。If we apply this method by changing the plate thickness to match the change in characteristic impedance, we can consider changing the plate thickness so that the characteristic impedance remains constant even if the microstrip line width is changed. Related examples of this type include, for example, Japanese Utility Model Application Publication No. 55-31373.
従来技術では、多層化によりマイクロストリップ線路幅
を狭くして小型化を行っているが、部品の接続には一定
の半田付ランドパターンが必要であり、ある特性インピ
ーダンスでの!iA路幅より半田付ランドパターン幅の
方が広い場合、その部分の線路幅を広くする必要がある
。しかし、パターン幅を広くすることによりこの半田付
ランドパターンによりマイクロストリップ線路の特性イ
ンピーダンスが変化し、不整合が生じる点については配
慮がされておらず5部品単品での性能は良いが接続する
と性能が劣化するという問題があった。In the conventional technology, miniaturization is achieved by narrowing the width of the microstrip line by multilayering, but a certain soldering land pattern is required to connect components, and it is necessary to use a certain characteristic impedance! If the soldering land pattern width is wider than the iA path width, it is necessary to widen the line width in that portion. However, by widening the pattern width, this soldered land pattern changes the characteristic impedance of the microstrip line, causing mismatching. There was a problem of deterioration.
〔課題を解決するための手段ゴ
上記問題点を解決するために、内層を接地導体(以下、
アースという)多層基板によるマイクロストリップ線路
に半田付ランドパターンを設けた場合、半田付ランドパ
ターン部分の内周のアースパターンを除き、下層アース
パターンにし、等価的に板厚を大きくすることにより、
同じ特性インピーダンスとするために線路幅が広くでき
、マイクロストリップ線路の特性インピーダンスの変化
が少なくて性能劣化も少なくできる。一方、半田付パタ
ーンを最適化することによりパターン強度も保たれ信頼
性を向上させることが出来る。[Means for solving the problem] In order to solve the above problem, the inner layer was grounded with a ground conductor (hereinafter referred to as
When a soldered land pattern is provided on a microstrip line made of a multilayer board (referred to as grounding), by excluding the grounding pattern on the inner periphery of the soldering land pattern and making it a lower layer grounding pattern, equivalently increasing the board thickness,
In order to maintain the same characteristic impedance, the line width can be widened, and the change in the characteristic impedance of the microstrip line is small, resulting in less performance deterioration. On the other hand, by optimizing the soldering pattern, pattern strength can be maintained and reliability can be improved.
マイクロストリップ線路の特性インピーダンスZoは、
Zo=337/(ty/h)・J’L (1+(1,7
35Er ) (w/h)−0,1+3@ )の
式から、基板の誘電率ε1.パターン幅W、基板板厚り
により決まる。また式から基板の誘電率が一定で、パタ
ーン幅と板厚の比を一定にすれば特性インピーダンスは
変わらない。従って、多層基板によるマイクロストリッ
プ線路にパターン幅の広い半田付ランドパターンを設け
ても、半田付ランドパターン部分の内層アースパターン
を除き、下層にアースパターンを設けて板厚を大きくす
ることにより、同等の特性インピーダンスが得られる。The characteristic impedance Zo of the microstrip line is
Zo=337/(ty/h)・J'L (1+(1,7
35Er) (w/h)-0,1+3@), the permittivity of the substrate is ε1. It is determined by the pattern width W and the thickness of the substrate. Also, from the equation, if the dielectric constant of the substrate is constant and the ratio of pattern width to board thickness is constant, the characteristic impedance will not change. Therefore, even if a soldering land pattern with a wide pattern width is provided on a microstrip line using a multilayer board, the same can be achieved by excluding the inner layer grounding pattern of the soldering land pattern portion and providing the grounding pattern on the lower layer to increase the board thickness. A characteristic impedance of is obtained.
また、マイクロス1−リップ線路のマイクロ波電力分布
は、接地面に対してマイクロストリップ線路のパターン
エツジからおよそ45°に広がった部分に集中している
ので、半田付ランドパターンのエツジから下層アースパ
ターンに対して45°広がった部分の内層アースパター
ンを除くことにより得られる。In addition, the microwave power distribution of the microstrip line is concentrated at an angle of about 45 degrees from the pattern edge of the microstrip line with respect to the ground plane. This is obtained by removing the inner layer ground pattern at a portion extending 45 degrees from the pattern.
以下、本発明の一実施例を第1,2図により説明する。 An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
多層基板によるマイクロストリップ線路1に部品を接続
するための半田付ランドパターン2を設けた場合、半田
付ランドパターン2の部分の内層アースパターン6を除
き、下層アースパターンをマイクロストリップ線路のア
ースパターンとすることにより、板厚を大きくした分半
田付ランドパターン2のパターン幅を広げても特性イン
ピーダンスを変えることなく、半田付ランドパターン2
を設けられ、パターンの強度も保たれ信頼性を向上させ
ることが出来る。When a soldering land pattern 2 for connecting components is provided to a microstrip line 1 made of a multilayer board, the lower layer grounding pattern can be used as the grounding pattern of the microstrip line, except for the inner layer grounding pattern 6 in the part of the soldering land pattern 2. By doing this, even if the pattern width of soldering land pattern 2 is increased by increasing the board thickness, the characteristic impedance does not change and the soldering land pattern 2
, the strength of the pattern can be maintained and reliability can be improved.
第3図は、従来一実施例を示す。第3図の場合は、半田
付ランドパターン2により特性インピーダンスが変化し
不整合が生じ性能が劣化する。FIG. 3 shows a conventional example. In the case of FIG. 3, the characteristic impedance changes due to the soldering land pattern 2, causing mismatch and deteriorating performance.
本発明によれば、多層基板におけるマイクロストリップ
線路に部品を接続するための半田付ランドパターンを設
けても、特性インピーダンスの変化を少なく、性能、信
頼性を向上させる効果がある。According to the present invention, even if a soldered land pattern for connecting components to a microstrip line on a multilayer board is provided, changes in characteristic impedance are reduced and performance and reliability are improved.
第1図は本発明の一実施例の上面図、第2図は本発明の
一実施例の断面図、第3図は従来例の斜視図である。
1・・・マイクロストリップ線路、
2・・・半田付ランドパターン、
3・・・1M基板、 4・・・2層基板、5・・
・3層基板、 6,7・・・内層パターン、8
・・・下層パターン。
第1 の
7
第2の
777゜
第5目FIG. 1 is a top view of one embodiment of the present invention, FIG. 2 is a sectional view of one embodiment of the present invention, and FIG. 3 is a perspective view of a conventional example. 1... Microstrip line, 2... Soldered land pattern, 3... 1M board, 4... 2-layer board, 5...
・3-layer board, 6, 7...inner layer pattern, 8
...lower pattern. 1st 7 2nd 777° 5th
Claims (1)
トリップ線路を形成した高周波回路の接続方法において
、部品接続のための半田付ランドを設けるために線路幅
を広くしても特性インピーダンスが変化しないよう内層
接地導体(アース)を一部分削除したことを特徴とする
多層基板の接続方法。In a high-frequency circuit connection method in which a microstrip line is formed using a conductor on the surface of a multilayer dielectric substrate, an inner layer is used to prevent the characteristic impedance from changing even if the line width is widened in order to provide soldering lands for connecting components. A method for connecting a multilayer board characterized by partially removing a ground conductor (earth).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1206815A JPH0371703A (en) | 1989-08-11 | 1989-08-11 | Connection method for multi-layer substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1206815A JPH0371703A (en) | 1989-08-11 | 1989-08-11 | Connection method for multi-layer substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0371703A true JPH0371703A (en) | 1991-03-27 |
Family
ID=16529549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1206815A Pending JPH0371703A (en) | 1989-08-11 | 1989-08-11 | Connection method for multi-layer substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0371703A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06350312A (en) * | 1993-06-04 | 1994-12-22 | Nec Corp | Connection structure between coaxial connector and multi-layer printed circuit board |
JP2001077240A (en) * | 1999-08-31 | 2001-03-23 | Kyocera Corp | High frequency wiring board and connecting structure thereof |
WO2005067095A1 (en) * | 2004-01-09 | 2005-07-21 | Nec Corporation | Coaxial line - flat substrate conversion structure and high-frequency signal converter |
JP2007123361A (en) * | 2005-10-25 | 2007-05-17 | Ricoh Co Ltd | Printed wiring board, method of adjusting impedance therein, electronic apparatus, and image formation device |
JP2007141522A (en) * | 2005-11-15 | 2007-06-07 | Fujitsu Component Ltd | Cable connector |
JP2007252221A (en) * | 2006-03-20 | 2007-10-04 | Yanmar Co Ltd | Tending machine |
JP2009054667A (en) * | 2007-08-24 | 2009-03-12 | Nec Corp | Multiplayer printed circuit board, connection structure of the multilayer printed circuit board and coaxial connector |
JP2011034317A (en) * | 2009-07-31 | 2011-02-17 | Toshiba Corp | Storage device |
CN102087719A (en) * | 2009-12-02 | 2011-06-08 | 三美电机株式会社 | Card device |
WO2022097424A1 (en) * | 2020-11-04 | 2022-05-12 | 株式会社村田製作所 | Multilayer circuit board in which signal power source separation circuit is formed |
-
1989
- 1989-08-11 JP JP1206815A patent/JPH0371703A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06350312A (en) * | 1993-06-04 | 1994-12-22 | Nec Corp | Connection structure between coaxial connector and multi-layer printed circuit board |
JP2001077240A (en) * | 1999-08-31 | 2001-03-23 | Kyocera Corp | High frequency wiring board and connecting structure thereof |
WO2005067095A1 (en) * | 2004-01-09 | 2005-07-21 | Nec Corporation | Coaxial line - flat substrate conversion structure and high-frequency signal converter |
JP2007123361A (en) * | 2005-10-25 | 2007-05-17 | Ricoh Co Ltd | Printed wiring board, method of adjusting impedance therein, electronic apparatus, and image formation device |
JP2007141522A (en) * | 2005-11-15 | 2007-06-07 | Fujitsu Component Ltd | Cable connector |
JP4673191B2 (en) * | 2005-11-15 | 2011-04-20 | 富士通コンポーネント株式会社 | Cable connector |
JP2007252221A (en) * | 2006-03-20 | 2007-10-04 | Yanmar Co Ltd | Tending machine |
JP2009054667A (en) * | 2007-08-24 | 2009-03-12 | Nec Corp | Multiplayer printed circuit board, connection structure of the multilayer printed circuit board and coaxial connector |
JP2011034317A (en) * | 2009-07-31 | 2011-02-17 | Toshiba Corp | Storage device |
CN102087719A (en) * | 2009-12-02 | 2011-06-08 | 三美电机株式会社 | Card device |
JP2011119948A (en) * | 2009-12-02 | 2011-06-16 | Mitsumi Electric Co Ltd | Card device |
WO2022097424A1 (en) * | 2020-11-04 | 2022-05-12 | 株式会社村田製作所 | Multilayer circuit board in which signal power source separation circuit is formed |
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