JPH0613181U - Circuit board for high-speed signal transmission - Google Patents

Circuit board for high-speed signal transmission

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Publication number
JPH0613181U
JPH0613181U JP5114692U JP5114692U JPH0613181U JP H0613181 U JPH0613181 U JP H0613181U JP 5114692 U JP5114692 U JP 5114692U JP 5114692 U JP5114692 U JP 5114692U JP H0613181 U JPH0613181 U JP H0613181U
Authority
JP
Japan
Prior art keywords
signal transmission
circuit board
speed signal
layer
land
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5114692U
Other languages
Japanese (ja)
Inventor
文泰 兼山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5114692U priority Critical patent/JPH0613181U/en
Publication of JPH0613181U publication Critical patent/JPH0613181U/en
Pending legal-status Critical Current

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Waveguides (AREA)

Abstract

(57)【要約】 【目的】 信号線とVIAランド間におけるインピーダ
ンスの不連続点での影響を抑え、信号の反射の少ない高
速信号伝送用回路基板構造を提供すること。 【構成】 符号1a,1bは多層基板である高速信号伝
送用回路基板の層間を電気的に接続するためのVIA、
符号2a,2b,2cはそれぞれ第1層、第2層、第3
層の概ね十字形をしたVIAランドである。各層のVI
Aランド2の形状をこのように十字型とすることによ
り、VIAランドの面積が減少し、高速信号伝送用回路
基板内に高周波信号を伝送させた場合でも、キャパシタ
ンス成分が抑えられ、インピーダンスの不連続点の発生
を減少させることができる。
(57) [Abstract] [PROBLEMS] To provide a circuit board structure for high-speed signal transmission in which the influence of impedance discontinuity between a signal line and a VIA land is suppressed and signal reflection is reduced. [Structure] Reference numerals 1a and 1b denote VIAs for electrically connecting layers of a circuit board for high-speed signal transmission, which is a multi-layer board,
Reference numerals 2a, 2b, and 2c denote the first layer, the second layer, and the third layer, respectively.
It is a VIA land that is generally cross-shaped in layers. VI of each layer
By making the shape of the A land 2 into a cross shape in this way, the area of the VIA land is reduced, and even when a high frequency signal is transmitted in the circuit board for high speed signal transmission, the capacitance component is suppressed and the impedance is not affected. The occurrence of continuous points can be reduced.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、高速信号を伝送する回路基板の構造に関するものである。 The present invention relates to a structure of a circuit board that transmits high speed signals.

【0002】[0002]

【従来の技術】[Prior art]

従来の高速信号伝送用回路基板の構造を図6に示す。図6(a),(b)は上 面図、(c)は多層基板である高速信号伝送用回路基板の断面図である。 FIG. 6 shows the structure of a conventional high-speed signal transmission circuit board. 6A and 6B are top views, and FIG. 6C is a cross-sectional view of a high-speed signal transmission circuit board which is a multilayer board.

【0003】 同図において、符号7a,7bは多層基板である高速信号伝送用回路基板の層 間を電気的に接続するためのVIAで、Au,Cu,W等の金属で埋められてい る。また、符号8a,8b,8cはVIAランドである。In FIG. 1, reference numerals 7a and 7b are VIAs for electrically connecting the layers of a high-speed signal transmission circuit board, which is a multi-layer board, and are filled with a metal such as Au, Cu, or W. Further, reference numerals 8a, 8b and 8c are VIA lands.

【0004】 これらVIAランドは、誘電体層11a,11b,11cを積層する上で、V IA7a,7bと信号線10とを電気的に確実に接続する必要がある。このため 、各層のVIAランド8は多層基板の製造過程おいて積層ずれを生じた場合でも 、確実に電気的接続ができる大きさに設計されている。In these VIA lands, when the dielectric layers 11a, 11b and 11c are stacked, it is necessary to electrically and surely connect the VIAs 7a and 7b and the signal line 10. For this reason, the VIA lands 8 of each layer are designed to have a size that enables reliable electrical connection even if a stacking error occurs in the manufacturing process of the multilayer substrate.

【0005】 図6(a)のVIAランド8aは円形、図6(b)のVIAランド8aは正方 形の形状をしている。符号9は第1層の信号線、符号10は第3層の信号線で、 符号12a,12bは電源またはアース層である。信号線9,10はストリップ ライン構造をしており、電源またはGND層12a,12b、誘電体層11a, 11bで、インピーダンスコントロールされている。The VIA land 8a of FIG. 6A has a circular shape, and the VIA land 8a of FIG. 6B has a square shape. Reference numeral 9 is a signal line of the first layer, reference numeral 10 is a signal line of the third layer, and reference numerals 12a and 12b are power supply or ground layers. The signal lines 9 and 10 have a strip line structure, and impedance is controlled by a power supply or GND layers 12a and 12b and dielectric layers 11a and 11b.

【0006】[0006]

【考案が解決しようとする課題】[Problems to be solved by the device]

しかしながら、図6に示すような高速信号伝送用回路基板に高周波信号を伝送 させた場合、VIAランドの面積が大きいためにキャパシタンス成分が大きくな る。このため、信号線とVIAランド間でインピーダンスの不連続点が発生し、 信号が反射するという問題がおこり、伝送特性が著しく劣化する。したがって、 従来の高速信号伝送用回路基板の構造では、伝送特性が劣化しない範囲での高速 化しか行えず、より高速に安定した信号伝送を行うことが出来なかった。 However, when a high-frequency signal is transmitted to the high-speed signal transmission circuit board as shown in FIG. 6, the capacitance component becomes large due to the large area of the VIA land. As a result, a discontinuity of impedance occurs between the signal line and the VIA land, causing a problem of signal reflection, and transmission characteristics are significantly deteriorated. Therefore, in the conventional structure of the circuit board for high-speed signal transmission, only high-speed operation can be performed within a range in which the transmission characteristics are not deteriorated, and stable signal transmission cannot be performed at higher speed.

【0007】 本考案はこのような従来技術の欠点を解消し、信号線とVIAランド間におけ るインピーダンスの不連続点での影響を抑え、信号の反射の少ない高速信号伝送 用回路基板を提供することを目的とする。The present invention solves the above-mentioned drawbacks of the prior art, suppresses the influence at the impedance discontinuity between the signal line and the VIA land, and provides a circuit board for high-speed signal transmission with less signal reflection. The purpose is to do.

【0008】[0008]

【課題を解決するための手段】[Means for Solving the Problems]

本考案は上記目的を達成するために、2層以上の信号伝送用導体層と2層以上 の電源またはアース層とにより回路基板が形成される高速信号伝送用回路基板に おいて、信号伝送用導体層間を接続するVIAのVIAランドは、積層ずれが生 じた場合でもVIAと電気的接続が行える大きさおよび形状を有するとともに、 VIAとの電気的接続が十分得られる範囲内でVIAランドの面積が等価的に少 なくなる形状を有する。 In order to achieve the above object, the present invention provides a high-speed signal transmission circuit board in which a circuit board is formed of two or more signal transmission conductor layers and two or more power or earth layers. The VIA land of the VIA that connects the conductor layers has a size and a shape that can be electrically connected to the VIA even if a stacking error occurs, and the VIA land of the VIA land can be sufficiently connected with the VIA land. It has a shape in which the area is equivalently reduced.

【0009】[0009]

【作用】[Action]

本考案による高速信号伝送用回路基板によれば、高速信号伝送を行ってもVI Aランドの面積が実質的に小さいため、キャパシタンス成分が抑えられる。した がって、信号線とVIAランド間のインピーダンスの不連続点での影響を少なく でき、信号劣化の無い安定した信号伝送を行うことができる。 According to the circuit board for high speed signal transmission according to the present invention, the capacitance component is suppressed because the area of the VIA land is substantially small even when high speed signal transmission is performed. Therefore, the influence at the impedance discontinuity between the signal line and the VIA land can be reduced, and stable signal transmission without signal deterioration can be performed.

【0010】[0010]

【実施例】【Example】

以下、添付図面を参照して本考案による高速信号伝送用回路基板を詳細に説明 する。 Hereinafter, a circuit board for high-speed signal transmission according to the present invention will be described in detail with reference to the accompanying drawings.

【0011】 図1は、本考案における高速信号伝送用回路基板の一実施例を示しており、( a)は上面図、(b)は多層基板である高速信号伝送用回路基板の断面図である 。FIG. 1 shows an embodiment of a high-speed signal transmission circuit board according to the present invention. (A) is a top view and (b) is a cross-sectional view of the high-speed signal transmission circuit board which is a multilayer board. is there .

【0012】 同図において、符号1a,1bは多層基板である高速信号伝送用回路基板の層 間を電気的に接続するためのVIAで、Au,Cu,W等の金属で埋められてい る。符号2a,2b,2cはそれぞれ第1層、第2層、第3層のVIAランドで あり、各層のVIAランド2は概ね十字形をしている。符号3,4はそれぞれ第 1層、第3層の信号線であり、符号5a,5bはそれぞれ第2層、第4層の電源 またはアース層である。符号6aは第1層と第2層間の第1の誘電体層、符号6 bは第2層と第3層間の第2の誘電体層、符号6cは第3層と第4層間の第3の 誘電体層である。In FIG. 1, reference numerals 1a and 1b are VIAs for electrically connecting the layers of a high-speed signal transmission circuit board, which is a multi-layer board, and are filled with a metal such as Au, Cu, or W. Reference numerals 2a, 2b, and 2c denote VIA lands of the first layer, the second layer, and the third layer, respectively, and the VIA lands 2 of each layer have a substantially cross shape. Reference numerals 3 and 4 are signal lines of the first layer and third layer, respectively, and reference numerals 5a and 5b are power source or ground layers of the second layer and fourth layer, respectively. Reference numeral 6a is a first dielectric layer between the first and second layers, reference numeral 6b is a second dielectric layer between the second and third layers, and reference numeral 6c is a third dielectric layer between the third and fourth layers. Of the dielectric layer.

【0013】 各層のVIAランド2の形状をこのように十字型とすることにより、VIAラ ンドの面積が減少し、高速信号伝送用回路基板内に高周波信号を伝送させた場合 でも、キャパシタンス成分が抑えられ、インピーダンスの不連続点の発生を減少 させることができる。By making the shape of the VIA land 2 of each layer into a cross shape in this way, the area of the VIA land is reduced, and even when a high frequency signal is transmitted in the circuit board for high speed signal transmission, the capacitance component is reduced. It can be suppressed and the occurrence of impedance discontinuity can be reduced.

【0014】 図2(a),(b)は、図1の高速信号伝送用回路基板における誘電体層6a ,6b間の積層ずれ、または信号線3の印刷ずれが生じた場合を示しており、( a)は上面図、(b)はその断面図である。このようにVIAランドの形状を十 字形にしても、積層ずれによる電気的オープンは生じることがなく、本実施例の 形状にしたことによる問題は発生しない。FIGS. 2A and 2B show a case where a stacking deviation between the dielectric layers 6 a and 6 b or a printing deviation of the signal line 3 occurs in the high-speed signal transmission circuit board of FIG. 1. , (A) is a top view and (b) is a sectional view thereof. In this way, even if the VIA land is formed in the shape of a dove, an electrical open due to the stacking error does not occur, and the problem caused by the shape of this embodiment does not occur.

【0015】 また、VIAランド2aの形状は特に十字形に限定されるものではなく、積層 ずれが生じた場合でもVIA1aと電気的接続が行える大きさおよび形状で、か つVIA1aとの電気的接続が十分得られる形状であれば良い。The shape of the VIA land 2a is not particularly limited to the cross shape, and the VIA land 2a has such a size and shape that it can be electrically connected to the VIA 1a even when a stacking error occurs, and the electrical connection to the VIA 1a is made. The shape may be such that

【0016】 すなわち、VIAランド2aの面積を減少させてキャパシタンス成分を抑え、 インピーダンスの不連続点の発生を減少させる形状として、たとえば図3に示す ような×字形でも良い。また、特に図示していないが*字形、人字形または円形 及び正方形のVIAランドに放射状に少ない本数のスリットを設けたものなど、 従来と最大長は変えないで面積を減少させる形状も考えられる。That is, as a shape that reduces the area of the VIA land 2a to suppress the capacitance component and reduces the occurrence of impedance discontinuities, for example, an X shape as shown in FIG. 3 may be used. Further, although not particularly shown, a shape which reduces the area without changing the maximum length from the conventional one, such as a * -shaped, human-shaped, circular or square VIA land provided with a small number of slits radially, may be considered.

【0017】 次に、図4を用いてVIAランド2aの形状を決める際の注意点について述べ る。図4(a)は図3に示したランド形状が、また(b)には(a)と比べて細 い線が放射状に形成されたランド形状がそれぞれ示されている。Next, points to be noted when determining the shape of the VIA land 2a will be described with reference to FIG. FIG. 4A shows the land shape shown in FIG. 3, and FIG. 4B shows the land shape in which fine lines are radially formed as compared with FIG.

【0018】 図4では、ランド面積は(b)より(a)の方が大きいように見えるが、電界 の分布により、(b)では隣接した線にカップリング効果が生じ、一本の線のよ うにはたらく。このため、(b)では等価的に見て(a)より大面積になる。し たがって、VIAランドの形状は、あまり繊細でない図1または図3のようなパ ターンが適している。In FIG. 4, the land area appears to be larger in (a) than in (b), but due to the distribution of the electric field, a coupling effect occurs in adjacent lines in (b), and the land area of Work well. Therefore, in (b), the area is equivalently larger than that in (a). Therefore, the VIA land is suitable for the pattern as shown in FIG. 1 or 3 which is not so delicate.

【0019】 また、VIAが少々ずれてもインピーダンスを一定に保ためには、中心からV IAの直径分の長さが導通部として少なくとも必要である。すなわち、図4の点 線で囲まれた範囲内を導通部とする。Further, in order to keep the impedance constant even if the VIA is slightly deviated, at least a length corresponding to the diameter of VIA from the center is required as the conducting portion. That is, the area surrounded by the dotted line in FIG.

【0020】 次に、従来のVIAと本実施例のVIAについて、3次元電磁界解析シミュレ ータを用いて解析を行なった結果を示す。図5は、その時の高速信号伝送用回路 基板のシミュレーションモデルである。すなわち、図5(a),(b)は従来の 高速信号伝送用回路基板のシミュレーションモデルであり、(a)は上面図、( b)は断面図である。また、図3(c),(d)は本考案の一実施例の高速信号 伝送用回路基板のシミュレーションモデルであり、(c)は上面図、(d)は断 面図である。 このシミュレーションにより得られた結果を表1に示す。Next, the results of analysis of the conventional VIA and the VIA of this embodiment using a three-dimensional electromagnetic field analysis simulator will be shown. FIG. 5 is a simulation model of the circuit board for high-speed signal transmission at that time. That is, FIGS. 5A and 5B are simulation models of a conventional high-speed signal transmission circuit board, FIG. 5A is a top view, and FIG. 5B is a cross-sectional view. 3 (c) and 3 (d) are simulation models of a circuit board for high-speed signal transmission according to one embodiment of the present invention, (c) is a top view and (d) is a cross-sectional view. The results obtained by this simulation are shown in Table 1.

【0021】[0021]

【表1】 [Table 1]

【0022】 このシミュレーション結果から従来のVIAと本考案のVIAのリターンロス を比べてみると、1GHz以上の周波数から差が現れ、高周波になるほど本考案 のVIAの方が良い特性であることがわかる。From this simulation result, comparing the return loss of the conventional VIA with that of the VIA of the present invention, a difference appears from a frequency of 1 GHz or higher, and the higher the frequency, the better the characteristic of the VIA of the present invention. .

【0023】 なお、本出願人は、先に特願平3−179237において、信号伝送用導体層 内の導体が電源またはアース層との距離、信号伝送用導体層内の導体幅、信号伝 送用導体層と電源またはアース層の間の誘電体の厚さによってインピーダンスが コントロールされる高速信号伝送用回路基板を提案している。本考案とこの提案 技術とを併せれば、さらに信頼性の高い、高速信号伝送用回路基板を提供するこ とが出来る。The applicant of the present application has previously described in Japanese Patent Application No. 3-179237 the distance between the conductor in the signal transmission conductor layer and the power supply or the ground layer, the conductor width in the signal transmission conductor layer, and the signal transmission. We have proposed a high-speed signal transmission circuit board whose impedance is controlled by the thickness of the dielectric between the conductor layer and the power or ground layer. By combining the present invention and this proposed technology, it is possible to provide a circuit board for high-speed signal transmission, which is more reliable.

【0024】[0024]

【考案の効果】[Effect of device]

以上詳細に説明したように本考案によれば、VIAランドの面積を等価的に見 て狭くすることにより、キャパシタンス成分が減少し、信号線とVIAランド間 のインピーダンスの不連続点の影響が抑えられ、高周波信号の反射特性を向上さ せることができる。 As described above in detail, according to the present invention, the area of the VIA land is equivalently narrowed to reduce the capacitance component and suppress the influence of the discontinuity point of the impedance between the signal line and the VIA land. As a result, the reflection characteristics of high frequency signals can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案における高速信号伝送用回路基板の実施
例を示す上面および断面図。
FIG. 1 is a top view and a sectional view showing an embodiment of a circuit board for high-speed signal transmission according to the present invention.

【図2】図1の実施例においてVIAがずれた場合の一
例を示す上面および断面図。
2A and 2B are a top view and a cross-sectional view showing an example when the VIA is displaced in the embodiment of FIG.

【図3】本考案における高速信号伝送用回路基板の他の
実施例を示す上面図。
FIG. 3 is a top view showing another embodiment of the circuit board for high speed signal transmission according to the present invention.

【図4】本考案におけるVIAランドの形状の比較例を
示す説明図。
FIG. 4 is an explanatory view showing a comparative example of the shapes of VIA lands in the present invention.

【図5】従来技術と本実施例とにおけるシュミレーショ
ンモデルを示した説明図。
FIG. 5 is an explanatory diagram showing a simulation model in the related art and the present embodiment.

【図6】従来技術におけるVIAランドの形状を示す上
面および断面図である。
6A and 6B are a top view and a cross-sectional view showing the shape of a VIA land in the conventional technique.

【符号の説明】[Explanation of symbols]

1a,1b VIA 2a,2b,2c VIAランド 3,4 信号線 5a,5b,5c 電源またはアース層 6a,6b,6c 誘電体層 1a, 1b VIA 2a, 2b, 2c VIA land 3,4 Signal line 5a, 5b, 5c Power supply or ground layer 6a, 6b, 6c Dielectric layer

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 2層以上の信号伝送用導体層と2層以上
の電源またはアース層とにより回路基板が形成される高
速信号伝送用回路基板において、 前記信号伝送用導体層間を接続するVIAのVIAラン
ドは、積層ずれが生じた場合でも前記VIAと電気的接
続が行える大きさおよび形状を有するとともに、前記V
IAとの電気的接続が十分得られる範囲内で前記VIA
ランドの面積が等価的に少なくなる形状を有することを
特徴とする高速信号伝送用回路基板。
1. A high-speed signal transmission circuit board in which a circuit board is formed by two or more signal transmission conductor layers and two or more power source or ground layers, and a VIA connecting the signal transmission conductor layers. The VIA land has such a size and shape that it can be electrically connected to the VIA even if a stacking error occurs, and
The above-mentioned VIA within a range in which electrical connection with the IA is sufficiently obtained.
A high-speed signal transmission circuit board having a shape in which the area of the land is equivalently reduced.
【請求項2】 請求項1に記載の高速信号伝送用回路基
板において、前記VIAランドの形状は概ね十字形であ
ることを特徴とする高速信号伝送用回路基板。
2. The circuit board for high speed signal transmission according to claim 1, wherein the VIA land has a substantially cross shape.
JP5114692U 1992-07-21 1992-07-21 Circuit board for high-speed signal transmission Pending JPH0613181U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5114692U JPH0613181U (en) 1992-07-21 1992-07-21 Circuit board for high-speed signal transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5114692U JPH0613181U (en) 1992-07-21 1992-07-21 Circuit board for high-speed signal transmission

Publications (1)

Publication Number Publication Date
JPH0613181U true JPH0613181U (en) 1994-02-18

Family

ID=12878689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5114692U Pending JPH0613181U (en) 1992-07-21 1992-07-21 Circuit board for high-speed signal transmission

Country Status (1)

Country Link
JP (1) JPH0613181U (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004266180A (en) * 2003-03-04 2004-09-24 Kyocera Corp Wiring board
JP2008211240A (en) * 1998-10-16 2008-09-11 Matsushita Electric Ind Co Ltd Multi-level circuit substrate, method for manufacturing the same and method for adjusting characteristic impedance therefor
JP2009239185A (en) * 2008-03-28 2009-10-15 Toppan Printing Co Ltd Build-up multilayer wiring board and manufacturing method therefor
KR20120038440A (en) * 2009-06-12 2012-04-23 3디 플러스 Method for positioning chips during the production of a reconstituted wafer
JP2019021793A (en) * 2017-07-19 2019-02-07 京セラ株式会社 Wiring board, package for electronic component, and electronic device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008211240A (en) * 1998-10-16 2008-09-11 Matsushita Electric Ind Co Ltd Multi-level circuit substrate, method for manufacturing the same and method for adjusting characteristic impedance therefor
JP4624440B2 (en) * 1998-10-16 2011-02-02 パナソニック株式会社 Multilayer circuit board, method for manufacturing the same, and method for adjusting characteristic impedance thereof
JP2004266180A (en) * 2003-03-04 2004-09-24 Kyocera Corp Wiring board
JP4508540B2 (en) * 2003-03-04 2010-07-21 京セラ株式会社 Wiring board and electronic device
JP2009239185A (en) * 2008-03-28 2009-10-15 Toppan Printing Co Ltd Build-up multilayer wiring board and manufacturing method therefor
KR20120038440A (en) * 2009-06-12 2012-04-23 3디 플러스 Method for positioning chips during the production of a reconstituted wafer
JP2012529762A (en) * 2009-06-12 2012-11-22 トロワデー、プリュ Method for positioning chips during production of reconstructed wafers
JP2019021793A (en) * 2017-07-19 2019-02-07 京セラ株式会社 Wiring board, package for electronic component, and electronic device

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